Module Definition
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Module : prim_edn_req
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.15 100.00 84.62 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_edn_req 96.15 100.00 84.62 100.00 100.00



Module Instance : tb.dut.u_edn_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.15 100.00 84.62 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.16 100.00 89.66 100.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.71 100.00 96.12 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_packer_fifo 73.08 100.00 92.31 100.00 0.00
u_prim_sync_reqack_data 95.83 100.00 83.33 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_edn_req
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN13911100.00
ALWAYS14333100.00
CONT_ASSIGN14911100.00
ALWAYS16300

53 logic word_req, word_ack; 54 1/1 assign word_req = req_i & ~ack_o; Tests: T1 T2 T3  55 56 logic [edn_pkg::ENDPOINT_BUS_WIDTH-1:0] word_data; 57 logic word_fips; 58 localparam int SyncWidth = $bits({edn_i.edn_fips, edn_i.edn_bus}); 59 prim_sync_reqack_data #( 60 .Width(SyncWidth), 61 .EnRstChks(EnRstChks), 62 .DataSrc2Dst(1'b0), 63 .DataReg(1'b0) 64 ) u_prim_sync_reqack_data ( 65 .clk_src_i ( clk_i ), 66 .rst_src_ni ( rst_ni ), 67 .clk_dst_i ( clk_edn_i ), 68 .rst_dst_ni ( rst_edn_ni ), 69 .req_chk_i ( req_chk_i ), 70 .src_req_i ( word_req ), 71 .src_ack_o ( word_ack ), 72 .dst_req_o ( edn_o.edn_req ), 73 .dst_ack_i ( edn_i.edn_ack ), 74 .data_i ( {edn_i.edn_fips, edn_i.edn_bus} ), 75 .data_o ( {word_fips, word_data} ) 76 ); 77 78 if (RepCheck) begin : gen_rep_chk 79 logic [edn_pkg::ENDPOINT_BUS_WIDTH-1:0] word_data_q; 80 always_ff @(posedge clk_i) begin 81 if (word_ack) begin 82 word_data_q <= word_data; 83 end 84 end 85 86 // do not check until we have received at least the first entry 87 logic chk_rep; 88 always_ff @(posedge clk_i or negedge rst_ni) begin 89 if (!rst_ni) begin 90 chk_rep <= '0; 91 end else if (word_ack) begin 92 chk_rep <= 1'b1; 93 end 94 end 95 96 // Need to track if any of the packed words has failed the repetition check, i.e., is identical 97 // to the last packed word. 98 logic err_d, err_q; 99 assign err_d = (req_i && ack_o) ? 1'b0 : // clear 100 (chk_rep && word_ack && word_data == word_data_q) ? 1'b1 : // set 101 err_q; // keep 102 always_ff @(posedge clk_i or negedge rst_ni) begin 103 if (!rst_ni) begin 104 err_q <= 1'b0; 105 end else begin 106 err_q <= err_d; 107 end 108 end 109 assign err_o = err_q; 110 111 end else begin : gen_no_rep_chk // block: gen_rep_chk 112 assign err_o = '0; 113 end 114 115 prim_packer_fifo #( 116 .InW(edn_pkg::ENDPOINT_BUS_WIDTH), 117 .OutW(OutWidth), 118 .ClearOnRead(1'b0) 119 ) u_prim_packer_fifo ( 120 .clk_i, 121 .rst_ni, 122 .clr_i ( 1'b0 ), // not needed 123 .wvalid_i ( word_ack ), 124 .wdata_i ( word_data ), 125 // no need for backpressure since we're always ready to 126 // sink data at this point. 127 .wready_o ( ), 128 .rvalid_o ( ack_o ), 129 .rdata_o ( data_o ), 130 // we're always ready to receive the packed output word 131 // at this point. 132 .rready_i ( 1'b1 ), 133 .depth_o ( ) 134 ); 135 136 // Need to track if any of the packed words has been generated with a pre-FIPS seed, i.e., has 137 // fips == 1'b0. 138 logic fips_d, fips_q; 139 1/1 assign fips_d = (req_i && ack_o) ? 1'b1 : // clear Tests: T1 T2 T3  140 (word_ack) ? fips_q & word_fips : // accumulate 141 fips_q; // keep 142 always_ff @(posedge clk_i or negedge rst_ni) begin 143 1/1 if (!rst_ni) begin Tests: T1 T2 T3  144 1/1 fips_q <= 1'b1; Tests: T1 T2 T3  145 end else begin 146 1/1 fips_q <= fips_d; Tests: T1 T2 T3  147 end 148 end 149 1/1 assign fips_o = fips_q; Tests: T1 T2 T3  150 151 //////////////// 152 // Assertions // 153 //////////////// 154 155 // Check EDN data is valid: Not all zeros, all ones, or not the same as previous data. 156 `ifdef INC_ASSERT 157 //VCS coverage off 158 // pragma coverage off 159 160 logic [OutWidth-1:0] data_prev, data_curr; 161 162 always_ff @(posedge ack_o or negedge rst_ni) begin 163 unreachable if (!rst_ni) begin 164 unreachable data_prev <= '0; 165 unreachable data_curr <= '0; 166 unreachable end else if (ack_o) begin 167 unreachable data_curr <= data_o; 168 unreachable data_prev <= data_curr; 169 end ==> MISSING_ELSE

Cond Coverage for Module : prim_edn_req
TotalCoveredPercent
Conditions131184.62
Logical131184.62
Non-Logical00
Event00

 LINE       54
 EXPRESSION (req_i & ((~ack_o)))
             --1--   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       139
 EXPRESSION ((req_i && ack_o) ? 1'b1 : (word_ack ? (fips_q & word_fips) : fips_q))
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 SUB-EXPRESSION (req_i && ack_o)
                 --1--    --2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       139
 SUB-EXPRESSION (word_ack ? (fips_q & word_fips) : fips_q)
                 ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 SUB-EXPRESSION (fips_q & word_fips)
                 ---1--   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T12,T13

Branch Coverage for Module : prim_edn_req
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 139 3 3 100.00
IF 143 2 2 100.00


139 assign fips_d = (req_i && ack_o) ? 1'b1 : // clear -1- ==> 140 (word_ack) ? fips_q & word_fips : // accumulate -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


143 if (!rst_ni) begin -1- 144 fips_q <= 1'b1; ==> 145 end else begin 146 fips_q <= fips_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_edn_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOutputDiffFromPrev_A 543226663 275017657 0 0
DataOutputValid_A 543226663 3929 0 0


DataOutputDiffFromPrev_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 543226663 275017657 0 0
T2 19766 18831 0 0
T3 2907 0 0 0
T4 32322 0 0 0
T5 0 19436 0 0
T6 0 32798 0 0
T9 48781 0 0 0
T10 27424 0 0 0
T11 21109 0 0 0
T12 37890 0 0 0
T13 4543 0 0 0
T14 8435 0 0 0
T18 2707 0 0 0
T25 0 13465 0 0
T26 0 76463 0 0
T27 0 13627 0 0
T28 0 15246 0 0
T29 0 12961 0 0
T165 0 127321 0 0
T166 0 57206 0 0

DataOutputValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 543226663 3929 0 0
T1 14143 1 0 0
T2 19766 142 0 0
T3 2907 1 0 0
T4 32322 41 0 0
T9 48781 1 0 0
T10 27424 1 0 0
T11 21109 1 0 0
T12 37890 1 0 0
T13 4543 1 0 0
T18 2707 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%