Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53708462	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

25454897

1

T1

184

T2

89

T3

119

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	12695063	1			T1	67		T2	22		T3	57
values[0x0]	33166358	1			T1	215		T2	152		T3	172
values[0x1]	33301938	1			T1	223		T2	162		T3	173

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46721168	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

32442191

1

T1

219

T2

116

T3

153

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	284420	1			T2	3		T10	3		T11	3
valid_sources[0x01]	245093	1			T2	2		T3	1		T10	14
valid_sources[0x02]	240171	1			T3	1		T10	9		T11	3
valid_sources[0x03]	554260	1			T2	1		T3	3		T10	11
valid_sources[0x04]	240934	1			T3	2		T10	7		T11	5
valid_sources[0x05]	245720	1			T10	15		T11	35		T17	21
valid_sources[0x06]	722487	1			T10	11		T11	1		T17	24
valid_sources[0x07]	241303	1			T2	1		T3	3		T10	13
valid_sources[0x08]	238269	1			T2	1		T3	3		T10	5
valid_sources[0x09]	244712	1			T3	2		T10	20		T11	9
valid_sources[0x0a]	728837	1			T10	7		T11	7		T17	30
valid_sources[0x0b]	241397	1			T10	3		T11	10		T17	21
valid_sources[0x0c]	238025	1			T10	10		T11	23		T17	16
valid_sources[0x0d]	241017	1			T2	1		T3	7		T10	5
valid_sources[0x0e]	243395	1			T10	6		T11	11		T17	16
valid_sources[0x0f]	241812	1			T3	4		T10	1		T11	11
valid_sources[0x10]	447983	1			T3	1		T10	18		T17	14
valid_sources[0x11]	239873	1			T3	2		T10	15		T11	15
valid_sources[0x12]	240235	1			T10	9		T11	12		T17	16
valid_sources[0x13]	240512	1			T2	1		T3	1		T10	12
valid_sources[0x14]	236874	1			T3	1		T10	4		T11	11
valid_sources[0x15]	242972	1			T3	2		T10	5		T11	6
valid_sources[0x16]	241305	1			T2	4		T3	2		T11	10
valid_sources[0x17]	244687	1			T10	7		T11	7		T17	14
valid_sources[0x18]	240360	1			T2	1		T3	2		T10	8
valid_sources[0x19]	239002	1			T10	9		T11	6		T17	14
valid_sources[0x1a]	237725	1			T3	1		T10	6		T11	14
valid_sources[0x1b]	278861	1			T3	1		T10	4		T17	18
valid_sources[0x1c]	240656	1			T2	1		T10	4		T11	15
valid_sources[0x1d]	357378	1			T3	1		T10	4		T11	3
valid_sources[0x1e]	254866	1			T2	5		T3	1		T10	11
valid_sources[0x1f]	239817	1			T3	4		T10	18		T17	18
valid_sources[0x20]	239762	1			T10	4		T11	2		T17	18
valid_sources[0x21]	240121	1			T3	4		T10	11		T11	4
valid_sources[0x22]	459364	1			T2	4		T3	2		T10	2
valid_sources[0x23]	1535690	1			T2	5		T3	1		T10	12
valid_sources[0x24]	241400	1			T3	3		T10	13		T17	24
valid_sources[0x25]	241520	1			T2	1		T10	13		T11	2
valid_sources[0x26]	244098	1			T3	3		T10	19		T11	6
valid_sources[0x27]	239089	1			T2	3		T10	11		T17	18
valid_sources[0x28]	697180	1			T2	1		T3	1		T10	15
valid_sources[0x29]	239799	1			T2	3		T10	13		T11	18
valid_sources[0x2a]	556967	1			T10	15		T11	28		T17	28
valid_sources[0x2b]	240267	1			T10	7		T11	7		T17	24
valid_sources[0x2c]	238951	1			T10	8		T11	5		T17	33
valid_sources[0x2d]	241461	1			T3	1		T10	7		T11	13
valid_sources[0x2e]	527862	1			T1	505		T2	4		T3	4
valid_sources[0x2f]	248244	1			T10	10		T11	9		T17	19
valid_sources[0x30]	239808	1			T2	1		T10	9		T11	14
valid_sources[0x31]	242122	1			T2	3		T10	7		T11	11
valid_sources[0x32]	238615	1			T2	2		T10	18		T11	17
valid_sources[0x33]	246272	1			T3	1		T10	2		T11	13
valid_sources[0x34]	248906	1			T2	1		T3	4		T10	5
valid_sources[0x35]	241778	1			T3	3		T10	2		T11	12
valid_sources[0x36]	242992	1			T3	1		T4	453		T10	9
valid_sources[0x37]	711216	1			T2	6		T3	2		T10	9
valid_sources[0x38]	501655	1			T2	1		T10	8		T11	21
valid_sources[0x39]	247734	1			T2	1		T3	4		T10	10
valid_sources[0x3a]	244881	1			T3	2		T10	7		T17	19
valid_sources[0x3b]	243052	1			T3	6		T10	7		T11	11
valid_sources[0x3c]	246431	1			T3	1		T10	4		T11	2
valid_sources[0x3d]	241720	1			T10	4		T11	26		T17	27
valid_sources[0x3e]	243376	1			T3	1		T10	8		T11	7
valid_sources[0x3f]	237290	1			T3	1		T10	3		T11	9
valid_sources[0x40]	241503	1			T3	2		T10	12		T11	2
valid_sources[0x41]	688185	1			T3	1		T10	3		T17	15
valid_sources[0x42]	250548	1			T2	4		T10	8		T11	2
valid_sources[0x43]	272019	1			T2	4		T10	5		T17	17
valid_sources[0x44]	241697	1			T2	3		T10	2		T11	5
valid_sources[0x45]	238903	1			T2	2		T3	1		T10	16
valid_sources[0x46]	285291	1			T2	1		T3	3		T10	4
valid_sources[0x47]	239226	1			T2	3		T3	7		T10	11
valid_sources[0x48]	243885	1			T2	3		T3	4		T10	13
valid_sources[0x49]	242020	1			T3	2		T10	1		T11	9
valid_sources[0x4a]	262351	1			T2	5		T10	4		T11	9
valid_sources[0x4b]	252283	1			T2	7		T3	2		T10	7
valid_sources[0x4c]	241996	1			T3	1		T10	9		T11	4
valid_sources[0x4d]	240899	1			T10	5		T11	5		T17	25
valid_sources[0x4e]	247330	1			T2	2		T10	9		T11	2
valid_sources[0x4f]	236971	1			T2	1		T3	2		T10	5
valid_sources[0x50]	439372	1			T2	1		T10	11		T17	20
valid_sources[0x51]	241683	1			T3	3		T10	9		T11	2
valid_sources[0x52]	254470	1			T2	1		T3	3		T10	12
valid_sources[0x53]	779562	1			T10	15		T11	6		T17	22
valid_sources[0x54]	241791	1			T2	2		T3	4		T10	4
valid_sources[0x55]	565992	1			T3	1		T10	17		T11	8
valid_sources[0x56]	241549	1			T11	8		T17	19		T16	39
valid_sources[0x57]	240833	1			T2	1		T3	3		T10	13
valid_sources[0x58]	237303	1			T2	1		T3	3		T10	8
valid_sources[0x59]	239314	1			T2	3		T10	3		T11	1
valid_sources[0x5a]	240709	1			T10	5		T11	7		T17	12
valid_sources[0x5b]	258253	1			T2	1		T10	13		T11	8
valid_sources[0x5c]	244456	1			T2	2		T3	2		T10	2
valid_sources[0x5d]	593760	1			T10	12		T11	4		T17	22
valid_sources[0x5e]	243411	1			T3	1		T11	16		T17	17
valid_sources[0x5f]	360156	1			T2	2		T3	2		T10	14
valid_sources[0x60]	242365	1			T3	1		T10	12		T11	2
valid_sources[0x61]	241541	1			T10	4		T11	3		T17	17
valid_sources[0x62]	240311	1			T2	5		T3	2		T10	32
valid_sources[0x63]	614751	1			T2	3		T10	7		T11	9
valid_sources[0x64]	244473	1			T3	1		T10	8		T11	6
valid_sources[0x65]	239959	1			T2	2		T3	2		T10	5
valid_sources[0x66]	243602	1			T3	1		T10	3		T11	14
valid_sources[0x67]	244438	1			T3	4		T10	22		T11	14
valid_sources[0x68]	243245	1			T3	2		T10	18		T11	1
valid_sources[0x69]	833853	1			T2	1		T3	1		T10	8
valid_sources[0x6a]	673316	1			T3	6		T10	9		T11	3
valid_sources[0x6b]	241592	1			T3	4		T10	5		T17	25
valid_sources[0x6c]	239111	1			T2	1		T3	1		T10	6
valid_sources[0x6d]	243171	1			T10	6		T11	5		T17	16
valid_sources[0x6e]	651967	1			T2	3		T3	3		T10	18
valid_sources[0x6f]	599423	1			T2	1		T3	5		T10	17
valid_sources[0x70]	252394	1			T3	3		T10	4		T11	8
valid_sources[0x71]	238351	1			T2	2		T3	1		T10	9
valid_sources[0x72]	242404	1			T3	1		T10	6		T11	10
valid_sources[0x73]	644753	1			T2	1		T10	16		T11	5
valid_sources[0x74]	241891	1			T3	3		T10	26		T11	14
valid_sources[0x75]	239920	1			T10	9		T11	13		T17	20
valid_sources[0x76]	244366	1			T2	2		T3	2		T10	13
valid_sources[0x77]	238450	1			T2	2		T3	2		T10	10
valid_sources[0x78]	246610	1			T3	2		T10	14		T11	8
valid_sources[0x79]	239710	1			T2	1		T3	2		T10	8
valid_sources[0x7a]	240483	1			T2	7		T10	5		T11	6
valid_sources[0x7b]	503547	1			T10	4		T11	3		T17	22
valid_sources[0x7c]	241105	1			T3	1		T10	6		T11	1
valid_sources[0x7d]	253940	1			T2	2		T10	1		T11	3
valid_sources[0x7e]	246684	1			T10	7		T11	3		T17	21
valid_sources[0x7f]	239652	1			T3	1		T10	12		T11	9
valid_sources[0x80]	274192	1			T3	2		T10	15		T11	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6084700

1

T1

36

T2

13

T3

27

values[0x0]

all_enables

biggest_size

12368097

1

T1

84

T2

51

T3

64

values[0x1]

all_enables

biggest_size

7002100

1

T1

64

T2

25

T3

28