Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T12
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T14
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T10

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	15547	0	0
DisabledNoTrigBkwd_A	2147483647	704563	0	0
DisabledNoTrigFwd_A	2147483647	1150046742	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15547	0	0
T2	0	414	0	0
T3	3817	1296	0	0
T4	14282	0	0	0
T5	21546	0	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T9	30914	0	0	0
T10	23711	0	0	0
T11	16619	0	0	0
T12	28713	0	0	0
T13	56933	0	0	0
T14	6822	1065	0	0
T15	26557	0	0	0
T16	36831	0	0	0
T17	35673	0	0	0
T26	21493	0	0	0
T29	70558	0	0	0
T30	58585	0	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T51	0	1195	0	0
T57	4016	577	0	0
T81	0	358	0	0
T84	24484	0	0	0
T126	0	770	0	0
T152	0	278	0	0
T239	0	1170	0	0
T240	0	915	0	0
T241	0	717	0	0
T242	0	880	0	0
T243	0	931	0	0
T244	0	1518	0	0
T245	0	620	0	0
T246	0	215	0	0
T247	0	835	0	0
T248	0	390	0	0
T249	0	405	0	0
T250	0	998	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	704563	0	0
T2	3334	0	0	0
T3	7634	30	0	0
T4	28564	0	0	0
T5	64638	0	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T10	71133	11	0	0
T11	49857	0	0	0
T12	86139	8	0	0
T13	227732	28	0	0
T14	10233	16	0	0
T15	53114	13	0	0
T16	147324	80	0	0
T17	107019	8	0	0
T23	0	2	0	0
T26	42986	0	0	0
T29	70558	79	0	0
T30	58585	11	0	0
T35	0	4	0	0
T40	0	2	0	0
T48	52907	5	0	0
T49	0	7	0	0
T51	0	16	0	0
T52	0	56	0	0
T53	0	7	0	0
T54	0	13	0	0
T55	0	90	0	0
T57	0	8	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1150046742	0	0
T1	5356	3042	0	0
T2	13336	10997	0	0
T3	15268	8681	0	0
T4	57128	2680	0	0
T5	86184	8553	0	0
T10	94844	52813	0	0
T11	66476	55642	0	0
T12	114852	95086	0	0
T13	227732	94515	0	0
T17	142692	117872	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T3 T4 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T12,T17
1	1	Covered	T1,T3,T10

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T51,T81
1	1	Covered	T1,T3,T10

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T10,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	544499054	4682	0	0
DisabledNoTrigBkwd_A	544499054	184076	0	0
DisabledNoTrigFwd_A	544499054	256715693	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	4682	0	0
T3	3817	1296	0	0
T4	14282	0	0	0
T5	21546	0	0	0
T10	23711	0	0	0
T11	16619	0	0	0
T12	28713	0	0	0
T13	56933	0	0	0
T14	3411	0	0	0
T16	36831	0	0	0
T17	35673	0	0	0
T51	0	1195	0	0
T81	0	358	0	0
T247	0	835	0	0
T250	0	998	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	184076	0	0
T3	3817	30	0	0
T4	14282	0	0	0
T5	21546	0	0	0
T10	23711	8	0	0
T11	16619	0	0	0
T12	28713	8	0	0
T13	56933	3	0	0
T14	3411	0	0	0
T16	36831	46	0	0
T17	35673	8	0	0
T29	0	7	0	0
T48	0	5	0	0
T49	0	7	0	0
T51	0	16	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	256715693	0	0
T1	1339	582	0	0
T2	3334	2718	0	0
T3	3817	2147	0	0
T4	14282	664	0	0
T5	21546	2122	0	0
T10	23711	8765	0	0
T11	16619	5938	0	0
T12	28713	20620	0	0
T13	56933	3006	0	0
T17	35673	11015	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T4 T10 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T13,T16
1	1	Covered	T4,T10,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T239,T126
1	1	Covered	T4,T10,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T13

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	544499054	4151	0	0
DisabledNoTrigBkwd_A	544499054	173188	0	0
DisabledNoTrigFwd_A	544499054	299834195	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	4151	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T9	30914	0	0	0
T14	3411	1065	0	0
T15	26557	0	0	0
T26	21493	0	0	0
T29	70558	0	0	0
T30	58585	0	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T126	0	770	0	0
T239	0	1170	0	0
T243	0	931	0	0
T246	0	215	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	173188	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T13	56933	6	0	0
T14	3411	16	0	0
T15	26557	13	0	0
T16	36831	0	0	0
T26	21493	0	0	0
T29	70558	27	0	0
T30	58585	0	0	0
T35	0	1	0	0
T40	0	2	0	0
T48	52907	0	0	0
T52	0	5	0	0
T53	0	7	0	0
T54	0	13	0	0
T55	0	47	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	299834195	0	0
T1	1339	586	0	0
T2	3334	2741	0	0
T3	3817	2167	0	0
T4	14282	668	0	0
T5	21546	2134	0	0
T10	23711	18401	0	0
T11	16619	16568	0	0
T12	28713	22908	0	0
T13	56933	31861	0	0
T17	35673	35619	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T4 T10 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T13,T26
1	1	Covered	T1,T10,T13

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T57,T241,T242
1	1	Covered	T1,T10,T13

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T13,T16

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	544499054	2969	0	0
DisabledNoTrigBkwd_A	544499054	192090	0	0
DisabledNoTrigFwd_A	544499054	277883919	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	2969	0	0
T18	248971	0	0	0
T24	21391	0	0	0
T25	86528	0	0	0
T44	183313	0	0	0
T57	4016	577	0	0
T84	24484	0	0	0
T89	3219	0	0	0
T90	21647	0	0	0
T146	8488	0	0	0
T239	2013	0	0	0
T241	0	717	0	0
T242	0	880	0	0
T248	0	390	0	0
T249	0	405	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	192090	0	0
T5	21546	0	0	0
T10	23711	3	0	0
T11	16619	0	0	0
T12	28713	0	0	0
T13	56933	19	0	0
T14	3411	0	0	0
T15	26557	0	0	0
T16	36831	34	0	0
T17	35673	0	0	0
T23	0	2	0	0
T26	21493	0	0	0
T29	0	45	0	0
T30	0	11	0	0
T35	0	3	0	0
T52	0	51	0	0
T55	0	43	0	0
T57	0	8	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	277883919	0	0
T1	1339	590	0	0
T2	3334	2761	0	0
T3	3817	2176	0	0
T4	14282	672	0	0
T5	21546	2145	0	0
T10	23711	17526	0	0
T11	16619	16568	0	0
T12	28713	28647	0	0
T13	56933	14113	0	0
T17	35673	35619	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T4 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T10,T13
1	1	Covered	T2,T10,T13

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T152,T240
1	1	Covered	T2,T10,T13

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T10,T13

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	544499054	3745	0	0
DisabledNoTrigBkwd_A	544499054	155209	0	0
DisabledNoTrigFwd_A	544499054	315612935	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	3745	0	0
T2	3334	414	0	0
T3	3817	0	0	0
T4	14282	0	0	0
T5	21546	0	0	0
T10	23711	0	0	0
T11	16619	0	0	0
T12	28713	0	0	0
T13	56933	0	0	0
T16	36831	0	0	0
T17	35673	0	0	0
T152	0	278	0	0
T240	0	915	0	0
T244	0	1518	0	0
T245	0	620	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	155209	0	0
T2	3334	6	0	0
T3	3817	0	0	0
T4	14282	0	0	0
T5	21546	0	0	0
T10	23711	2	0	0
T11	16619	0	0	0
T12	28713	0	0	0
T13	56933	3	0	0
T15	0	187	0	0
T16	36831	0	0	0
T17	35673	0	0	0
T52	0	33	0	0
T53	0	3	0	0
T54	0	3	0	0
T55	0	16	0	0
T87	0	1	0	0
T148	0	6	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	315612935	0	0
T1	1339	1284	0	0
T2	3334	2777	0	0
T3	3817	2191	0	0
T4	14282	676	0	0
T5	21546	2152	0	0
T10	23711	8121	0	0
T11	16619	16568	0	0
T12	28713	22911	0	0
T13	56933	45535	0	0
T17	35673	35619	0	0