Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.56	100.00	97.78		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.56	100.00	97.78		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.39	100.00	97.78	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T3 T4 T10 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T3 T4 T10 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T3 T4 T10 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T26 T15 T29 
159        1/1                    state_d = TimeoutSt;
           Tests:       T26 T15 T29 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T26 T15 T29 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T26 T15 T29 
172        1/1                    state_d    = Phase0St;
           Tests:       T15 T30 T31 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T15 T30 T31 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T15 T30 T31 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T15 T30 T31 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T26 T15 T29 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T26 T15 T29 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T26 T15 T29 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T26 T15 T29 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T3 T10 T12 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T3 T10 T12 
190        1/1                  esc_state_o = Phase0;
           Tests:       T3 T10 T12 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T3 T10 T12 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
194        1/1                    state_d = IdleSt;
           Tests:       T32 T33 T34 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T33 T34 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T32 T33 T34 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
198        1/1                    state_d = Phase1St;
           Tests:       T3 T10 T12 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T10 T12 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T3 T10 T12 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T3 T10 T12 
207        1/1                  esc_state_o = Phase1;
           Tests:       T3 T10 T12 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T3 T10 T12 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
211        1/1                    state_d = IdleSt;
           Tests:       T29 T35 T36 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T29 T35 T36 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T29 T35 T36 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
215        1/1                    state_d = Phase2St;
           Tests:       T3 T10 T12 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T10 T12 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T3 T10 T12 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T3 T10 T12 
224        1/1                  esc_state_o = Phase2;
           Tests:       T3 T10 T12 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T3 T10 T12 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
229        1/1                    state_d = IdleSt;
           Tests:       T31 T37 T38 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T31 T37 T38 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T31 T37 T38 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
233        1/1                    state_d = Phase3St;
           Tests:       T3 T10 T12 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T3 T10 T12 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T3 T10 T12 
241        1/1                  esc_state_o = Phase3;
           Tests:       T3 T10 T12 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T3 T10 T12 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
245        1/1                    state_d = IdleSt;
           Tests:       T13 T31 T37 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T31 T37 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T13 T31 T37 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
249        1/1                    state_d = TerminalSt;
           Tests:       T3 T10 T12 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T3 T10 T12 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
259        1/1                  esc_state_o = Terminal;
           Tests:       T3 T10 T12 
260        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
261        1/1                    state_d = IdleSt;
           Tests:       T13 T29 T30 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T6 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T6 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T6 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T6 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Covered	T3,T4,T10
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T10

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T39
1	1	1	Covered	T3,T4,T10

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T12
1	0	1	Covered	T2,T3,T13
1	1	0	Covered	T1,T26,T15
1	1	1	Covered	T26,T15,T29

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T15,T29
0	1	Covered	T15,T30,T31
1	0	Covered	T40,T37,T41

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T26,T15,T29
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T40,T37,T41

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T15,T29
1	0	Covered	T42
1	1	Covered	T15,T30,T31

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T17,T13
1	Covered	T3,T10,T12

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T12
1	Covered	T13,T29,T30

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T12
1	Covered	T10,T13,T29

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T12
1	Covered	T17,T31,T43

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T6,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T3,T10,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T3,T10,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T3,T10,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T3,T10,T12

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T6,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T10,T12
Phase1St	198	Covered	T3,T10,T12
Phase2St	215	Covered	T3,T10,T12
Phase3St	233	Covered	T3,T10,T12
TerminalSt	249	Covered	T3,T10,T12
TimeoutSt	159	Covered	T26,T15,T29

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T6,T8,T9
IdleSt->Phase0St	152	Covered	T3,T10,T12
IdleSt->TimeoutSt	159	Covered	T26,T15,T29
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T44,T32,T45
Phase0St->Phase1St	198	Covered	T3,T10,T12
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T29,T35,T25
Phase1St->Phase2St	215	Covered	T3,T10,T12
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T31,T37,T38
Phase2St->Phase3St	233	Covered	T3,T10,T12
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T13,T31,T37
Phase3St->TerminalSt	249	Covered	T3,T10,T12
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T13,T29,T30
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T26,T15,T29
TimeoutSt->Phase0St	172	Covered	T15,T30,T31

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T10
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T26,T15,T29
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T15,T30,T31
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T26,T15,T29
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T26,T15,T29
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T32,T33,T34
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T10,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T10,T12,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T29,T35,T36
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T10,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T10,T12,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T37,T38
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T10,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T10,T12,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T13,T31,T37
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T10,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T10,T12,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T13,T29,T30
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T10,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1036	0	0
CheckAccumTrig0_A	2147483647	2292	0	0
CheckAccumTrig1_A	2147483647	115	0	0
CheckClr_A	2147483647	1030	0	0
CheckEn_A	2147483647	860574872	0	0
CheckPhase0_A	2147483647	2591	0	0
CheckPhase1_A	2147483647	2534	0	0
CheckPhase2_A	2147483647	2501	0	0
CheckPhase3_A	2147483647	2456	0	0
CheckTimeout0_A	2147483647	2285	0	0
CheckTimeoutSt1_A	2147483647	291927	0	0
CheckTimeoutSt2_A	2147483647	1911	0	0
CheckTimeoutStTrig_A	2147483647	247	0	0
ErrorStAllEscAsserted_A	2147483647	5735	0	0
ErrorStIsTerminal_A	2147483647	4655	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1036	0	0
T6	135916	223	0	0
T8	153668	246	0	0
T9	123656	228	0	0
T29	282232	0	0	0
T30	234340	0	0	0
T31	210020	0	0	0
T46	0	107	0	0
T47	0	232	0	0
T48	211628	0	0	0
T49	414336	0	0	0
T50	82436	0	0	0
T51	18260	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2292	0	0
T2	3334	0	0	0
T3	7634	1	0	0
T4	28564	0	0	0
T5	64638	0	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T10	71133	2	0	0
T11	49857	0	0	0
T12	86139	1	0	0
T13	227732	10	0	0
T14	10233	1	0	0
T15	53114	0	0	0
T16	147324	2	0	0
T17	107019	1	0	0
T23	0	1	0	0
T26	42986	0	0	0
T29	70558	8	0	0
T30	58585	1	0	0
T35	0	3	0	0
T40	0	1	0	0
T48	52907	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	115	0	0
T32	76223	0	0	0
T34	0	1	0	0
T35	34333	0	0	0
T36	512139	2	0	0
T37	39609	1	0	0
T40	94005	1	0	0
T41	62389	1	0	0
T45	325915	1	0	0
T46	108252	0	0	0
T47	31117	0	0	0
T56	230699	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	2	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	18878	0	0	0
T74	191036	0	0	0
T75	67925	0	0	0
T76	41279	0	0	0
T77	13512	0	0	0
T78	148330	0	0	0
T79	23187	0	0	0
T80	91594	0	0	0
T81	1145	0	0	0
T82	185164	0	0	0
T83	545454	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1030	0	0
T6	101937	0	0	0
T8	115251	0	0	0
T13	170799	8	0	0
T14	10233	0	0	0
T15	79671	0	0	0
T16	110493	0	0	0
T23	0	3	0	0
T26	64479	0	0	0
T29	211674	5	0	0
T30	175755	1	0	0
T31	0	5	0	0
T35	34333	2	0	0
T36	0	2	0	0
T37	39609	8	0	0
T40	94005	3	0	0
T43	0	1	0	0
T46	108252	0	0	0
T47	31117	0	0	0
T48	158721	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	230699	0	0	0
T58	0	4	0	0
T59	0	1	0	0
T60	0	1	0	0
T73	18878	0	0	0
T74	191036	0	0	0
T75	67925	0	0	0
T76	41279	0	0	0
T77	0	1	0	0
T78	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	860574872	0	0
T1	5356	3041	0	0
T2	13336	10997	0	0
T3	15268	8681	0	0
T4	57128	2676	0	0
T5	86184	8549	0	0
T10	94844	32639	0	0
T11	66476	55638	0	0
T12	114852	76370	0	0
T13	227732	28536	0	0
T17	142692	109148	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2591	0	0
T2	3334	0	0	0
T3	7634	1	0	0
T4	28564	0	0	0
T5	64638	0	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T10	71133	2	0	0
T11	49857	0	0	0
T12	86139	1	0	0
T13	227732	10	0	0
T14	10233	1	0	0
T15	53114	1	0	0
T16	147324	2	0	0
T17	107019	1	0	0
T23	0	1	0	0
T26	42986	0	0	0
T29	70558	8	0	0
T30	58585	2	0	0
T31	0	5	0	0
T35	0	1	0	0
T40	0	1	0	0
T48	52907	1	0	0
T49	0	1	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	2	0	0
T87	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2534	0	0
T2	3334	0	0	0
T3	7634	1	0	0
T4	28564	0	0	0
T5	64638	0	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T10	71133	2	0	0
T11	49857	0	0	0
T12	86139	1	0	0
T13	227732	10	0	0
T14	10233	1	0	0
T15	53114	1	0	0
T16	147324	2	0	0
T17	107019	1	0	0
T23	0	1	0	0
T26	42986	0	0	0
T29	70558	7	0	0
T30	58585	2	0	0
T31	0	5	0	0
T35	0	1	0	0
T40	0	1	0	0
T48	52907	1	0	0
T49	0	1	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	2	0	0
T87	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2501	0	0
T2	3334	0	0	0
T3	7634	1	0	0
T4	28564	0	0	0
T5	64638	0	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T10	71133	2	0	0
T11	49857	0	0	0
T12	86139	1	0	0
T13	227732	10	0	0
T14	10233	1	0	0
T15	53114	1	0	0
T16	147324	2	0	0
T17	107019	1	0	0
T23	0	1	0	0
T26	42986	0	0	0
T29	70558	7	0	0
T30	58585	2	0	0
T31	0	4	0	0
T35	0	1	0	0
T40	0	1	0	0
T48	52907	1	0	0
T49	0	1	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	2	0	0
T87	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2456	0	0
T2	3334	0	0	0
T3	7634	1	0	0
T4	28564	0	0	0
T5	64638	0	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T10	71133	2	0	0
T11	49857	0	0	0
T12	86139	1	0	0
T13	227732	9	0	0
T14	10233	1	0	0
T15	53114	1	0	0
T16	147324	2	0	0
T17	107019	1	0	0
T23	0	1	0	0
T26	42986	0	0	0
T29	70558	7	0	0
T30	58585	2	0	0
T31	0	3	0	0
T35	0	1	0	0
T40	0	1	0	0
T48	52907	1	0	0
T49	0	1	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	2	0	0
T87	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2285	0	0
T6	101937	0	0	0
T7	22501	0	0	0
T8	115251	0	0	0
T9	123656	0	0	0
T15	79671	2	0	0
T25	0	3	0	0
T26	42986	3	0	0
T29	211674	1	0	0
T30	234340	2	0	0
T31	210020	13	0	0
T36	0	10	0	0
T37	0	1	0	0
T40	0	10	0	0
T41	0	1	0	0
T43	28601	0	0	0
T44	0	3	0	0
T48	158721	0	0	0
T49	414336	0	0	0
T50	41218	3	0	0
T51	4565	0	0	0
T52	54781	0	0	0
T53	0	3	0	0
T55	0	1	0	0
T76	0	7	0	0
T80	0	2	0	0
T87	0	1	0	0
T88	0	3	0	0
T89	0	1	0	0
T90	0	6	0	0
T91	0	3	0	0
T92	94296	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	291927	0	0
T6	101937	0	0	0
T7	22501	0	0	0
T8	115251	0	0	0
T9	123656	0	0	0
T15	79671	973	0	0
T25	0	344	0	0
T26	42986	180	0	0
T29	211674	178	0	0
T30	234340	195	0	0
T31	210020	1611	0	0
T36	0	3083	0	0
T37	0	4	0	0
T40	0	1052	0	0
T41	0	8	0	0
T43	28601	0	0	0
T44	0	603	0	0
T48	158721	0	0	0
T49	414336	0	0	0
T50	41218	400	0	0
T51	4565	0	0	0
T52	54781	0	0	0
T53	0	900	0	0
T55	0	154	0	0
T76	0	1216	0	0
T80	0	275	0	0
T87	0	841	0	0
T88	0	436	0	0
T89	0	53	0	0
T90	0	1139	0	0
T91	0	465	0	0
T92	94296	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1911	0	0
T6	101937	0	0	0
T7	22501	0	0	0
T8	115251	0	0	0
T9	123656	0	0	0
T15	79671	1	0	0
T25	0	2	0	0
T26	42986	3	0	0
T29	211674	1	0	0
T30	234340	1	0	0
T31	210020	8	0	0
T36	0	6	0	0
T40	0	9	0	0
T43	28601	0	0	0
T44	0	2	0	0
T48	158721	0	0	0
T49	414336	0	0	0
T50	41218	3	0	0
T51	4565	0	0	0
T52	54781	0	0	0
T53	0	2	0	0
T55	0	1	0	0
T58	0	8	0	0
T76	0	7	0	0
T80	0	2	0	0
T88	0	3	0	0
T89	0	1	0	0
T90	0	5	0	0
T91	0	2	0	0
T92	94296	0	0	0
T93	0	1	0	0
T94	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	247	0	0
T6	33979	0	0	0
T7	67503	0	0	0
T8	38417	0	0	0
T9	92742	0	0	0
T15	26557	1	0	0
T21	101058	0	0	0
T29	70558	0	0	0
T30	175755	1	0	0
T31	210020	5	0	0
T36	0	8	0	0
T43	85803	0	0	0
T44	0	1	0	0
T48	52907	0	0	0
T49	310752	0	0	0
T50	82436	0	0	0
T51	13695	0	0	0
T52	164343	0	0	0
T62	0	1	0	0
T68	0	1	0	0
T87	11710	1	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	282888	0	0	0
T95	0	3	0	0
T96	0	1	0	0
T97	0	3	0	0
T98	0	1	0	0
T99	0	3	0	0
T100	0	2	0	0
T101	0	1	0	0
T102	0	2	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	31550	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5735	0	0
T6	135916	1209	0	0
T8	153668	1374	0	0
T9	123656	1248	0	0
T29	282232	0	0	0
T30	234340	0	0	0
T31	210020	0	0	0
T46	0	630	0	0
T47	0	1274	0	0
T48	211628	0	0	0
T49	414336	0	0	0
T50	82436	0	0	0
T51	18260	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4655	0	0
T6	135916	969	0	0
T8	153668	1134	0	0
T9	123656	1008	0	0
T29	282232	0	0	0
T30	234340	0	0	0
T31	210020	0	0	0
T46	0	510	0	0
T47	0	1034	0	0
T48	211628	0	0	0
T49	414336	0	0	0
T50	82436	0	0	0
T51	18260	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5356	5136	0	0
T2	13336	13068	0	0
T3	15268	14876	0	0
T4	57128	56648	0	0
T5	86184	85464	0	0
T10	94844	94444	0	0
T11	66476	66272	0	0
T12	114852	114588	0	0
T13	227732	227336	0	0
T17	142692	142476	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5356	5136	0	0
T2	13336	13068	0	0
T3	15268	14876	0	0
T4	57128	56648	0	0
T5	86184	85464	0	0
T10	94844	94444	0	0
T11	66476	66272	0	0
T12	114852	114588	0	0
T13	227732	227336	0	0
T17	142692	142476	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T3 T10 T12 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T3 T10 T12 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T3 T10 T12 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T26 T29 T31 
159        1/1                    state_d = TimeoutSt;
           Tests:       T26 T29 T31 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T26 T29 T31 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T26 T29 T31 
172        1/1                    state_d    = Phase0St;
           Tests:       T31 T40 T37 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T31 T40 T37 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T31 T40 T37 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T31 T40 T37 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T26 T29 T31 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T26 T29 T31 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T26 T29 T50 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T26 T29 T50 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T3 T10 T12 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T3 T10 T12 
190        1/1                  esc_state_o = Phase0;
           Tests:       T3 T10 T12 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T3 T10 T12 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
194        1/1                    state_d = IdleSt;
           Tests:       T32 T33 T34 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T33 T34 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T32 T33 T34 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
198        1/1                    state_d = Phase1St;
           Tests:       T3 T10 T12 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T10 T12 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T3 T10 T12 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T3 T10 T12 
207        1/1                  esc_state_o = Phase1;
           Tests:       T3 T10 T12 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T3 T10 T12 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
211        1/1                    state_d = IdleSt;
           Tests:       T29 T35 T107 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T29 T35 T107 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T29 T35 T107 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
215        1/1                    state_d = Phase2St;
           Tests:       T3 T10 T12 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T10 T12 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T3 T10 T12 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T3 T10 T12 
224        1/1                  esc_state_o = Phase2;
           Tests:       T3 T10 T12 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T3 T10 T12 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
229        1/1                    state_d = IdleSt;
           Tests:       T31 T37 T108 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T31 T37 T108 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T31 T37 T108 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
233        1/1                    state_d = Phase3St;
           Tests:       T3 T10 T12 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T3 T10 T12 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T3 T10 T12 
241        1/1                  esc_state_o = Phase3;
           Tests:       T3 T10 T12 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T3 T10 T12 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
245        1/1                    state_d = IdleSt;
           Tests:       T31 T37 T32 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T31 T37 T32 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T31 T37 T32 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
249        1/1                    state_d = TerminalSt;
           Tests:       T3 T10 T12 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T3 T10 T12 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
259        1/1                  esc_state_o = Terminal;
           Tests:       T3 T10 T12 
260        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
261        1/1                    state_d = IdleSt;
           Tests:       T13 T31 T43 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T6 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T6 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T6 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T6 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Covered	T3,T10,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T10,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T11,T17
1	0	1	Covered	T3,T16,T48
1	1	0	Covered	T26,T15,T30
1	1	1	Covered	T26,T29,T31

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T29,T31
0	1	Covered	T31,T44,T36
1	0	Covered	T40,T37,T45

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T26,T29,T31
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T40,T37,T45

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T29,T31
1	0	Not Covered
1	1	Covered	T31,T44,T36

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T17,T13
1	Covered	T3,T12,T13

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T12
1	Covered	T13,T49,T43

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T17
1	Covered	T10,T29,T37

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T12
1	Covered	T17,T31,T43

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T6,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T3,T10,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T3,T10,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T3,T10,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T3,T10,T12

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T6,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T10,T12
Phase1St	198	Covered	T3,T10,T12
Phase2St	215	Covered	T3,T10,T12
Phase3St	233	Covered	T3,T10,T12
TerminalSt	249	Covered	T3,T10,T12
TimeoutSt	159	Covered	T26,T29,T31

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T6,T8,T9
IdleSt->Phase0St	152	Covered	T3,T10,T12
IdleSt->TimeoutSt	159	Covered	T26,T29,T31
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T44,T32,T45
Phase0St->Phase1St	198	Covered	T3,T10,T12
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T29,T35,T25
Phase1St->Phase2St	215	Covered	T3,T10,T12
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T31,T37,T108
Phase2St->Phase3St	233	Covered	T3,T10,T12
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T31,T37,T32
Phase3St->TerminalSt	249	Covered	T3,T10,T12
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T13,T31,T43
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T26,T29,T50
TimeoutSt->Phase0St	172	Covered	T31,T40,T37

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T26,T29,T31
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T31,T40,T37
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T26,T29,T31
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T26,T29,T50
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T32,T33,T34
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T10,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T10,T12,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T29,T35,T107
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T10,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T10,T12,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T37,T108
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T10,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T10,T12,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T31,T37,T32
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T10,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T10,T12,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T13,T31,T43
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T10,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	544499054	254	0	0
CheckAccumTrig0_A	544499054	893	0	0
CheckAccumTrig1_A	544499054	45	0	0
CheckClr_A	544499054	454	0	0
CheckEn_A	544261746	194169146	0	0
CheckPhase0_A	544499054	987	0	0
CheckPhase1_A	544499054	963	0	0
CheckPhase2_A	544499054	946	0	0
CheckPhase3_A	544499054	921	0	0
CheckTimeout0_A	544499054	451	0	0
CheckTimeoutSt1_A	544499054	53818	0	0
CheckTimeoutSt2_A	544499054	326	0	0
CheckTimeoutStTrig_A	544499054	78	0	0
ErrorStAllEscAsserted_A	544499054	1429	0	0
ErrorStIsTerminal_A	544499054	1159	0	0
EscStateOut_A	544257248	544184274	0	0
u_state_regs_A	544499054	544311867	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	254	0	0
T6	33979	44	0	0
T8	38417	57	0	0
T9	30914	60	0	0
T29	70558	0	0	0
T30	58585	0	0	0
T31	52505	0	0	0
T46	0	31	0	0
T47	0	62	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T50	20609	0	0	0
T51	4565	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	893	0	0
T3	3817	1	0	0
T4	14282	0	0	0
T5	21546	0	0	0
T10	23711	1	0	0
T11	16619	0	0	0
T12	28713	1	0	0
T13	56933	2	0	0
T14	3411	0	0	0
T16	36831	1	0	0
T17	35673	1	0	0
T29	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	45	0	0
T34	0	1	0	0
T35	34333	0	0	0
T37	39609	1	0	0
T40	94005	1	0	0
T45	0	1	0	0
T46	108252	0	0	0
T47	31117	0	0	0
T56	230699	0	0	0
T58	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T68	0	1	0	0
T73	18878	0	0	0
T74	191036	0	0	0
T75	67925	0	0	0
T76	41279	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	454	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T13	56933	1	0	0
T14	3411	0	0	0
T15	26557	0	0	0
T16	36831	0	0	0
T23	0	2	0	0
T26	21493	0	0	0
T29	70558	1	0	0
T30	58585	0	0	0
T31	0	5	0	0
T35	0	1	0	0
T37	0	8	0	0
T40	0	2	0	0
T43	0	1	0	0
T48	52907	0	0	0
T54	0	1	0	0
T84	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544261746	194169146	0	0
T1	1339	582	0	0
T2	3334	2718	0	0
T3	3817	2147	0	0
T4	14282	663	0	0
T5	21546	2121	0	0
T10	23711	8765	0	0
T11	16619	5937	0	0
T12	28713	1907	0	0
T13	56933	3006	0	0
T17	35673	2294	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	987	0	0
T3	3817	1	0	0
T4	14282	0	0	0
T5	21546	0	0	0
T10	23711	1	0	0
T11	16619	0	0	0
T12	28713	1	0	0
T13	56933	2	0	0
T14	3411	0	0	0
T16	36831	1	0	0
T17	35673	1	0	0
T29	0	2	0	0
T31	0	5	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	963	0	0
T3	3817	1	0	0
T4	14282	0	0	0
T5	21546	0	0	0
T10	23711	1	0	0
T11	16619	0	0	0
T12	28713	1	0	0
T13	56933	2	0	0
T14	3411	0	0	0
T16	36831	1	0	0
T17	35673	1	0	0
T29	0	1	0	0
T31	0	5	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	946	0	0
T3	3817	1	0	0
T4	14282	0	0	0
T5	21546	0	0	0
T10	23711	1	0	0
T11	16619	0	0	0
T12	28713	1	0	0
T13	56933	2	0	0
T14	3411	0	0	0
T16	36831	1	0	0
T17	35673	1	0	0
T29	0	1	0	0
T31	0	4	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	921	0	0
T3	3817	1	0	0
T4	14282	0	0	0
T5	21546	0	0	0
T10	23711	1	0	0
T11	16619	0	0	0
T12	28713	1	0	0
T13	56933	2	0	0
T14	3411	0	0	0
T16	36831	1	0	0
T17	35673	1	0	0
T29	0	1	0	0
T31	0	3	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	451	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T9	30914	0	0	0
T15	26557	0	0	0
T26	21493	3	0	0
T29	70558	1	0	0
T30	58585	0	0	0
T31	52505	5	0	0
T37	0	1	0	0
T40	0	10	0	0
T44	0	2	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T50	0	2	0	0
T55	0	1	0	0
T76	0	2	0	0
T89	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	53818	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T9	30914	0	0	0
T15	26557	0	0	0
T26	21493	180	0	0
T29	70558	178	0	0
T30	58585	0	0	0
T31	52505	265	0	0
T37	0	4	0	0
T40	0	1052	0	0
T44	0	326	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T50	0	266	0	0
T55	0	154	0	0
T76	0	332	0	0
T89	0	53	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	326	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T9	30914	0	0	0
T15	26557	0	0	0
T26	21493	3	0	0
T29	70558	1	0	0
T30	58585	0	0	0
T31	52505	0	0	0
T40	0	9	0	0
T44	0	1	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T50	0	2	0	0
T55	0	1	0	0
T76	0	2	0	0
T89	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	78	0	0
T7	22501	0	0	0
T21	101058	0	0	0
T31	52505	5	0	0
T36	0	2	0	0
T43	28601	0	0	0
T44	0	1	0	0
T50	20609	0	0	0
T51	4565	0	0	0
T52	54781	0	0	0
T68	0	1	0	0
T87	11710	0	0	0
T92	94296	0	0	0
T95	0	3	0	0
T96	0	1	0	0
T97	0	3	0	0
T98	0	1	0	0
T100	0	2	0	0
T101	0	1	0	0
T106	31550	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	1429	0	0
T6	33979	309	0	0
T8	38417	328	0	0
T9	30914	287	0	0
T29	70558	0	0	0
T30	58585	0	0	0
T31	52505	0	0	0
T46	0	162	0	0
T47	0	343	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T50	20609	0	0	0
T51	4565	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	1159	0	0
T6	33979	249	0	0
T8	38417	268	0	0
T9	30914	227	0	0
T29	70558	0	0	0
T30	58585	0	0	0
T31	52505	0	0	0
T46	0	132	0	0
T47	0	283	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T50	20609	0	0	0
T51	4565	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544257248	544184274	0	0
T1	1339	1284	0	0
T2	3334	3267	0	0
T3	3817	3719	0	0
T4	14282	14162	0	0
T5	21546	21366	0	0
T10	23711	23611	0	0
T11	16619	16568	0	0
T12	28713	28647	0	0
T13	56933	56834	0	0
T17	35673	35619	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	544311867	0	0
T1	1339	1284	0	0
T2	3334	3267	0	0
T3	3817	3719	0	0
T4	14282	14162	0	0
T5	21546	21366	0	0
T10	23711	23611	0	0
T11	16619	16568	0	0
T12	28713	28647	0	0
T13	56933	56834	0	0
T17	35673	35619	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T10 T13 T16 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T10 T13 T16 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T10 T13 T16 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T30 T31 T87 
159        1/1                    state_d = TimeoutSt;
           Tests:       T30 T31 T87 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T30 T31 T87 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T30 T31 T87 
172        1/1                    state_d    = Phase0St;
           Tests:       T30 T87 T53 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T30 T87 T53 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T30 T87 T53 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T30 T87 T53 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T30 T31 T87 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T30 T31 T87 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T30 T31 T53 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T30 T31 T53 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T13 T16 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T10 T13 T16 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T10 T13 T16 
190        1/1                  esc_state_o = Phase0;
           Tests:       T10 T13 T16 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T10 T13 T16 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T10 T13 T16 
194        1/1                    state_d = IdleSt;
           Tests:       T109 T110 T111 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T109 T110 T111 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T109 T110 T111 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T13 T16 
198        1/1                    state_d = Phase1St;
           Tests:       T10 T13 T16 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T13 T16 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T13 T16 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T13 T16 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T10 T13 T16 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T10 T13 T16 
207        1/1                  esc_state_o = Phase1;
           Tests:       T10 T13 T16 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T10 T13 T16 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T10 T13 T16 
211        1/1                    state_d = IdleSt;
           Tests:       T60 T112 T113 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T60 T112 T113 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T60 T112 T113 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T13 T16 
215        1/1                    state_d = Phase2St;
           Tests:       T10 T13 T16 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T13 T16 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T13 T16 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T13 T16 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T10 T13 T16 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T10 T13 T16 
224        1/1                  esc_state_o = Phase2;
           Tests:       T10 T13 T16 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T10 T13 T16 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T10 T13 T16 
229        1/1                    state_d = IdleSt;
           Tests:       T38 T114 T115 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T38 T114 T115 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T38 T114 T115 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T13 T16 
233        1/1                    state_d = Phase3St;
           Tests:       T10 T13 T16 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T13 T16 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T13 T16 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T10 T13 T16 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T10 T13 T16 
241        1/1                  esc_state_o = Phase3;
           Tests:       T10 T13 T16 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T10 T13 T16 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T10 T13 T16 
245        1/1                    state_d = IdleSt;
           Tests:       T13 T116 T117 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T116 T117 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T13 T116 T117 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T13 T16 
249        1/1                    state_d = TerminalSt;
           Tests:       T10 T13 T16 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T13 T16 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T10 T13 T16 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T10 T13 T16 
259        1/1                  esc_state_o = Terminal;
           Tests:       T10 T13 T16 
260        1/1                  if (clr_i) begin
           Tests:       T10 T13 T16 
261        1/1                    state_d = IdleSt;
           Tests:       T13 T29 T30 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T6 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T6 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T6 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T6 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Covered	T10,T13,T16
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T13,T16

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T10,T13,T16

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T13,T29
1	0	1	Covered	T16,T52,T54
1	1	0	Covered	T26,T15,T50
1	1	1	Covered	T30,T31,T87

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T87
0	1	Covered	T30,T87,T53
1	0	Covered	T36,T118,T66

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T30,T31,T87
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T36,T118,T66

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T30,T31,T87
1	0	Not Covered
1	1	Covered	T30,T87,T53

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T13,T29,T30
1	Covered	T10,T16,T55

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T16,T29
1	Covered	T13,T30,T119

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T10,T13,T16
1	Covered	T29,T87,T53

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T10,T13,T16
1	Covered	T52,T35,T119

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T6,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T10,T13,T87

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T13,T16,T30

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T13,T16,T29

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T13,T16,T29

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T6,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T10,T13,T16
Phase1St	198	Covered	T10,T13,T16
Phase2St	215	Covered	T10,T13,T16
Phase3St	233	Covered	T10,T13,T16
TerminalSt	249	Covered	T10,T13,T16
TimeoutSt	159	Covered	T30,T31,T87

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T6,T8,T9
IdleSt->Phase0St	152	Covered	T10,T13,T16
IdleSt->TimeoutSt	159	Covered	T30,T31,T87
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T36,T109,T110
Phase0St->Phase1St	198	Covered	T10,T13,T16
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T45,T60,T112
Phase1St->Phase2St	215	Covered	T10,T13,T16
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T38,T114,T115
Phase2St->Phase3St	233	Covered	T10,T13,T16
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T13,T116,T117
Phase3St->TerminalSt	249	Covered	T10,T13,T16
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T13,T29,T30
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T30,T31,T53
TimeoutSt->Phase0St	172	Covered	T30,T87,T53

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T13,T16
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T30,T31,T87
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T30,T87,T53
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T30,T31,T87
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T30,T31,T53
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T109,T110,T111
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T10,T13,T16
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T10,T13,T16
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T60,T112,T113
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T10,T13,T16
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T10,T13,T16
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T38,T114,T115
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T10,T13,T16
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T10,T13,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T13,T116,T117
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T10,T13,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T10,T13,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T13,T29,T30
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T10,T13,T16
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	544499054	270	0	0
CheckAccumTrig0_A	544499054	469	0	0
CheckAccumTrig1_A	544499054	23	0	0
CheckClr_A	544499054	195	0	0
CheckEn_A	544261746	216113014	0	0
CheckPhase0_A	544499054	547	0	0
CheckPhase1_A	544499054	537	0	0
CheckPhase2_A	544499054	533	0	0
CheckPhase3_A	544499054	526	0	0
CheckTimeout0_A	544499054	728	0	0
CheckTimeoutSt1_A	544499054	88774	0	0
CheckTimeoutSt2_A	544499054	641	0	0
CheckTimeoutStTrig_A	544499054	61	0	0
ErrorStAllEscAsserted_A	544499054	1397	0	0
ErrorStIsTerminal_A	544499054	1127	0	0
EscStateOut_A	544257248	544184274	0	0
u_state_regs_A	544499054	544311867	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	270	0	0
T6	33979	55	0	0
T8	38417	62	0	0
T9	30914	75	0	0
T29	70558	0	0	0
T30	58585	0	0	0
T31	52505	0	0	0
T46	0	25	0	0
T47	0	53	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T50	20609	0	0	0
T51	4565	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	469	0	0
T5	21546	0	0	0
T10	23711	1	0	0
T11	16619	0	0	0
T12	28713	0	0	0
T13	56933	7	0	0
T14	3411	0	0	0
T15	26557	0	0	0
T16	36831	1	0	0
T17	35673	0	0	0
T23	0	1	0	0
T26	21493	0	0	0
T29	0	5	0	0
T30	0	1	0	0
T35	0	2	0	0
T52	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	23	0	0
T36	512139	1	0	0
T38	138418	0	0	0
T58	392548	0	0	0
T66	0	1	0	0
T70	0	1	0	0
T99	0	2	0	0
T114	0	1	0	0
T120	0	1	0	0
T121	0	2	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	608260	0	0	0
T126	1845	0	0	0
T127	226593	0	0	0
T128	71013	0	0	0
T129	108865	0	0	0
T130	26922	0	0	0
T131	4195	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	195	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T13	56933	7	0	0
T14	3411	0	0	0
T15	26557	0	0	0
T16	36831	0	0	0
T19	0	1	0	0
T23	0	1	0	0
T26	21493	0	0	0
T29	70558	4	0	0
T30	58585	1	0	0
T35	0	1	0	0
T41	0	1	0	0
T48	52907	0	0	0
T53	0	1	0	0
T119	0	4	0	0
T132	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544261746	216113014	0	0
T1	1339	590	0	0
T2	3334	2761	0	0
T3	3817	2176	0	0
T4	14282	671	0	0
T5	21546	2144	0	0
T10	23711	2726	0	0
T11	16619	16567	0	0
T12	28713	28646	0	0
T13	56933	14113	0	0
T17	35673	35618	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	547	0	0
T5	21546	0	0	0
T10	23711	1	0	0
T11	16619	0	0	0
T12	28713	0	0	0
T13	56933	7	0	0
T14	3411	0	0	0
T15	26557	0	0	0
T16	36831	1	0	0
T17	35673	0	0	0
T23	0	1	0	0
T26	21493	0	0	0
T29	0	5	0	0
T30	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T87	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	537	0	0
T5	21546	0	0	0
T10	23711	1	0	0
T11	16619	0	0	0
T12	28713	0	0	0
T13	56933	7	0	0
T14	3411	0	0	0
T15	26557	0	0	0
T16	36831	1	0	0
T17	35673	0	0	0
T23	0	1	0	0
T26	21493	0	0	0
T29	0	5	0	0
T30	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T87	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	533	0	0
T5	21546	0	0	0
T10	23711	1	0	0
T11	16619	0	0	0
T12	28713	0	0	0
T13	56933	7	0	0
T14	3411	0	0	0
T15	26557	0	0	0
T16	36831	1	0	0
T17	35673	0	0	0
T23	0	1	0	0
T26	21493	0	0	0
T29	0	5	0	0
T30	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T87	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	526	0	0
T5	21546	0	0	0
T10	23711	1	0	0
T11	16619	0	0	0
T12	28713	0	0	0
T13	56933	6	0	0
T14	3411	0	0	0
T15	26557	0	0	0
T16	36831	1	0	0
T17	35673	0	0	0
T23	0	1	0	0
T26	21493	0	0	0
T29	0	5	0	0
T30	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T87	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	728	0	0
T7	22501	0	0	0
T9	30914	0	0	0
T25	0	2	0	0
T30	58585	2	0	0
T31	52505	8	0	0
T43	28601	0	0	0
T44	0	1	0	0
T49	103584	0	0	0
T50	20609	0	0	0
T51	4565	0	0	0
T52	54781	0	0	0
T53	0	2	0	0
T76	0	2	0	0
T87	0	1	0	0
T88	0	3	0	0
T90	0	4	0	0
T92	94296	0	0	0
T119	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	88774	0	0
T7	22501	0	0	0
T9	30914	0	0	0
T25	0	237	0	0
T30	58585	195	0	0
T31	52505	1346	0	0
T43	28601	0	0	0
T44	0	277	0	0
T49	103584	0	0	0
T50	20609	0	0	0
T51	4565	0	0	0
T52	54781	0	0	0
T53	0	93	0	0
T76	0	347	0	0
T87	0	841	0	0
T88	0	436	0	0
T90	0	844	0	0
T92	94296	0	0	0
T119	0	35	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	641	0	0
T7	22501	0	0	0
T9	30914	0	0	0
T25	0	1	0	0
T30	58585	1	0	0
T31	52505	8	0	0
T43	28601	0	0	0
T44	0	1	0	0
T49	103584	0	0	0
T50	20609	0	0	0
T51	4565	0	0	0
T52	54781	0	0	0
T53	0	1	0	0
T76	0	2	0	0
T88	0	3	0	0
T90	0	4	0	0
T92	94296	0	0	0
T94	0	2	0	0
T119	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	61	0	0
T7	22501	0	0	0
T9	30914	0	0	0
T30	58585	1	0	0
T31	52505	0	0	0
T32	0	1	0	0
T36	0	3	0	0
T43	28601	0	0	0
T49	103584	0	0	0
T50	20609	0	0	0
T51	4565	0	0	0
T52	54781	0	0	0
T53	0	1	0	0
T58	0	1	0	0
T87	0	1	0	0
T92	94296	0	0	0
T99	0	1	0	0
T107	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	1397	0	0
T6	33979	306	0	0
T8	38417	336	0	0
T9	30914	318	0	0
T29	70558	0	0	0
T30	58585	0	0	0
T31	52505	0	0	0
T46	0	140	0	0
T47	0	297	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T50	20609	0	0	0
T51	4565	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	1127	0	0
T6	33979	246	0	0
T8	38417	276	0	0
T9	30914	258	0	0
T29	70558	0	0	0
T30	58585	0	0	0
T31	52505	0	0	0
T46	0	110	0	0
T47	0	237	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T50	20609	0	0	0
T51	4565	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544257248	544184274	0	0
T1	1339	1284	0	0
T2	3334	3267	0	0
T3	3817	3719	0	0
T4	14282	14162	0	0
T5	21546	21366	0	0
T10	23711	23611	0	0
T11	16619	16568	0	0
T12	28713	28647	0	0
T13	56933	56834	0	0
T17	35673	35619	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	544311867	0	0
T1	1339	1284	0	0
T2	3334	3267	0	0
T3	3817	3719	0	0
T4	14282	14162	0	0
T5	21546	21366	0	0
T10	23711	23611	0	0
T11	16619	16568	0	0
T12	28713	28647	0	0
T13	56933	56834	0	0
T17	35673	35619	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T2 T10 T13 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T2 T10 T13 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T2 T10 T13 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T26 T30 T31 
159        1/1                    state_d = TimeoutSt;
           Tests:       T26 T30 T31 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T26 T30 T31 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T26 T30 T31 
172        1/1                    state_d    = Phase0St;
           Tests:       T30 T87 T25 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T30 T87 T25 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T30 T87 T25 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T30 T87 T25 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T26 T30 T31 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T26 T30 T31 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T26 T31 T50 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T26 T31 T50 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T10 T13 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T2 T10 T13 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T2 T10 T13 
190        1/1                  esc_state_o = Phase0;
           Tests:       T2 T10 T13 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T2 T10 T13 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T2 T10 T13 
194        1/1                    state_d = IdleSt;
           Tests:       T135 T136 T137 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T135 T136 T137 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T135 T136 T137 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T10 T13 
198        1/1                    state_d = Phase1St;
           Tests:       T2 T10 T13 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T10 T13 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T10 T13 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T10 T13 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T2 T10 T13 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T2 T10 T13 
207        1/1                  esc_state_o = Phase1;
           Tests:       T2 T10 T13 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T2 T10 T13 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T2 T10 T13 
211        1/1                    state_d = IdleSt;
           Tests:       T138 T139 T140 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T138 T139 T140 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T138 T139 T140 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T10 T13 
215        1/1                    state_d = Phase2St;
           Tests:       T2 T10 T13 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T10 T13 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T10 T13 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T10 T13 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T2 T10 T13 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T2 T10 T13 
224        1/1                  esc_state_o = Phase2;
           Tests:       T2 T10 T13 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T2 T10 T13 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T2 T10 T13 
229        1/1                    state_d = IdleSt;
           Tests:       T141 T142 T143 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T141 T142 T143 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T141 T142 T143 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T10 T13 
233        1/1                    state_d = Phase3St;
           Tests:       T2 T10 T13 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T10 T13 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T10 T13 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T2 T10 T13 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T2 T10 T13 
241        1/1                  esc_state_o = Phase3;
           Tests:       T2 T10 T13 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T2 T10 T13 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T2 T10 T13 
245        1/1                    state_d = IdleSt;
           Tests:       T144 T145 T72 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T144 T145 T72 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T144 T145 T72 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T10 T13 
249        1/1                    state_d = TerminalSt;
           Tests:       T2 T10 T13 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T10 T13 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T2 T10 T13 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T2 T10 T13 
259        1/1                  esc_state_o = Terminal;
           Tests:       T2 T10 T13 
260        1/1                  if (clr_i) begin
           Tests:       T2 T10 T13 
261        1/1                    state_d = IdleSt;
           Tests:       T13 T146 T147 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T6 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T6 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T6 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T6 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Covered	T2,T10,T13
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T26
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T10,T13

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T13

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T26
1	0	1	Covered	T2,T13,T16
1	1	0	Covered	T1,T26,T29
1	1	1	Covered	T26,T30,T31

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T30,T31
0	1	Covered	T30,T25,T83
1	0	Covered	T87,T119,T34

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T26,T30,T31
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T87,T119,T34

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T30,T31
1	0	Not Covered
1	1	Covered	T30,T25,T83

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T13,T15
1	Covered	T2,T13,T52

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T10,T13
1	Covered	T15,T53,T148

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T10,T13
1	Covered	T30,T119,T149

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T13,T15
1	Covered	T10,T13,T54

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T6,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T2,T10,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T2,T10,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T2,T13,T30

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T2,T10,T13

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T6,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T10,T13
Phase1St	198	Covered	T2,T10,T13
Phase2St	215	Covered	T2,T10,T13
Phase3St	233	Covered	T2,T10,T13
TerminalSt	249	Covered	T2,T10,T13
TimeoutSt	159	Covered	T26,T30,T31

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T6,T8,T9
IdleSt->Phase0St	152	Covered	T2,T10,T13
IdleSt->TimeoutSt	159	Covered	T26,T30,T31
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T36,T60,T150
Phase0St->Phase1St	198	Covered	T2,T10,T13
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T138,T151,T139
Phase1St->Phase2St	215	Covered	T2,T10,T13
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T141,T142,T143
Phase2St->Phase3St	233	Covered	T2,T10,T13
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T144,T145,T72
Phase3St->TerminalSt	249	Covered	T2,T10,T13
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T13,T148,T23
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T26,T31,T50
TimeoutSt->Phase0St	172	Covered	T30,T87,T25

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T13
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T26,T30,T31
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T30,T87,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T26,T30,T31
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T26,T31,T50
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T135,T136,T137
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T10,T13
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T10,T13,T15
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T138,T139,T140
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T10,T13
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T10,T13,T15
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T141,T142,T143
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T10,T13
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T10,T13,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T144,T145,T72
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T10,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T10,T13,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T13,T146,T147
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T10,T13
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	544499054	282	0	0
CheckAccumTrig0_A	544499054	488	0	0
CheckAccumTrig1_A	544499054	19	0	0
CheckClr_A	544499054	203	0	0
CheckEn_A	544261746	231329921	0	0
CheckPhase0_A	544499054	545	0	0
CheckPhase1_A	544499054	534	0	0
CheckPhase2_A	544499054	528	0	0
CheckPhase3_A	544499054	521	0	0
CheckTimeout0_A	544499054	605	0	0
CheckTimeoutSt1_A	544499054	72265	0	0
CheckTimeoutSt2_A	544499054	529	0	0
CheckTimeoutStTrig_A	544499054	53	0	0
ErrorStAllEscAsserted_A	544499054	1457	0	0
ErrorStIsTerminal_A	544499054	1187	0	0
EscStateOut_A	544257248	544184274	0	0
u_state_regs_A	544499054	544311867	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	282	0	0
T6	33979	75	0	0
T8	38417	70	0	0
T9	30914	54	0	0
T29	70558	0	0	0
T30	58585	0	0	0
T31	52505	0	0	0
T46	0	32	0	0
T47	0	51	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T50	20609	0	0	0
T51	4565	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	488	0	0
T2	3334	1	0	0
T3	3817	0	0	0
T4	14282	0	0	0
T5	21546	0	0	0
T10	23711	1	0	0
T11	16619	0	0	0
T12	28713	0	0	0
T13	56933	2	0	0
T15	0	1	0	0
T16	36831	0	0	0
T17	35673	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T148	0	1	0	0
T152	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	19	0	0
T21	101058	0	0	0
T34	0	1	0	0
T53	63199	0	0	0
T54	45788	0	0	0
T55	119194	0	0	0
T69	0	1	0	0
T87	11710	1	0	0
T88	39085	0	0	0
T106	31550	0	0	0
T109	0	1	0	0
T119	0	1	0	0
T121	0	1	0	0
T148	78553	0	0	0
T151	0	1	0	0
T152	1013	0	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	79124	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	203	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T13	56933	1	0	0
T14	3411	0	0	0
T15	26557	0	0	0
T16	36831	0	0	0
T26	21493	0	0	0
T29	70558	0	0	0
T30	58585	0	0	0
T48	52907	0	0	0
T60	0	3	0	0
T62	0	6	0	0
T86	0	1	0	0
T118	0	1	0	0
T138	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544261746	231329921	0	0
T1	1339	1283	0	0
T2	3334	2777	0	0
T3	3817	2191	0	0
T4	14282	675	0	0
T5	21546	2151	0	0
T10	23711	2748	0	0
T11	16619	16567	0	0
T12	28713	22910	0	0
T13	56933	3069	0	0
T17	35673	35618	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	545	0	0
T2	3334	1	0	0
T3	3817	0	0	0
T4	14282	0	0	0
T5	21546	0	0	0
T10	23711	1	0	0
T11	16619	0	0	0
T12	28713	0	0	0
T13	56933	2	0	0
T15	0	1	0	0
T16	36831	0	0	0
T17	35673	0	0	0
T30	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T87	0	1	0	0
T148	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	534	0	0
T2	3334	1	0	0
T3	3817	0	0	0
T4	14282	0	0	0
T5	21546	0	0	0
T10	23711	1	0	0
T11	16619	0	0	0
T12	28713	0	0	0
T13	56933	2	0	0
T15	0	1	0	0
T16	36831	0	0	0
T17	35673	0	0	0
T30	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T87	0	1	0	0
T148	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	528	0	0
T2	3334	1	0	0
T3	3817	0	0	0
T4	14282	0	0	0
T5	21546	0	0	0
T10	23711	1	0	0
T11	16619	0	0	0
T12	28713	0	0	0
T13	56933	2	0	0
T15	0	1	0	0
T16	36831	0	0	0
T17	35673	0	0	0
T30	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T87	0	1	0	0
T148	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	521	0	0
T2	3334	1	0	0
T3	3817	0	0	0
T4	14282	0	0	0
T5	21546	0	0	0
T10	23711	1	0	0
T11	16619	0	0	0
T12	28713	0	0	0
T13	56933	2	0	0
T15	0	1	0	0
T16	36831	0	0	0
T17	35673	0	0	0
T30	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T87	0	1	0	0
T148	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	605	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T9	30914	0	0	0
T15	26557	0	0	0
T25	0	2	0	0
T26	21493	3	0	0
T29	70558	0	0	0
T30	58585	1	0	0
T31	52505	5	0	0
T35	0	1	0	0
T44	0	1	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T50	0	2	0	0
T76	0	3	0	0
T87	0	1	0	0
T88	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	72265	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T9	30914	0	0	0
T15	26557	0	0	0
T25	0	286	0	0
T26	21493	166	0	0
T29	70558	0	0	0
T30	58585	961	0	0
T31	52505	990	0	0
T35	0	35	0	0
T44	0	277	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T50	0	265	0	0
T76	0	619	0	0
T87	0	2	0	0
T88	0	190	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	529	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T9	30914	0	0	0
T15	26557	0	0	0
T26	21493	3	0	0
T29	70558	0	0	0
T30	58585	0	0	0
T31	52505	5	0	0
T35	0	1	0	0
T44	0	1	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T50	0	2	0	0
T76	0	3	0	0
T78	0	1	0	0
T80	0	1	0	0
T88	0	1	0	0
T94	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	53	0	0
T7	22501	0	0	0
T9	30914	0	0	0
T25	0	1	0	0
T30	58585	1	0	0
T31	52505	0	0	0
T36	0	1	0	0
T43	28601	0	0	0
T49	103584	0	0	0
T50	20609	0	0	0
T51	4565	0	0	0
T52	54781	0	0	0
T67	0	1	0	0
T83	0	1	0	0
T92	94296	0	0	0
T97	0	1	0	0
T98	0	1	0	0
T117	0	3	0	0
T157	0	1	0	0
T159	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	1457	0	0
T6	33979	310	0	0
T8	38417	372	0	0
T9	30914	328	0	0
T29	70558	0	0	0
T30	58585	0	0	0
T31	52505	0	0	0
T46	0	136	0	0
T47	0	311	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T50	20609	0	0	0
T51	4565	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	1187	0	0
T6	33979	250	0	0
T8	38417	312	0	0
T9	30914	268	0	0
T29	70558	0	0	0
T30	58585	0	0	0
T31	52505	0	0	0
T46	0	106	0	0
T47	0	251	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T50	20609	0	0	0
T51	4565	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544257248	544184274	0	0
T1	1339	1284	0	0
T2	3334	3267	0	0
T3	3817	3719	0	0
T4	14282	14162	0	0
T5	21546	21366	0	0
T10	23711	23611	0	0
T11	16619	16568	0	0
T12	28713	28647	0	0
T13	56933	56834	0	0
T17	35673	35619	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	544311867	0	0
T1	1339	1284	0	0
T2	3334	3267	0	0
T3	3817	3719	0	0
T4	14282	14162	0	0
T5	21546	21366	0	0
T10	23711	23611	0	0
T11	16619	16568	0	0
T12	28713	28647	0	0
T13	56933	56834	0	0
T17	35673	35619	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T4 T5 T13 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T4 T5 T13 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T4 T5 T13 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T15 T50 T53 
159        1/1                    state_d = TimeoutSt;
           Tests:       T15 T50 T53 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T15 T50 T53 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T15 T50 T53 
172        1/1                    state_d    = Phase0St;
           Tests:       T15 T90 T41 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T15 T90 T41 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T15 T90 T41 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T15 T90 T41 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T15 T50 T53 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T15 T50 T53 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T15 T50 T53 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T15 T50 T53 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T13 T14 T15 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T13 T14 T15 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T13 T14 T15 
190        1/1                  esc_state_o = Phase0;
           Tests:       T13 T14 T15 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T13 T14 T15 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T13 T14 T15 
194        1/1                    state_d = IdleSt;
           Tests:       T160 T161 T162 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T160 T161 T162 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T160 T161 T162 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T13 T14 T15 
198        1/1                    state_d = Phase1St;
           Tests:       T13 T14 T15 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T14 T15 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T13 T14 T15 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T13 T14 T15 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T13 T14 T15 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T13 T14 T15 
207        1/1                  esc_state_o = Phase1;
           Tests:       T13 T14 T15 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T13 T14 T15 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T13 T14 T15 
211        1/1                    state_d = IdleSt;
           Tests:       T36 T163 T161 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T36 T163 T161 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T36 T163 T161 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T13 T14 T15 
215        1/1                    state_d = Phase2St;
           Tests:       T13 T14 T15 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T14 T15 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T13 T14 T15 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T13 T14 T15 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T13 T14 T15 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T13 T14 T15 
224        1/1                  esc_state_o = Phase2;
           Tests:       T13 T14 T15 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T13 T14 T15 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T13 T14 T15 
229        1/1                    state_d = IdleSt;
           Tests:       T59 T164 T155 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T59 T164 T155 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T59 T164 T155 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T13 T14 T15 
233        1/1                    state_d = Phase3St;
           Tests:       T13 T14 T15 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T14 T15 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T13 T14 T15 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T13 T14 T15 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T13 T14 T15 
241        1/1                  esc_state_o = Phase3;
           Tests:       T13 T14 T15 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T13 T14 T15 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T13 T14 T15 
245        1/1                    state_d = IdleSt;
           Tests:       T86 T66 T165 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T86 T66 T165 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T86 T66 T165 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T13 T14 T15 
249        1/1                    state_d = TerminalSt;
           Tests:       T13 T14 T15 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T14 T15 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T13 T14 T15 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T13 T14 T15 
259        1/1                  esc_state_o = Terminal;
           Tests:       T13 T14 T15 
260        1/1                  if (clr_i) begin
           Tests:       T13 T14 T15 
261        1/1                    state_d = IdleSt;
           Tests:       T40 T77 T78 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T6 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T6 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T6 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T6 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	44	97.78
Logical	45	44	97.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Covered	T4,T5,T13
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T13

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T39
1	1	1	Covered	T4,T5,T13

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T12,T13
1	0	1	Covered	T16,T14,T52
1	1	0	Covered	T26,T29,T30
1	1	1	Covered	T15,T50,T53

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T15,T50,T53
0	1	Covered	T15,T90,T91
1	0	Covered	T41,T36,T59

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T15,T50,T53
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T41,T36,T59

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T50,T53
1	0	Covered	T42
1	1	Covered	T15,T90,T91

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T13,T29,T52
1	Covered	T14,T15,T55

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T29,T52,T35

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T14,T15,T29
1	Covered	T13,T54,T40

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T53,T56,T82

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T6,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T14,T15,T52

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T14,T29,T52

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T13,T14,T52

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T14,T29,T52

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T6,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T13,T14,T15
Phase1St	198	Covered	T13,T14,T15
Phase2St	215	Covered	T13,T14,T15
Phase3St	233	Covered	T13,T14,T15
TerminalSt	249	Covered	T13,T14,T15
TimeoutSt	159	Covered	T15,T50,T53

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T6,T8,T9
IdleSt->Phase0St	152	Covered	T13,T14,T29
IdleSt->TimeoutSt	159	Covered	T15,T50,T53
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T44,T36,T166
Phase0St->Phase1St	198	Covered	T13,T14,T15
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T36,T163,T161
Phase1St->Phase2St	215	Covered	T13,T14,T15
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T59,T102,T164
Phase2St->Phase3St	233	Covered	T13,T14,T15
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T86,T64,T66
Phase3St->TerminalSt	249	Covered	T13,T14,T15
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T40,T77,T32
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T15,T50,T53
TimeoutSt->Phase0St	172	Covered	T15,T90,T41

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T13
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T50,T53
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T15,T90,T41
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T15,T50,T53
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T15,T50,T53
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T160,T161,T162
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T13,T14,T15
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T13,T15,T29
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T36,T163,T161
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T13,T14,T15
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T13,T15,T29
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T59,T164,T155
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T13,T14,T15
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T13,T15,T29
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T86,T66,T165
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T13,T14,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T13,T15,T29
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T40,T77,T78
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T13,T14,T15
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	544499054	230	0	0
CheckAccumTrig0_A	544499054	442	0	0
CheckAccumTrig1_A	544499054	28	0	0
CheckClr_A	544499054	178	0	0
CheckEn_A	544261746	218962791	0	0
CheckPhase0_A	544499054	512	0	0
CheckPhase1_A	544499054	500	0	0
CheckPhase2_A	544499054	494	0	0
CheckPhase3_A	544499054	488	0	0
CheckTimeout0_A	544499054	501	0	0
CheckTimeoutSt1_A	544499054	77070	0	0
CheckTimeoutSt2_A	544499054	415	0	0
CheckTimeoutStTrig_A	544499054	55	0	0
ErrorStAllEscAsserted_A	544499054	1452	0	0
ErrorStIsTerminal_A	544499054	1182	0	0
EscStateOut_A	544257248	544184274	0	0
u_state_regs_A	544499054	544311867	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	230	0	0
T6	33979	49	0	0
T8	38417	57	0	0
T9	30914	39	0	0
T29	70558	0	0	0
T30	58585	0	0	0
T31	52505	0	0	0
T46	0	19	0	0
T47	0	66	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T50	20609	0	0	0
T51	4565	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	442	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T13	56933	1	0	0
T14	3411	1	0	0
T15	26557	0	0	0
T16	36831	0	0	0
T26	21493	0	0	0
T29	70558	1	0	0
T30	58585	0	0	0
T35	0	1	0	0
T40	0	1	0	0
T48	52907	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	28	0	0
T32	76223	0	0	0
T36	0	1	0	0
T41	62389	1	0	0
T45	325915	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T65	0	2	0	0
T67	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T77	13512	0	0	0
T78	148330	0	0	0
T79	23187	0	0	0
T80	91594	0	0	0
T81	1145	0	0	0
T82	185164	0	0	0
T83	545454	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	178	0	0
T35	34333	0	0	0
T36	0	2	0	0
T37	39609	0	0	0
T40	94005	1	0	0
T46	108252	0	0	0
T47	31117	0	0	0
T56	230699	0	0	0
T58	0	4	0	0
T59	0	1	0	0
T60	0	1	0	0
T73	18878	0	0	0
T74	191036	0	0	0
T75	67925	0	0	0
T76	41279	0	0	0
T77	0	1	0	0
T78	0	1	0	0
T83	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544261746	218962791	0	0
T1	1339	586	0	0
T2	3334	2741	0	0
T3	3817	2167	0	0
T4	14282	667	0	0
T5	21546	2133	0	0
T10	23711	18400	0	0
T11	16619	16567	0	0
T12	28713	22907	0	0
T13	56933	8348	0	0
T17	35673	35618	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	512	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T13	56933	1	0	0
T14	3411	1	0	0
T15	26557	1	0	0
T16	36831	0	0	0
T26	21493	0	0	0
T29	70558	1	0	0
T30	58585	0	0	0
T35	0	1	0	0
T40	0	1	0	0
T48	52907	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	500	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T13	56933	1	0	0
T14	3411	1	0	0
T15	26557	1	0	0
T16	36831	0	0	0
T26	21493	0	0	0
T29	70558	1	0	0
T30	58585	0	0	0
T35	0	1	0	0
T40	0	1	0	0
T48	52907	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	494	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T13	56933	1	0	0
T14	3411	1	0	0
T15	26557	1	0	0
T16	36831	0	0	0
T26	21493	0	0	0
T29	70558	1	0	0
T30	58585	0	0	0
T35	0	1	0	0
T40	0	1	0	0
T48	52907	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	488	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T13	56933	1	0	0
T14	3411	1	0	0
T15	26557	1	0	0
T16	36831	0	0	0
T26	21493	0	0	0
T29	70558	1	0	0
T30	58585	0	0	0
T35	0	1	0	0
T40	0	1	0	0
T48	52907	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	501	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T9	30914	0	0	0
T15	26557	2	0	0
T25	0	1	0	0
T29	70558	0	0	0
T30	58585	0	0	0
T31	52505	0	0	0
T36	0	10	0	0
T41	0	1	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T50	20609	1	0	0
T53	0	1	0	0
T76	0	3	0	0
T80	0	2	0	0
T90	0	2	0	0
T91	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	77070	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T9	30914	0	0	0
T15	26557	973	0	0
T25	0	107	0	0
T29	70558	0	0	0
T30	58585	0	0	0
T31	52505	0	0	0
T36	0	3083	0	0
T41	0	8	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T50	20609	134	0	0
T53	0	807	0	0
T76	0	537	0	0
T80	0	275	0	0
T90	0	295	0	0
T91	0	465	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	415	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T9	30914	0	0	0
T15	26557	1	0	0
T25	0	1	0	0
T29	70558	0	0	0
T30	58585	0	0	0
T31	52505	0	0	0
T36	0	6	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T50	20609	1	0	0
T53	0	1	0	0
T58	0	8	0	0
T76	0	3	0	0
T80	0	2	0	0
T90	0	1	0	0
T91	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	55	0	0
T6	33979	0	0	0
T8	38417	0	0	0
T9	30914	0	0	0
T15	26557	1	0	0
T29	70558	0	0	0
T30	58585	0	0	0
T31	52505	0	0	0
T36	0	3	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T50	20609	0	0	0
T62	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0
T99	0	2	0	0
T102	0	2	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	1452	0	0
T6	33979	284	0	0
T8	38417	338	0	0
T9	30914	315	0	0
T29	70558	0	0	0
T30	58585	0	0	0
T31	52505	0	0	0
T46	0	192	0	0
T47	0	323	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T50	20609	0	0	0
T51	4565	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	1182	0	0
T6	33979	224	0	0
T8	38417	278	0	0
T9	30914	255	0	0
T29	70558	0	0	0
T30	58585	0	0	0
T31	52505	0	0	0
T46	0	162	0	0
T47	0	263	0	0
T48	52907	0	0	0
T49	103584	0	0	0
T50	20609	0	0	0
T51	4565	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544257248	544184274	0	0
T1	1339	1284	0	0
T2	3334	3267	0	0
T3	3817	3719	0	0
T4	14282	14162	0	0
T5	21546	21366	0	0
T10	23711	23611	0	0
T11	16619	16568	0	0
T12	28713	28647	0	0
T13	56933	56834	0	0
T17	35673	35619	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544499054	544311867	0	0
T1	1339	1284	0	0
T2	3334	3267	0	0
T3	3817	3719	0	0
T4	14282	14162	0	0
T5	21546	21366	0	0
T10	23711	23611	0	0
T11	16619	16568	0	0
T12	28713	28647	0	0
T13	56933	56834	0	0
T17	35673	35619	0	0