Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1279010
Category 01279010

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1279010
Severity 01279010

Summary for Assertions
NUMBERPERCENT
Total Number1279100.00
Uncovered20.16
Success127799.84
Failure00.00
Incomplete493.83
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered660.00
All Matches440.00
First Matches440.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.u_reg_wrap.u_reg.u_ping_timer_en_shadowed.CheckSwAccessIsLegal_A 0082482400
tb.dut.u_reg_wrap.u_reg.u_ping_timer_en_shadowed.MubiIsNotYetSupported_A 0060100090760031668300
tb.dut.u_reg_wrap.u_reg.u_reg_if.AllowedLatency_A 0082482400
tb.dut.u_reg_wrap.u_reg.u_reg_if.MatchedWidthAssert 0082482400
tb.dut.u_reg_wrap.u_reg.u_reg_if.u_err.dataWidthOnly32_A 0082482400
tb.dut.u_reg_wrap.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 0082482400
tb.dut.u_reg_wrap.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 0082482400
tb.dut.u_reg_wrap.u_reg.u_rsp_intg_gen.DataWidthCheck_A 0082482400
tb.dut.u_reg_wrap.u_reg.u_rsp_intg_gen.PayLoadWidthCheck 0082482400
tb.dut.u_reg_wrap.u_reg.wePulse 006010009076431099900

Assertions Incomplete:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en.gen_flops.gen_no_stable_chks.OutputDelay_A 0057469552557453315401857
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A 0057469552500619

Detail Report for Cover Sequences

Cover Sequences Uncovered:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 00601001447000
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 00601001447000
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 00601001447000
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00601001447000
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 00601001447000
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00601001447000

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 006010014472005942005940
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0060100144763047630470
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 00601001447187980518798050
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 006010014474231645242316452777

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 006010014472005942005940
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0060100144763047630470
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 00601001447187980518798050
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 006010014474231645242316452777