Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	574695525	0	0	619
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	574695525	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	574695525	574539856	0	0
tb.dut.CheckAccuCntDw	0	0	619	619	0	0
tb.dut.CheckEscCntDw	0	0	619	619	0	0
tb.dut.CheckNAlerts	0	0	619	619	0	0
tb.dut.CheckNClasses	0	0	619	619	0	0
tb.dut.CheckNEscSev	0	0	619	619	0	0
tb.dut.CrashdumpKnownO_A	0	0	574695525	574539856	0	0
tb.dut.EdnKnownO_A	0	0	574695525	574539856	0	0
tb.dut.EscPKnownO_A	0	0	574695525	574539856	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	574695525	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	574695525	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	574695525	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	574695525	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	574695525	70	0	0
tb.dut.IrqAKnownO_A	0	0	574695525	574539856	0	0
tb.dut.IrqBKnownO_A	0	0	574695525	574539856	0	0
tb.dut.IrqCKnownO_A	0	0	574695525	574539856	0	0
tb.dut.IrqDKnownO_A	0	0	574695525	574539856	0	0
tb.dut.TlAReadyKnownO_A	0	0	574695525	574539856	0	0
tb.dut.TlDValidKnownO_A	0	0	574695525	574539856	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	601000907	187522	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	601000907	18598	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	601000907	17370	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	601000907	17360	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	601000907	18362	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	601000907	17139	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	601000907	17253	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	601000907	17214	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	601000907	17282	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	601000907	17282	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	601000907	18500	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	601000907	17344	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	601000907	18575	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	601000907	17259	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	601000907	17127	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	601000907	17376	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	601000907	17124	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	601000907	18061	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	601000907	18209	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	601000907	17408	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	601000907	17432	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	601000907	17812	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	601000907	17450	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	601000907	17504	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	601000907	18632	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	601000907	17393	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	601000907	17584	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	601000907	17585	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	601000907	18543	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	601000907	17318	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	601000907	18574	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	601000907	17860	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	601000907	18549	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	601000907	18677	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	601000907	17400	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	601000907	17362	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	601000907	17049	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	601000907	17369	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	601000907	17634	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	601000907	17446	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	601000907	17251	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	601000907	18465	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	601000907	17078	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	601000907	16966	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	601000907	17454	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	601000907	17310	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	601000907	17238	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	601000907	18363	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	601000907	17320	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	601000907	17516	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	601000907	17236	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	601000907	18642	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	601000907	17128	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	601000907	17330	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	601000907	17624	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	601000907	18718	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	601000907	17508	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	601000907	17191	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	601000907	17371	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	601000907	18566	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	601000907	17670	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	601000907	17195	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	601000907	17149	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	601000907	18200	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	601000907	18620	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	601000907	17266	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	601000907	17292	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	601000907	19085	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	601000907	17493	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	601000907	18420	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	601000907	37275	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	601000907	17417	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	601000907	17442	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	601000907	16999	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	601000907	16942	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	601000907	17718	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	601000907	17467	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	601000907	17362	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	601000907	17409	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	574695525	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	574695525	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	574695525	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	574695525	5817	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	574695525	193080	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	574695525	280947005	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	574695525	199	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	574695525	800	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	574695525	44	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	574695525	426	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	574561090	210061375	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	574695525	862	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	574695525	841	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	574695525	815	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	574695525	802	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	574695525	1345	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	574695525	129921	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	574695525	1250	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	574695525	50	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	574695525	1091	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	574695525	881	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	574560034	574493581	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	574695525	574539856	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	574695525	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	574695525	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	574695525	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	574695525	3887	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	574695525	189124	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	574695525	289851908	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	574695525	189	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	574695525	422	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	574695525	18	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	574695525	176	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	574561090	205568966	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	574695525	469	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	574695525	463	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	574695525	453	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	574695525	437	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	574695525	1167	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	574695525	104979	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	574695525	1102	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	574695525	42	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	574695525	1134	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	574695525	924	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	574560034	574493581	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	574695525	574539856	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	574695525	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	574695525	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	574695525	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	574695525	3916	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	574695525	173536	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	574695525	298228729	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	574695525	183	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	574695525	429	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	574695525	21	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	574695525	192	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	574561090	220780718	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	574695525	483	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	574695525	472	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	574695525	461	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	574695525	457	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	574695525	1197	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	574695525	101088	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	574695525	1123	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	574695525	48	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	574695525	1102	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	574695525	892	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	574560034	574493581	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	574695525	574539856	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	574695525	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	574695525	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	574695525	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	574695525	3263	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	574695525	177515	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	574695525	291443643	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	574695525	221	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	574695525	477	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	574695525	16	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	574695525	249	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	574561090	220362855	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	574695525	528	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	574695525	520	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	574695525	507	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	574695525	494	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	574695525	950	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	574695525	90191	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	574695525	876	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	574695525	56	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	574695525	1175	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	574695525	965	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	574560034	574493581	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	574695525	574539856	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	601000907	82810290	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	601000907	600316683	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	601000907	600316683	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	601000907	156666837	0	0
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