| | | | | | | |
prim_packer_fifo |
68.93 |
100.00 |
90.00 |
|
|
85.71 |
0.00 |
alert_handler_lpg_ctrl |
73.39 |
96.77 |
|
|
|
50.00 |
|
prim_count |
89.52 |
|
|
89.52 |
|
|
|
prim_count ( parameter Width=16,ResetValue=0,EnableAlertTriggerSVA=0,PossibleActions=10,NumCnt=2 + Width=16,ResetValue=0,EnableAlertTriggerSVA=0,PossibleActions=15,NumCnt=2 ) |
100.00 |
|
|
100.00 |
|
|
|
prim_count ( parameter Width=2,ResetValue=0,EnableAlertTriggerSVA=0,PossibleActions=5,NumCnt=2 ) |
100.00 |
|
|
100.00 |
|
|
|
prim_count ( parameter Width=32,ResetValue=0,EnableAlertTriggerSVA=0,PossibleActions=7,NumCnt=2 ) |
68.57 |
|
|
68.57 |
|
|
|
alert_handler_ping_timer |
91.46 |
100.00 |
97.30 |
|
60.00 |
100.00 |
100.00 |
tlul_rsp_intg_gen |
91.67 |
83.33 |
|
|
|
|
100.00 |
tlul_rsp_intg_gen |
100.00 |
|
|
|
|
|
100.00 |
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 ) |
66.67 |
66.67 |
|
|
|
|
|
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 ) |
100.00 |
100.00 |
|
|
|
|
|
alert_handler_esc_timer |
92.30 |
100.00 |
91.49 |
|
70.00 |
100.00 |
100.00 |
prim_sync_reqack |
95.83 |
100.00 |
83.33 |
|
|
100.00 |
100.00 |
prim_edn_req |
96.15 |
100.00 |
84.62 |
|
|
100.00 |
100.00 |
tlul_adapter_reg |
98.98 |
100.00 |
95.92 |
|
|
100.00 |
100.00 |
prim_subreg_shadow |
99.04 |
100.00 |
96.15 |
|
|
100.00 |
100.00 |
alert_handler_reg_top |
99.16 |
100.00 |
96.62 |
|
|
100.00 |
100.00 |
tlul_assert |
99.30 |
100.00 |
|
|
|
100.00 |
97.90 |
alert_handler_reg_wrap |
99.93 |
100.00 |
99.78 |
|
|
100.00 |
|
tlul_data_integ_dec |
100.00 |
100.00 |
|
|
|
|
|
prim_sparse_fsm_flop |
100.00 |
100.00 |
|
|
|
|
100.00 |
prim_esc_sender |
100.00 |
|
|
100.00 |
|
|
|
tlul_cmd_intg_chk |
100.00 |
100.00 |
|
|
|
|
100.00 |
alert_handler_accu |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
prim_onehot_check |
100.00 |
|
|
100.00 |
|
|
|
prim_subreg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_subreg |
100.00 |
100.00 |
|
|
|
100.00 |
|
prim_subreg ( parameter DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 + DW=1,SwAccess=5,RESVAL=1,Mubi=0 + DW=1,SwAccess=4,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=16,SwAccess=0,RESVAL,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=2,SwAccess=0,RESVAL,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=32,SwAccess=0,RESVAL,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_secded_inv_39_32_dec |
100.00 |
|
|
100.00 |
|
|
|
prim_double_lfsr |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
prim_generic_buf |
100.00 |
100.00 |
|
|
|
|
|
prim_intr_hw |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
prim_subreg_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_subreg_arb |
100.00 |
|
|
|
|
100.00 |
|
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=2,SwAccess=0,Mubi=0 + DW=32,SwAccess=0,Mubi=0 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=4,Mubi=0 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=16,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=2,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_ext |
100.00 |
100.00 |
|
|
|
|
|
prim_alert_receiver |
100.00 |
|
|
100.00 |
|
|
|
alert_handler_csr_assert_fpv |
100.00 |
|
|
|
|
|
100.00 |
alert_handler |
100.00 |
100.00 |
|
100.00 |
|
|
100.00 |
prim_secded_inv_39_32_enc |
100.00 |
100.00 |
|
|
|
|
|
tlul_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
prim_lfsr |
100.00 |
|
|
100.00 |
|
|
|
prim_secded_inv_64_57_enc |
100.00 |
100.00 |
|
|
|
|
|
prim_secded_inv_64_57_dec |
100.00 |
|
|
100.00 |
|
|
|
alert_handler_class |
100.00 |
100.00 |
|
|
|
|
|
prim_sync_reqack_data |
100.00 |
100.00 |
|
|
|
|
100.00 |
prim_generic_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
prim_mubi4_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
prim_mubi4_sync |
100.00 |
|
|
|
|
|
100.00 |
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=6 ) |
100.00 |
100.00 |
|
|
|
|
|
tlul_data_integ_enc |
|
|
|
|
|
|
|
prim_reg_we_check |
|
|
|
|
|
|
|
prim_buf |
|
|
|
|
|
|
|
prim_generic_flop_2sync |
|
|
|
|
|
|
|
prim_flop |
|
|
|
|
|
|
|
prim_flop_2sync |
|
|
|
|
|
|
|
tb |
|
|
|
|
|
|
|