Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	44016	1			T49	1		T16	8		T91	188
class_i[0x1]	74686	1			T12	4		T49	3		T15	4
class_i[0x2]	42465	1			T22	5		T49	17		T15	1
class_i[0x3]	63315	1			T22	1913		T94	6		T49	21

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	55046	1			T12	1		T22	8		T49	17
alert[0x1]	55543	1			T12	3		T22	816		T49	2
alert[0x2]	56021	1			T22	1089		T94	6		T49	12
alert[0x3]	57872	1			T22	5		T49	11		T15	3

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

224194

1

T12

4

T22

1918

T94

6

esc_ping_fail

288

1

T15

5

T16

6

T17

11

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	54967	1			T12	1		T22	8		T49	17
esc_integrity_fail	alert[0x1]	55470	1			T12	3		T22	816		T49	2
esc_integrity_fail	alert[0x2]	55948	1			T22	1089		T94	6		T49	12
esc_integrity_fail	alert[0x3]	57809	1			T22	5		T49	11		T15	2
esc_ping_fail	alert[0x0]	79	1			T15	2		T16	1		T17	2
esc_ping_fail	alert[0x1]	73	1			T15	1		T16	3		T17	3
esc_ping_fail	alert[0x2]	73	1			T15	1		T16	2		T17	3
esc_ping_fail	alert[0x3]	63	1			T15	1		T17	3		T84	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	43941	1			T49	1		T16	2		T91	188
esc_integrity_fail	class_i[0x1]	74605	1			T12	4		T49	3		T15	2
esc_integrity_fail	class_i[0x2]	42400	1			T22	5		T49	17		T28	6
esc_integrity_fail	class_i[0x3]	63248	1			T22	1913		T94	6		T49	21
esc_ping_fail	class_i[0x0]	75	1			T16	6		T335	12		T333	6
esc_ping_fail	class_i[0x1]	81	1			T15	2		T17	11		T84	3
esc_ping_fail	class_i[0x2]	65	1			T15	1		T130	9		T155	7
esc_ping_fail	class_i[0x3]	67	1			T15	2		T84	1		T122	2