Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	3	41	93.18

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	3	41	93.18	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	144	1			T37	1		T49	1		T53	1
index[0x1]	164	1			T9	1		T22	1		T49	1
index[0x2]	132	1			T3	2		T9	2		T22	1
index[0x3]	182	1			T12	1		T22	1		T25	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	172	1			T3	2		T15	1		T53	1
lens_less_than_1000[1]	113	1			T12	1		T22	1		T126	1
lens_less_than_1000[2]	72	1			T25	1		T126	1		T93	1
lens_less_than_1000[3]	73	1			T126	1		T85	1		T156	1
lens_less_than_1000[4]	61	1			T22	1		T125	1		T26	1
lens_less_than_1000[5]	28	1			T53	1		T143	1		T297	2
lens_less_than_1000[6]	34	1			T37	1		T49	1		T298	1
lens_less_than_1000[7]	21	1			T22	1		T125	1		T97	1
lens_less_than_1000[8]	10	1			T49	1		T299	1		T300	1
lens_less_than_1000[9]	2	1			T68	1		T301	1		-	-
len_2	36	1			T9	3		T257	1		T138	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	3	41	93.18	3

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0] , index[0x1] , index[0x2]]	[lens_less_than_1000[9]]	--	--	3

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	41	1			T91	1		T57	3		T81	1
index[0x0]	lens_less_than_1000[1]	34	1			T126	1		T32	1		T258	1
index[0x0]	lens_less_than_1000[2]	11	1			T126	1		T93	1		T104	1
index[0x0]	lens_less_than_1000[3]	12	1			T74	1		T139	1		T69	1
index[0x0]	lens_less_than_1000[4]	12	1			T125	1		T102	2		T68	1
index[0x0]	lens_less_than_1000[5]	7	1			T53	1		T302	1		T303	1
index[0x0]	lens_less_than_1000[6]	10	1			T37	1		T304	1		T273	1
index[0x0]	lens_less_than_1000[7]	2	1			T305	1		T157	1		-	-
index[0x0]	lens_less_than_1000[8]	5	1			T49	1		T300	1		T306	1
index[0x0]	len_2	10	1			T102	1		T307	1		T289	1
index[0x1]	lens_less_than_1000[0]	43	1			T53	1		T90	1		T56	5
index[0x1]	lens_less_than_1000[1]	37	1			T22	1		T260	1		T60	1
index[0x1]	lens_less_than_1000[2]	21	1			T308	1		T141	1		T66	6
index[0x1]	lens_less_than_1000[3]	18	1			T126	1		T136	1		T110	3
index[0x1]	lens_less_than_1000[4]	13	1			T26	1		T309	1		T112	1
index[0x1]	lens_less_than_1000[5]	8	1			T297	2		T310	1		T311	1
index[0x1]	lens_less_than_1000[6]	5	1			T49	1		T306	1		T304	1
index[0x1]	lens_less_than_1000[7]	4	1			T312	1		T313	1		T157	1
index[0x1]	lens_less_than_1000[8]	2	1			T141	1		T281	1		-	-
index[0x1]	len_2	13	1			T9	1		T257	1		T307	9
index[0x2]	lens_less_than_1000[0]	37	1			T3	2		T15	1		T55	1
index[0x2]	lens_less_than_1000[1]	19	1			T28	1		T74	1		T258	1
index[0x2]	lens_less_than_1000[2]	15	1			T155	1		T66	1		T102	1
index[0x2]	lens_less_than_1000[3]	22	1			T33	1		T66	1		T314	1
index[0x2]	lens_less_than_1000[4]	13	1			T22	1		T148	1		T68	1
index[0x2]	lens_less_than_1000[5]	7	1			T315	1		T104	1		T316	1
index[0x2]	lens_less_than_1000[6]	6	1			T298	1		T317	2		T121	1
index[0x2]	lens_less_than_1000[7]	8	1			T97	1		T318	1		T319	6
index[0x2]	lens_less_than_1000[8]	1	1			T301	1		-	-		-	-
index[0x2]	len_2	4	1			T9	2		T282	1		T320	1
index[0x3]	lens_less_than_1000[0]	51	1			T159	1		T28	1		T86	3
index[0x3]	lens_less_than_1000[1]	23	1			T12	1		T28	1		T122	1
index[0x3]	lens_less_than_1000[2]	25	1			T25	1		T261	1		T321	1
index[0x3]	lens_less_than_1000[3]	21	1			T85	1		T156	1		T134	1
index[0x3]	lens_less_than_1000[4]	23	1			T66	1		T117	1		T322	1
index[0x3]	lens_less_than_1000[5]	6	1			T143	1		T121	2		T282	1
index[0x3]	lens_less_than_1000[6]	13	1			T323	1		T123	1		T131	1
index[0x3]	lens_less_than_1000[7]	7	1			T22	1		T125	1		T324	1
index[0x3]	lens_less_than_1000[8]	2	1			T299	1		T70	1		-	-
index[0x3]	lens_less_than_1000[9]	2	1			T68	1		T301	1		-	-
index[0x3]	len_2	9	1			T138	1		T307	8		-	-