Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.74	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	5	35	87.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	5	35	87.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	50	1			T25	1		T55	1		T93	1
class_index[0x1]	42	1			T22	2		T35	2		T90	1
class_index[0x2]	48	1			T91	1		T93	1		T97	1
class_index[0x3]	56	1			T90	1		T97	1		T56	2

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	83	1			T25	1		T35	2		T93	3
intr_timeout_cnt[1]	35	1			T55	1		T97	1		T28	1
intr_timeout_cnt[2]	21	1			T22	1		T104	2		T274	1
intr_timeout_cnt[3]	19	1			T22	1		T91	1		T103	2
intr_timeout_cnt[4]	6	1			T67	1		T158	1		T275	1
intr_timeout_cnt[5]	2	1			T103	1		T276	1		-	-
intr_timeout_cnt[6]	7	1			T26	1		T110	3		T71	1
intr_timeout_cnt[7]	8	1			T90	2		T136	1		T277	2
intr_timeout_cnt[8]	7	1			T101	1		T123	1		T278	1
intr_timeout_cnt[9]	8	1			T26	1		T110	1		T279	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	5	35	87.50	5

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[5] , intr_timeout_cnt[6]]	--	--	2
[class_index[0x2]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[5] , intr_timeout_cnt[6]]	--	--	2

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	27	1			T25	1		T93	1		T99	1
class_index[0x0]	intr_timeout_cnt[1]	6	1			T55	1		T28	1		T32	1
class_index[0x0]	intr_timeout_cnt[2]	2	1			T274	1		T280	1		-	-
class_index[0x0]	intr_timeout_cnt[3]	7	1			T279	1		T281	1		T282	4
class_index[0x0]	intr_timeout_cnt[4]	1	1			T275	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	2	1			T136	1		T283	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	3	1			T101	1		T110	1		T284	1
class_index[0x0]	intr_timeout_cnt[9]	2	1			T26	1		T285	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	20	1			T35	2		T93	1		T102	1
class_index[0x1]	intr_timeout_cnt[1]	5	1			T32	1		T118	1		T71	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T22	1		T104	1		T284	2
class_index[0x1]	intr_timeout_cnt[3]	2	1			T22	1		T285	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	2	1			T67	1		T286	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	1	1			T103	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	2	1			T110	1		T71	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T90	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T278	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	2	1			T110	1		T273	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	18	1			T93	1		T32	1		T60	1
class_index[0x2]	intr_timeout_cnt[1]	12	1			T97	1		T99	1		T287	1
class_index[0x2]	intr_timeout_cnt[2]	1	1			T288	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[3]	5	1			T91	1		T289	1		T282	2
class_index[0x2]	intr_timeout_cnt[4]	2	1			T290	1		T291	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	1	1			T276	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	5	1			T26	1		T110	2		T273	1
class_index[0x2]	intr_timeout_cnt[8]	2	1			T123	1		T273	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	2	1			T279	1		T284	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	18	1			T97	1		T56	2		T142	1
class_index[0x3]	intr_timeout_cnt[1]	12	1			T292	1		T273	1		T293	2
class_index[0x3]	intr_timeout_cnt[2]	12	1			T104	1		T137	1		T71	1
class_index[0x3]	intr_timeout_cnt[3]	5	1			T103	2		T294	1		T281	1
class_index[0x3]	intr_timeout_cnt[4]	1	1			T158	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	5	1			T90	1		T277	2		T295	1
class_index[0x3]	intr_timeout_cnt[8]	1	1			T290	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	2	1			T285	1		T296	1		-	-