Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	292081	1			T3	5		T9	27		T10	19
all_values[1]	292081	1			T3	5		T9	27		T10	19
all_values[2]	292081	1			T3	5		T9	27		T10	19
all_values[3]	292081	1			T3	5		T9	27		T10	19

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

580487

1

T3

12

T9

65

T10

41

auto[1]

587837

1

T3

8

T9

43

T10

35

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

693932

1

T3

12

T9

95

T10

42

auto[1]

474392

1

T3

8

T9

13

T10

34

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	85129	1			T3	1		T9	9		T10	7
all_values[0]	auto[0]	auto[1]	59895	1			T3	1		T9	8		T10	6
all_values[0]	auto[1]	auto[0]	86834	1			T3	2		T9	5		T10	3
all_values[0]	auto[1]	auto[1]	60223	1			T3	1		T9	5		T10	3
all_values[1]	auto[0]	auto[0]	86897	1			T3	2		T9	19		T10	4
all_values[1]	auto[0]	auto[1]	58512	1			T3	1		T10	4		T13	7
all_values[1]	auto[1]	auto[0]	88170	1			T3	1		T9	8		T10	6
all_values[1]	auto[1]	auto[1]	58502	1			T3	1		T10	5		T13	4
all_values[2]	auto[0]	auto[0]	86761	1			T3	1		T9	15		T10	6
all_values[2]	auto[0]	auto[1]	57931	1			T3	1		T10	6		T13	3
all_values[2]	auto[1]	auto[0]	88886	1			T3	2		T9	12		T10	5
all_values[2]	auto[1]	auto[1]	58503	1			T3	1		T10	2		T13	8
all_values[3]	auto[0]	auto[0]	84996	1			T3	3		T9	14		T10	4
all_values[3]	auto[0]	auto[1]	60366	1			T3	2		T10	4		T13	6
all_values[3]	auto[1]	auto[0]	86259	1			T9	13		T10	7		T14	17
all_values[3]	auto[1]	auto[1]	60460	1			T10	4		T13	5		T12	2