Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	292081	1			T3	5		T9	27		T10	19
all_pins[1]	292081	1			T3	5		T9	27		T10	19
all_pins[2]	292081	1			T3	5		T9	27		T10	19
all_pins[3]	292081	1			T3	5		T9	27		T10	19

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	930636	1			T3	17		T9	103		T10	62
values[0x1]	237688	1			T3	3		T9	5		T10	14
transitions[0x0=>0x1]	156831	1			T3	3		T9	4		T10	10
transitions[0x1=>0x0]	157070	1			T3	3		T9	5		T10	10

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	231858	1			T3	4		T9	22		T10	16
all_pins[0]	values[0x1]	60223	1			T3	1		T9	5		T10	3
all_pins[0]	transitions[0x0=>0x1]	59716	1			T3	1		T9	4		T10	3
all_pins[0]	transitions[0x1=>0x0]	60192	1			T10	4		T13	5		T12	2
all_pins[1]	values[0x0]	233579	1			T3	4		T9	27		T10	14
all_pins[1]	values[0x1]	58502	1			T3	1		T10	5		T13	4
all_pins[1]	transitions[0x0=>0x1]	31654	1			T3	1		T10	4		T13	2
all_pins[1]	transitions[0x1=>0x0]	33375	1			T3	1		T9	5		T10	2
all_pins[2]	values[0x0]	233578	1			T3	4		T9	27		T10	17
all_pins[2]	values[0x1]	58503	1			T3	1		T10	2		T13	8
all_pins[2]	transitions[0x0=>0x1]	31925	1			T3	1		T13	6		T22	1
all_pins[2]	transitions[0x1=>0x0]	31924	1			T3	1		T10	3		T13	2
all_pins[3]	values[0x0]	231621	1			T3	5		T9	27		T10	15
all_pins[3]	values[0x1]	60460	1			T10	4		T13	5		T12	2
all_pins[3]	transitions[0x0=>0x1]	33536	1			T10	3		T13	1		T22	2
all_pins[3]	transitions[0x1=>0x0]	31579	1			T3	1		T10	1		T13	4