Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	93178	1			T56	483		T299	653		T329	1187
accum_cnt_1000	188214	1			T22	16		T50	22		T146	38
accum_cnt_100	18707	1			T9	3		T50	53		T52	27
accum_cnt_50	64543	1			T9	11		T10	9		T13	16
accum_cnt_10	133014	1			T9	3		T10	28		T13	6
accum_cnt_0	332764	1			T3	8		T9	55		T10	15

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	217117	1			T3	2		T9	18		T10	13
class_index[0x1]	217117	1			T3	2		T9	18		T10	13
class_index[0x2]	217117	1			T3	2		T9	18		T10	13
class_index[0x3]	217117	1			T3	2		T9	18		T10	13

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	23852	1			T299	252		T329	361		T108	64
class_index[0x0]	accum_cnt_1000	48668	1			T125	56		T95	38		T330	5
class_index[0x0]	accum_cnt_100	5525	1			T9	3		T52	2		T55	7
class_index[0x0]	accum_cnt_50	16600	1			T9	11		T22	11		T42	10
class_index[0x0]	accum_cnt_10	31344	1			T9	3		T10	1		T12	1
class_index[0x0]	accum_cnt_0	81085	1			T3	2		T9	1		T10	12
class_index[0x1]	accum_cnt_2000	24491	1			T299	401		T329	419		T331	489
class_index[0x1]	accum_cnt_1000	43768	1			T146	8		T125	35		T93	10
class_index[0x1]	accum_cnt_100	4216	1			T50	17		T52	15		T146	20
class_index[0x1]	accum_cnt_50	15097	1			T87	16		T49	10		T50	16
class_index[0x1]	accum_cnt_10	39005	1			T10	12		T12	1		T22	19
class_index[0x1]	accum_cnt_0	79634	1			T3	2		T9	18		T10	1
class_index[0x2]	accum_cnt_2000	19847	1			T56	213		T329	407		T108	629
class_index[0x2]	accum_cnt_1000	49299	1			T50	4		T146	12		T256	51
class_index[0x2]	accum_cnt_100	4549	1			T50	22		T35	6		T146	21
class_index[0x2]	accum_cnt_50	15474	1			T10	7		T22	2		T25	2
class_index[0x2]	accum_cnt_10	36209	1			T10	5		T12	2		T22	16
class_index[0x2]	accum_cnt_0	83506	1			T3	2		T9	18		T10	1
class_index[0x3]	accum_cnt_2000	24988	1			T56	270		T331	405		T306	615
class_index[0x3]	accum_cnt_1000	46479	1			T22	16		T50	18		T146	18
class_index[0x3]	accum_cnt_100	4417	1			T50	14		T52	10		T35	6
class_index[0x3]	accum_cnt_50	17372	1			T10	2		T13	16		T22	1
class_index[0x3]	accum_cnt_10	26456	1			T10	10		T13	6		T22	1
class_index[0x3]	accum_cnt_0	88539	1			T3	2		T9	18		T10	1