Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	7826	1			T49	1		T84	1		T79	1
alert[0x1]	4663	1			T122	1		T155	1		T332	1
alert[0x2]	3164	1			T333	1		T77	5		T334	1
alert[0x3]	7260	1			T77	1		T108	3159		T140	116
alert[0x4]	2147	1			T84	1		T90	9		T333	1
alert[0x5]	18048	1			T16	2		T77	12		T79	2
alert[0x6]	1255	1			T16	1		T257	2		T335	1
alert[0x7]	6941	1			T130	1		T28	2		T39	1
alert[0x8]	3603	1			T155	1		T79	2		T81	1
alert[0x9]	7583	1			T28	6		T259	443		T60	8
alert[0xa]	2936	1			T16	1		T84	1		T335	1
alert[0xb]	1330	1			T17	1		T90	6		T79	1
alert[0xc]	3826	1			T22	9		T335	1		T259	3
alert[0xd]	3008	1			T56	5		T155	1		T108	8
alert[0xe]	5397	1			T84	1		T93	1		T122	1
alert[0xf]	7172	1			T333	1		T79	1		T259	12
alert[0x10]	2820	1			T15	1		T259	29		T108	124
alert[0x11]	2778	1			T259	73		T336	1		T140	5
alert[0x12]	5916	1			T17	2		T130	2		T28	1
alert[0x13]	2422	1			T12	7		T16	2		T155	1
alert[0x14]	4878	1			T17	1		T259	129		T258	3
alert[0x15]	12423	1			T93	15		T333	1		T155	1
alert[0x16]	8909	1			T15	2		T53	1		T17	1
alert[0x17]	10485	1			T16	1		T56	2		T155	1
alert[0x18]	11462	1			T84	1		T130	1		T28	12
alert[0x19]	4562	1			T17	1		T258	11		T108	515
alert[0x1a]	3562	1			T84	1		T122	1		T333	1
alert[0x1b]	5156	1			T77	7		T259	26		T337	2
alert[0x1c]	1376	1			T22	1		T90	16		T130	1
alert[0x1d]	3673	1			T28	12		T335	1		T259	27
alert[0x1e]	2468	1			T130	1		T259	137		T108	7
alert[0x1f]	6597	1			T84	1		T337	1		T258	9
alert[0x20]	2048	1			T257	1		T259	1		T26	1
alert[0x21]	3013	1			T53	6		T257	4		T130	1
alert[0x22]	6516	1			T81	1		T259	116		T336	1
alert[0x23]	2719	1			T335	1		T155	1		T60	2
alert[0x24]	4382	1			T90	5		T130	1		T259	36
alert[0x25]	2282	1			T90	7		T335	1		T333	1
alert[0x26]	2035	1			T84	1		T28	2		T335	1
alert[0x27]	6080	1			T53	1		T155	1		T259	140
alert[0x28]	1070	1			T91	4		T130	1		T333	1
alert[0x29]	4605	1			T12	1		T130	1		T79	1
alert[0x2a]	9062	1			T259	256		T108	1432		T140	225
alert[0x2b]	6131	1			T15	1		T84	2		T90	1
alert[0x2c]	3382	1			T22	3		T17	2		T333	1
alert[0x2d]	9825	1			T22	8		T39	2		T79	1
alert[0x2e]	5520	1			T22	4		T17	1		T155	1
alert[0x2f]	4921	1			T22	2		T90	12		T130	1
alert[0x30]	3786	1			T79	1		T81	1		T108	2014
alert[0x31]	3302	1			T22	2		T84	1		T90	3
alert[0x32]	7117	1			T90	16		T145	12		T333	1
alert[0x33]	7018	1			T22	11		T84	1		T335	1
alert[0x34]	3598	1			T15	1		T130	1		T155	1
alert[0x35]	6691	1			T16	2		T17	1		T84	1
alert[0x36]	2869	1			T16	1		T84	1		T335	1
alert[0x37]	9132	1			T130	1		T155	1		T259	78
alert[0x38]	2771	1			T17	1		T259	62		T258	1
alert[0x39]	6982	1			T257	2		T333	1		T79	1
alert[0x3a]	11215	1			T16	2		T17	1		T108	51
alert[0x3b]	2139	1			T130	1		T333	1		T56	1
alert[0x3c]	1471	1			T15	1		T130	1		T335	2
alert[0x3d]	5129	1			T12	4		T39	1		T155	1
alert[0x3e]	5238	1			T28	49		T338	1		T337	1
alert[0x3f]	8969	1			T84	1		T28	1		T79	1
alert[0x40]	1318	1			T16	1		T90	1		T28	5

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	118995	1			T12	12		T49	1		T15	2
class_i[0x1]	59489	1			T15	1		T53	1		T17	11
class_i[0x2]	85995	1			T15	2		T16	1		T257	4
class_i[0x3]	73503	1			T22	40		T15	1		T53	7

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

337290

1

T12

12

T22

40

T49

1

alert_ping_fail

692

1

T15

6

T16

13

T17

12

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	7818	1			T49	1		T259	1420		T339	6
alert_integrity_fail	alert[0x1]	4654	1			T297	2		T65	8		T66	67
alert_integrity_fail	alert[0x2]	3150	1			T77	5		T102	8		T339	426
alert_integrity_fail	alert[0x3]	7253	1			T77	1		T108	3159		T140	116
alert_integrity_fail	alert[0x4]	2139	1			T90	9		T26	1		T108	199
alert_integrity_fail	alert[0x5]	18031	1			T77	12		T259	115		T108	6586
alert_integrity_fail	alert[0x6]	1242	1			T257	2		T108	233		T60	6
alert_integrity_fail	alert[0x7]	6931	1			T28	2		T39	1		T258	1
alert_integrity_fail	alert[0x8]	3586	1			T147	3		T339	106		T70	44
alert_integrity_fail	alert[0x9]	7576	1			T28	6		T259	443		T60	8
alert_integrity_fail	alert[0xa]	2930	1			T259	59		T27	4		T300	3
alert_integrity_fail	alert[0xb]	1317	1			T90	6		T258	1		T108	6
alert_integrity_fail	alert[0xc]	3812	1			T22	9		T259	3		T101	2
alert_integrity_fail	alert[0xd]	3001	1			T56	5		T108	8		T101	4
alert_integrity_fail	alert[0xe]	5388	1			T93	1		T259	140		T26	26
alert_integrity_fail	alert[0xf]	7160	1			T259	12		T258	4		T101	20
alert_integrity_fail	alert[0x10]	2812	1			T259	29		T108	124		T60	1
alert_integrity_fail	alert[0x11]	2769	1			T259	73		T140	5		T157	58
alert_integrity_fail	alert[0x12]	5901	1			T28	1		T77	1		T259	662
alert_integrity_fail	alert[0x13]	2409	1			T12	7		T259	786		T140	17
alert_integrity_fail	alert[0x14]	4870	1			T259	129		T258	3		T108	5
alert_integrity_fail	alert[0x15]	12412	1			T93	15		T108	2279		T66	184
alert_integrity_fail	alert[0x16]	8885	1			T53	1		T56	7		T140	10
alert_integrity_fail	alert[0x17]	10471	1			T56	2		T259	199		T26	8
alert_integrity_fail	alert[0x18]	11451	1			T28	12		T60	2		T140	17
alert_integrity_fail	alert[0x19]	4552	1			T258	11		T108	515		T140	2624
alert_integrity_fail	alert[0x1a]	3554	1			T140	284		T66	45		T117	81
alert_integrity_fail	alert[0x1b]	5143	1			T77	7		T259	26		T108	2897
alert_integrity_fail	alert[0x1c]	1365	1			T22	1		T90	16		T60	9
alert_integrity_fail	alert[0x1d]	3666	1			T28	12		T259	27		T101	2
alert_integrity_fail	alert[0x1e]	2456	1			T259	137		T108	7		T140	240
alert_integrity_fail	alert[0x1f]	6585	1			T258	9		T108	176		T140	39
alert_integrity_fail	alert[0x20]	2039	1			T257	1		T259	1		T26	1
alert_integrity_fail	alert[0x21]	2997	1			T53	6		T257	4		T28	2
alert_integrity_fail	alert[0x22]	6500	1			T259	116		T101	10		T140	521
alert_integrity_fail	alert[0x23]	2711	1			T60	2		T140	36		T66	52
alert_integrity_fail	alert[0x24]	4377	1			T90	5		T259	36		T140	623
alert_integrity_fail	alert[0x25]	2269	1			T90	7		T57	5		T259	79
alert_integrity_fail	alert[0x26]	2024	1			T28	2		T259	45		T26	11
alert_integrity_fail	alert[0x27]	6067	1			T53	1		T259	140		T108	1
alert_integrity_fail	alert[0x28]	1060	1			T91	4		T101	5		T117	129
alert_integrity_fail	alert[0x29]	4595	1			T12	1		T258	3		T340	1
alert_integrity_fail	alert[0x2a]	9052	1			T259	256		T108	1432		T140	225
alert_integrity_fail	alert[0x2b]	6115	1			T90	1		T259	31		T140	11
alert_integrity_fail	alert[0x2c]	3370	1			T22	3		T259	68		T26	1
alert_integrity_fail	alert[0x2d]	9812	1			T22	8		T39	2		T300	3
alert_integrity_fail	alert[0x2e]	5510	1			T22	4		T140	105		T66	131
alert_integrity_fail	alert[0x2f]	4913	1			T22	2		T90	12		T259	38
alert_integrity_fail	alert[0x30]	3777	1			T108	2014		T300	1		T140	106
alert_integrity_fail	alert[0x31]	3295	1			T22	2		T90	3		T56	4
alert_integrity_fail	alert[0x32]	7103	1			T90	16		T145	12		T108	17
alert_integrity_fail	alert[0x33]	7003	1			T22	11		T26	1		T258	1
alert_integrity_fail	alert[0x34]	3584	1			T259	665		T108	419		T140	22
alert_integrity_fail	alert[0x35]	6678	1			T77	3		T108	12		T66	267
alert_integrity_fail	alert[0x36]	2857	1			T259	14		T108	238		T140	27
alert_integrity_fail	alert[0x37]	9126	1			T259	78		T108	27		T300	3
alert_integrity_fail	alert[0x38]	2763	1			T259	62		T258	1		T108	89
alert_integrity_fail	alert[0x39]	6977	1			T257	2		T259	62		T108	1289
alert_integrity_fail	alert[0x3a]	11209	1			T108	51		T341	14		T66	26
alert_integrity_fail	alert[0x3b]	2128	1			T56	1		T259	40		T108	623
alert_integrity_fail	alert[0x3c]	1458	1			T140	60		T340	1		T66	24
alert_integrity_fail	alert[0x3d]	5124	1			T12	4		T39	1		T26	1
alert_integrity_fail	alert[0x3e]	5230	1			T28	49		T108	120		T340	51
alert_integrity_fail	alert[0x3f]	8966	1			T28	1		T259	69		T26	1
alert_integrity_fail	alert[0x40]	1312	1			T90	1		T28	5		T77	4
alert_ping_fail	alert[0x0]	8	1			T84	1		T79	1		T336	1
alert_ping_fail	alert[0x1]	9	1			T122	1		T155	1		T332	1
alert_ping_fail	alert[0x2]	14	1			T333	1		T334	1		T342	1
alert_ping_fail	alert[0x3]	7	1			T323	1		T106	1		T334	1
alert_ping_fail	alert[0x4]	8	1			T84	1		T333	1		T332	1
alert_ping_fail	alert[0x5]	17	1			T16	2		T79	2		T343	1
alert_ping_fail	alert[0x6]	13	1			T16	1		T335	1		T333	1
alert_ping_fail	alert[0x7]	10	1			T130	1		T79	1		T323	1
alert_ping_fail	alert[0x8]	17	1			T155	1		T79	2		T81	1
alert_ping_fail	alert[0x9]	7	1			T334	1		T344	1		T345	1
alert_ping_fail	alert[0xa]	6	1			T16	1		T84	1		T335	1
alert_ping_fail	alert[0xb]	13	1			T17	1		T79	1		T106	1
alert_ping_fail	alert[0xc]	14	1			T335	1		T336	1		T323	1
alert_ping_fail	alert[0xd]	7	1			T155	1		T346	1		T334	1
alert_ping_fail	alert[0xe]	9	1			T84	1		T122	1		T155	1
alert_ping_fail	alert[0xf]	12	1			T333	1		T79	1		T323	1
alert_ping_fail	alert[0x10]	8	1			T15	1		T342	1		T347	1
alert_ping_fail	alert[0x11]	9	1			T336	1		T106	1		T346	2
alert_ping_fail	alert[0x12]	15	1			T17	2		T130	2		T335	3
alert_ping_fail	alert[0x13]	13	1			T16	2		T155	1		T323	1
alert_ping_fail	alert[0x14]	8	1			T17	1		T348	1		T349	1
alert_ping_fail	alert[0x15]	11	1			T333	1		T155	1		T336	1
alert_ping_fail	alert[0x16]	24	1			T15	2		T17	1		T130	2
alert_ping_fail	alert[0x17]	14	1			T16	1		T155	1		T337	1
alert_ping_fail	alert[0x18]	11	1			T84	1		T130	1		T155	2
alert_ping_fail	alert[0x19]	10	1			T17	1		T106	1		T350	1
alert_ping_fail	alert[0x1a]	8	1			T84	1		T122	1		T333	1
alert_ping_fail	alert[0x1b]	13	1			T337	2		T336	2		T350	2
alert_ping_fail	alert[0x1c]	11	1			T130	1		T79	1		T337	1
alert_ping_fail	alert[0x1d]	7	1			T335	1		T346	1		T348	1
alert_ping_fail	alert[0x1e]	12	1			T130	1		T347	1		T351	1
alert_ping_fail	alert[0x1f]	12	1			T84	1		T337	1		T352	1
alert_ping_fail	alert[0x20]	9	1			T337	2		T336	1		T346	1
alert_ping_fail	alert[0x21]	16	1			T130	1		T335	1		T106	1
alert_ping_fail	alert[0x22]	16	1			T81	1		T336	1		T323	2
alert_ping_fail	alert[0x23]	8	1			T335	1		T155	1		T336	1
alert_ping_fail	alert[0x24]	5	1			T130	1		T337	1		T346	1
alert_ping_fail	alert[0x25]	13	1			T335	1		T333	1		T337	1
alert_ping_fail	alert[0x26]	11	1			T84	1		T335	1		T337	1
alert_ping_fail	alert[0x27]	13	1			T155	1		T336	1		T106	1
alert_ping_fail	alert[0x28]	10	1			T130	1		T333	1		T350	1
alert_ping_fail	alert[0x29]	10	1			T130	1		T79	1		T323	1
alert_ping_fail	alert[0x2a]	10	1			T334	1		T353	1		T303	1
alert_ping_fail	alert[0x2b]	16	1			T15	1		T84	2		T333	1
alert_ping_fail	alert[0x2c]	12	1			T17	2		T333	1		T155	1
alert_ping_fail	alert[0x2d]	13	1			T79	1		T343	1		T336	1
alert_ping_fail	alert[0x2e]	10	1			T17	1		T155	1		T348	1
alert_ping_fail	alert[0x2f]	8	1			T130	1		T350	1		T353	1
alert_ping_fail	alert[0x30]	9	1			T79	1		T81	1		T323	1
alert_ping_fail	alert[0x31]	7	1			T84	1		T337	1		T336	1
alert_ping_fail	alert[0x32]	14	1			T333	1		T155	1		T323	1
alert_ping_fail	alert[0x33]	15	1			T84	1		T335	1		T122	1
alert_ping_fail	alert[0x34]	14	1			T15	1		T130	1		T155	1
alert_ping_fail	alert[0x35]	13	1			T16	2		T17	1		T84	1
alert_ping_fail	alert[0x36]	12	1			T16	1		T84	1		T335	1
alert_ping_fail	alert[0x37]	6	1			T130	1		T155	1		T334	1
alert_ping_fail	alert[0x38]	8	1			T17	1		T343	1		T353	1
alert_ping_fail	alert[0x39]	5	1			T333	1		T79	1		T106	1
alert_ping_fail	alert[0x3a]	6	1			T16	2		T17	1		T350	2
alert_ping_fail	alert[0x3b]	11	1			T130	1		T333	1		T337	1
alert_ping_fail	alert[0x3c]	13	1			T15	1		T130	1		T335	2
alert_ping_fail	alert[0x3d]	5	1			T155	1		T336	1		T353	1
alert_ping_fail	alert[0x3e]	8	1			T338	1		T337	1		T354	1
alert_ping_fail	alert[0x3f]	3	1			T84	1		T79	1		T355	1
alert_ping_fail	alert[0x40]	6	1			T16	1		T334	1		T303	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	118813	1			T12	12		T49	1		T257	5
alert_integrity_fail	class_i[0x1]	59325	1			T53	1		T28	53		T259	6548
alert_integrity_fail	class_i[0x2]	85851	1			T257	4		T90	76		T28	23
alert_integrity_fail	class_i[0x3]	73301	1			T22	40		T53	7		T145	12
alert_ping_fail	class_i[0x0]	182	1			T15	2		T17	1		T84	5
alert_ping_fail	class_i[0x1]	164	1			T15	1		T17	11		T84	3
alert_ping_fail	class_i[0x2]	144	1			T15	2		T16	1		T84	5
alert_ping_fail	class_i[0x3]	202	1			T15	1		T16	12		T84	2