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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.21 99.99 98.67 97.09 100.00 100.00 99.38 99.36


Total test records in report: 824
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T783 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.692384505 Sep 11 04:59:59 PM UTC 24 Sep 11 05:00:09 PM UTC 24 58846944 ps
T784 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.3693787216 Sep 11 05:00:06 PM UTC 24 Sep 11 05:00:10 PM UTC 24 11470862 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2143472121 Sep 11 05:00:06 PM UTC 24 Sep 11 05:00:15 PM UTC 24 91926906 ps
T785 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.563535737 Sep 11 05:00:06 PM UTC 24 Sep 11 05:00:22 PM UTC 24 652667690 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1408822943 Sep 11 04:58:25 PM UTC 24 Sep 11 05:00:22 PM UTC 24 3112511972 ps
T786 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.370218046 Sep 11 05:00:10 PM UTC 24 Sep 11 05:00:27 PM UTC 24 663488316 ps
T787 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.3214636332 Sep 11 05:00:28 PM UTC 24 Sep 11 05:00:32 PM UTC 24 11157346 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2255093399 Sep 11 05:00:23 PM UTC 24 Sep 11 05:00:32 PM UTC 24 92426948 ps
T788 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1106047152 Sep 11 04:59:54 PM UTC 24 Sep 11 05:00:34 PM UTC 24 2753625829 ps
T789 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.3817191174 Sep 11 05:00:23 PM UTC 24 Sep 11 05:00:35 PM UTC 24 52808760 ps
T790 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.949349886 Sep 11 05:00:37 PM UTC 24 Sep 11 05:00:40 PM UTC 24 10231438 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3642106548 Sep 11 04:57:42 PM UTC 24 Sep 11 05:00:35 PM UTC 24 3871799446 ps
T791 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2446086080 Sep 11 05:00:06 PM UTC 24 Sep 11 05:00:37 PM UTC 24 1628578208 ps
T792 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.3520999693 Sep 11 05:00:36 PM UTC 24 Sep 11 05:00:39 PM UTC 24 13894384 ps
T793 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.3697584501 Sep 11 05:00:38 PM UTC 24 Sep 11 05:00:41 PM UTC 24 14869826 ps
T794 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.830483961 Sep 11 05:00:32 PM UTC 24 Sep 11 05:00:41 PM UTC 24 115647526 ps
T795 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.1462229980 Sep 11 05:00:40 PM UTC 24 Sep 11 05:00:43 PM UTC 24 33016229 ps
T796 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.4117011982 Sep 11 05:00:40 PM UTC 24 Sep 11 05:00:43 PM UTC 24 15629692 ps
T797 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.1811625099 Sep 11 05:00:41 PM UTC 24 Sep 11 05:00:44 PM UTC 24 8246073 ps
T798 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.276188864 Sep 11 05:00:41 PM UTC 24 Sep 11 05:00:44 PM UTC 24 10053055 ps
T799 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.68054426 Sep 11 05:00:35 PM UTC 24 Sep 11 05:00:45 PM UTC 24 570065847 ps
T800 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.1090937113 Sep 11 05:00:42 PM UTC 24 Sep 11 05:00:46 PM UTC 24 27411974 ps
T801 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.2650443984 Sep 11 05:00:44 PM UTC 24 Sep 11 05:00:47 PM UTC 24 6607417 ps
T802 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.1622432456 Sep 11 05:00:44 PM UTC 24 Sep 11 05:00:48 PM UTC 24 14128230 ps
T803 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.83875527 Sep 11 05:00:46 PM UTC 24 Sep 11 05:00:49 PM UTC 24 19294513 ps
T804 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.2584690305 Sep 11 05:00:46 PM UTC 24 Sep 11 05:00:49 PM UTC 24 15335514 ps
T805 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.174504370 Sep 11 05:00:46 PM UTC 24 Sep 11 05:00:49 PM UTC 24 10612401 ps
T806 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.4221662521 Sep 11 05:00:47 PM UTC 24 Sep 11 05:00:50 PM UTC 24 22189091 ps
T807 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.2858323302 Sep 11 05:00:47 PM UTC 24 Sep 11 05:00:50 PM UTC 24 10933924 ps
T808 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.1224720210 Sep 11 05:00:48 PM UTC 24 Sep 11 05:00:51 PM UTC 24 25177215 ps
T809 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.748568128 Sep 11 05:00:48 PM UTC 24 Sep 11 05:00:51 PM UTC 24 27951237 ps
T810 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.1406431304 Sep 11 05:00:50 PM UTC 24 Sep 11 05:00:53 PM UTC 24 7866089 ps
T811 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.476449779 Sep 11 05:00:50 PM UTC 24 Sep 11 05:00:53 PM UTC 24 20950721 ps
T812 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.1420181088 Sep 11 05:00:50 PM UTC 24 Sep 11 05:00:54 PM UTC 24 7975490 ps
T813 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.1268284525 Sep 11 05:00:50 PM UTC 24 Sep 11 05:00:54 PM UTC 24 9387019 ps
T814 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.3828536779 Sep 11 05:00:52 PM UTC 24 Sep 11 05:00:55 PM UTC 24 7618591 ps
T815 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.692381556 Sep 11 05:00:51 PM UTC 24 Sep 11 05:00:55 PM UTC 24 10278733 ps
T816 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.2374961418 Sep 11 05:00:52 PM UTC 24 Sep 11 05:00:55 PM UTC 24 7393274 ps
T817 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.3995055223 Sep 11 05:00:55 PM UTC 24 Sep 11 05:00:58 PM UTC 24 10424875 ps
T818 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.1705377347 Sep 11 05:00:55 PM UTC 24 Sep 11 05:00:58 PM UTC 24 7847990 ps
T819 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.2069230292 Sep 11 05:00:55 PM UTC 24 Sep 11 05:00:58 PM UTC 24 6285099 ps
T820 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.190300875 Sep 11 05:00:55 PM UTC 24 Sep 11 05:00:58 PM UTC 24 11371844 ps
T821 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.244626760 Sep 11 05:00:56 PM UTC 24 Sep 11 05:00:59 PM UTC 24 17536305 ps
T822 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.401414809 Sep 11 05:00:56 PM UTC 24 Sep 11 05:00:59 PM UTC 24 18796167 ps
T823 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.859112599 Sep 11 05:00:33 PM UTC 24 Sep 11 05:01:08 PM UTC 24 751969011 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1091303254 Sep 11 04:57:24 PM UTC 24 Sep 11 05:01:25 PM UTC 24 6464709313 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2515367570 Sep 11 04:57:54 PM UTC 24 Sep 11 05:01:26 PM UTC 24 8890504518 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3561724909 Sep 11 05:00:16 PM UTC 24 Sep 11 05:02:05 PM UTC 24 1662546039 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3565312003 Sep 11 04:59:19 PM UTC 24 Sep 11 05:02:05 PM UTC 24 2079703743 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3597685322 Sep 11 04:57:02 PM UTC 24 Sep 11 05:02:24 PM UTC 24 16372328944 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2565032059 Sep 11 04:54:23 PM UTC 24 Sep 11 05:02:33 PM UTC 24 25863415395 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.4261183094 Sep 11 04:56:44 PM UTC 24 Sep 11 05:02:50 PM UTC 24 2340017630 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3141619151 Sep 11 04:59:41 PM UTC 24 Sep 11 05:03:02 PM UTC 24 6795694580 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.698999551 Sep 11 04:53:49 PM UTC 24 Sep 11 05:03:21 PM UTC 24 20539093387 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2354056668 Sep 11 04:59:57 PM UTC 24 Sep 11 05:03:33 PM UTC 24 7542073281 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2082807928 Sep 11 04:53:19 PM UTC 24 Sep 11 05:04:01 PM UTC 24 5911015068 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2688651675 Sep 11 04:59:09 PM UTC 24 Sep 11 05:04:05 PM UTC 24 7594336544 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.844890244 Sep 11 04:56:04 PM UTC 24 Sep 11 05:04:27 PM UTC 24 110037812056 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2493485664 Sep 11 04:58:41 PM UTC 24 Sep 11 05:05:48 PM UTC 24 7819132099 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.379675448 Sep 11 04:57:53 PM UTC 24 Sep 11 05:05:53 PM UTC 24 29351475862 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3685784282 Sep 11 04:58:23 PM UTC 24 Sep 11 05:07:22 PM UTC 24 32981537498 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3186506685 Sep 11 04:57:01 PM UTC 24 Sep 11 05:07:26 PM UTC 24 5999575397 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2176068635 Sep 11 04:59:56 PM UTC 24 Sep 11 05:09:12 PM UTC 24 10077127417 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3825942193 Sep 11 04:59:09 PM UTC 24 Sep 11 05:09:15 PM UTC 24 30628817224 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1312455814 Sep 11 04:55:32 PM UTC 24 Sep 11 05:09:45 PM UTC 24 200475571436 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3178557450 Sep 11 04:58:40 PM UTC 24 Sep 11 05:10:11 PM UTC 24 8513060785 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3649624228 Sep 11 04:55:01 PM UTC 24 Sep 11 05:10:45 PM UTC 24 52606024296 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2811702105 Sep 11 04:53:22 PM UTC 24 Sep 11 05:11:14 PM UTC 24 135468670351 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.4027334555 Sep 11 05:00:11 PM UTC 24 Sep 11 05:11:38 PM UTC 24 4538212681 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3010264073 Sep 11 04:59:19 PM UTC 24 Sep 11 05:14:51 PM UTC 24 59480818908 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3637388603 Sep 11 04:56:24 PM UTC 24 Sep 11 05:15:49 PM UTC 24 65773562715 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3811524497 Sep 11 04:59:37 PM UTC 24 Sep 11 05:16:03 PM UTC 24 55391118493 ps
T824 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1391390885 Sep 11 04:57:23 PM UTC 24 Sep 11 05:16:31 PM UTC 24 17023864588 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.610392741 Sep 11 04:57:41 PM UTC 24 Sep 11 05:18:24 PM UTC 24 68693183011 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/0.alert_handler_sig_int_fail.3687997958
Short name T22
Test name
Test status
Simulation time 249311586 ps
CPU time 36.02 seconds
Started Sep 11 01:56:32 PM UTC 24
Finished Sep 11 01:57:09 PM UTC 24
Peak memory 263000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687997958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3687997958
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all_with_rand_reset.1851301491
Short name T36
Test name
Test status
Simulation time 5749815534 ps
CPU time 138.69 seconds
Started Sep 11 01:57:09 PM UTC 24
Finished Sep 11 01:59:31 PM UTC 24
Peak memory 279796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1851301491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.al
ert_handler_stress_all_with_rand_reset.1851301491
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy_stress.2917352547
Short name T2
Test name
Test status
Simulation time 700219914 ps
CPU time 14.7 seconds
Started Sep 11 01:56:33 PM UTC 24
Finished Sep 11 01:56:49 PM UTC 24
Peak memory 262900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917352547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2917352547
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/1.alert_handler_sec_cm.4070070376
Short name T7
Test name
Test status
Simulation time 1847876270 ps
CPU time 36.54 seconds
Started Sep 11 01:57:10 PM UTC 24
Finished Sep 11 01:57:48 PM UTC 24
Peak memory 295260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070070376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.4070070376
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1305275500
Short name T199
Test name
Test status
Simulation time 303272741 ps
CPU time 30.63 seconds
Started Sep 11 04:53:29 PM UTC 24
Finished Sep 11 04:54:01 PM UTC 24
Peak memory 260632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305275500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1305275500
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy.2872029245
Short name T56
Test name
Test status
Simulation time 9288063122 ps
CPU time 928.04 seconds
Started Sep 11 01:56:32 PM UTC 24
Finished Sep 11 02:12:10 PM UTC 24
Peak memory 285492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872029245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2872029245
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all_with_rand_reset.2903128033
Short name T110
Test name
Test status
Simulation time 13888289340 ps
CPU time 314.3 seconds
Started Sep 11 02:47:07 PM UTC 24
Finished Sep 11 02:52:26 PM UTC 24
Peak memory 279476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2903128033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.a
lert_handler_stress_all_with_rand_reset.2903128033
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_classes.1854597875
Short name T3
Test name
Test status
Simulation time 114496893 ps
CPU time 6.65 seconds
Started Sep 11 01:56:45 PM UTC 24
Finished Sep 11 01:56:53 PM UTC 24
Peak memory 262996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854597875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1854597875
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all.1022910933
Short name T66
Test name
Test status
Simulation time 10890178265 ps
CPU time 1091.73 seconds
Started Sep 11 02:17:28 PM UTC 24
Finished Sep 11 02:35:52 PM UTC 24
Peak memory 302260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022910933 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_stress_all.1022910933
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/12.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3358783364
Short name T170
Test name
Test status
Simulation time 2156148979 ps
CPU time 275.71 seconds
Started Sep 11 04:54:27 PM UTC 24
Finished Sep 11 04:59:07 PM UTC 24
Peak memory 279380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358783364 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_errors.3358783364
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg.2572563481
Short name T76
Test name
Test status
Simulation time 26079935627 ps
CPU time 1075.51 seconds
Started Sep 11 01:57:38 PM UTC 24
Finished Sep 11 02:15:47 PM UTC 24
Peak memory 285816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572563481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2572563481
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg_stub_clk.1346012157
Short name T139
Test name
Test status
Simulation time 201625041545 ps
CPU time 2917.46 seconds
Started Sep 11 01:56:32 PM UTC 24
Finished Sep 11 02:45:42 PM UTC 24
Peak memory 304936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346012157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1346012157
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all.3862788829
Short name T700
Test name
Test status
Simulation time 17668773113 ps
CPU time 1631.09 seconds
Started Sep 11 03:37:45 PM UTC 24
Finished Sep 11 04:05:16 PM UTC 24
Peak memory 318260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862788829 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_stress_all.3862788829
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/49.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3141619151
Short name T176
Test name
Test status
Simulation time 6795694580 ps
CPU time 197.21 seconds
Started Sep 11 04:59:41 PM UTC 24
Finished Sep 11 05:03:02 PM UTC 24
Peak memory 285592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141619151 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_errors.3141619151
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all_with_rand_reset.3189992602
Short name T28
Test name
Test status
Simulation time 4024675497 ps
CPU time 195.6 seconds
Started Sep 11 02:07:17 PM UTC 24
Finished Sep 11 02:10:36 PM UTC 24
Peak memory 279540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3189992602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.al
ert_handler_stress_all_with_rand_reset.3189992602
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg.716307440
Short name T114
Test name
Test status
Simulation time 115583860310 ps
CPU time 1646.6 seconds
Started Sep 11 02:30:26 PM UTC 24
Finished Sep 11 02:58:12 PM UTC 24
Peak memory 285564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716307440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.716307440
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/19.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3637388603
Short name T193
Test name
Test status
Simulation time 65773562715 ps
CPU time 1150.6 seconds
Started Sep 11 04:56:24 PM UTC 24
Finished Sep 11 05:15:49 PM UTC 24
Peak memory 279444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637388603 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shado
w_reg_errors_with_csr_rw.3637388603
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/6.alert_handler_ping_timeout.1296816312
Short name T155
Test name
Test status
Simulation time 28389217575 ps
CPU time 625.57 seconds
Started Sep 11 02:03:40 PM UTC 24
Finished Sep 11 02:14:13 PM UTC 24
Peak memory 263100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296816312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1296816312
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/6.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_intr_timeout.2201001589
Short name T42
Test name
Test status
Simulation time 872852857 ps
CPU time 22.89 seconds
Started Sep 11 01:56:51 PM UTC 24
Finished Sep 11 01:57:15 PM UTC 24
Peak memory 269108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201001589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2201001589
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1871635163
Short name T164
Test name
Test status
Simulation time 8379447053 ps
CPU time 261.65 seconds
Started Sep 11 04:53:24 PM UTC 24
Finished Sep 11 04:57:49 PM UTC 24
Peak memory 285584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871635163 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors.1871635163
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy.1028397802
Short name T140
Test name
Test status
Simulation time 51247260984 ps
CPU time 1716.67 seconds
Started Sep 11 01:58:22 PM UTC 24
Finished Sep 11 02:27:19 PM UTC 24
Peak memory 285756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028397802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1028397802
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.698999551
Short name T181
Test name
Test status
Simulation time 20539093387 ps
CPU time 565.16 seconds
Started Sep 11 04:53:49 PM UTC 24
Finished Sep 11 05:03:21 PM UTC 24
Peak memory 285596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698999551 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow
_reg_errors_with_csr_rw.698999551
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_intr_test.244042552
Short name T387
Test name
Test status
Simulation time 13908352 ps
CPU time 2.42 seconds
Started Sep 11 04:54:42 PM UTC 24
Finished Sep 11 04:54:46 PM UTC 24
Peak memory 250404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244042552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.244042552
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all.4209178187
Short name T93
Test name
Test status
Simulation time 12853852654 ps
CPU time 301.4 seconds
Started Sep 11 02:01:58 PM UTC 24
Finished Sep 11 02:07:04 PM UTC 24
Peak memory 269428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209178187 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_stress_all.4209178187
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/5.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/11.alert_handler_ping_timeout.1328213699
Short name T336
Test name
Test status
Simulation time 13293994704 ps
CPU time 502.59 seconds
Started Sep 11 02:15:35 PM UTC 24
Finished Sep 11 02:24:03 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328213699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1328213699
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg.2628129649
Short name T364
Test name
Test status
Simulation time 40846347574 ps
CPU time 2093.24 seconds
Started Sep 11 02:18:49 PM UTC 24
Finished Sep 11 02:54:05 PM UTC 24
Peak memory 299828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628129649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2628129649
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/13.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1942219710
Short name T211
Test name
Test status
Simulation time 1253095618 ps
CPU time 93.25 seconds
Started Sep 11 04:53:59 PM UTC 24
Finished Sep 11 04:55:34 PM UTC 24
Peak memory 262688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942219710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1942219710
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3178557450
Short name T198
Test name
Test status
Simulation time 8513060785 ps
CPU time 681.3 seconds
Started Sep 11 04:58:40 PM UTC 24
Finished Sep 11 05:10:11 PM UTC 24
Peak memory 279444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178557450 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shad
ow_reg_errors_with_csr_rw.3178557450
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/4.alert_handler_ping_timeout.3955761142
Short name T130
Test name
Test status
Simulation time 11064629763 ps
CPU time 432.19 seconds
Started Sep 11 02:00:18 PM UTC 24
Finished Sep 11 02:07:36 PM UTC 24
Peak memory 269180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955761142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3955761142
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/17.alert_handler_ping_timeout.3453853758
Short name T334
Test name
Test status
Simulation time 55399122020 ps
CPU time 391.96 seconds
Started Sep 11 02:25:18 PM UTC 24
Finished Sep 11 02:31:55 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453853758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3453853758
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/3.alert_handler_sig_int_fail.3961241348
Short name T49
Test name
Test status
Simulation time 3113838593 ps
CPU time 47.85 seconds
Started Sep 11 01:58:20 PM UTC 24
Finished Sep 11 01:59:10 PM UTC 24
Peak memory 263192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961241348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3961241348
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg.3240346686
Short name T356
Test name
Test status
Simulation time 169311635575 ps
CPU time 2515.68 seconds
Started Sep 11 01:57:04 PM UTC 24
Finished Sep 11 02:39:28 PM UTC 24
Peak memory 295804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240346686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3240346686
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1091303254
Short name T167
Test name
Test status
Simulation time 6464709313 ps
CPU time 236.79 seconds
Started Sep 11 04:57:24 PM UTC 24
Finished Sep 11 05:01:25 PM UTC 24
Peak memory 285728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091303254 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_errors.1091303254
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg.2505822099
Short name T81
Test name
Test status
Simulation time 44237086870 ps
CPU time 1063.33 seconds
Started Sep 11 01:58:45 PM UTC 24
Finished Sep 11 02:16:41 PM UTC 24
Peak memory 295728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505822099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2505822099
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/4.alert_handler_sig_int_fail.2101274543
Short name T53
Test name
Test status
Simulation time 419541121 ps
CPU time 37.1 seconds
Started Sep 11 02:00:00 PM UTC 24
Finished Sep 11 02:00:43 PM UTC 24
Peak memory 263000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101274543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2101274543
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/26.alert_handler_sig_int_fail.3413202676
Short name T158
Test name
Test status
Simulation time 736226845 ps
CPU time 29.98 seconds
Started Sep 11 02:46:33 PM UTC 24
Finished Sep 11 02:47:04 PM UTC 24
Peak memory 269404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413202676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3413202676
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/26.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.4261183094
Short name T179
Test name
Test status
Simulation time 2340017630 ps
CPU time 360.79 seconds
Started Sep 11 04:56:44 PM UTC 24
Finished Sep 11 05:02:50 PM UTC 24
Peak memory 283540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261183094 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shado
w_reg_errors_with_csr_rw.4261183094
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all.1896386851
Short name T281
Test name
Test status
Simulation time 151708713535 ps
CPU time 2144.5 seconds
Started Sep 11 02:28:39 PM UTC 24
Finished Sep 11 03:04:48 PM UTC 24
Peak memory 297860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896386851 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_stress_all.1896386851
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/18.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg.4277444922
Short name T383
Test name
Test status
Simulation time 114263408086 ps
CPU time 3302.31 seconds
Started Sep 11 02:54:30 PM UTC 24
Finished Sep 11 03:50:08 PM UTC 24
Peak memory 304608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277444922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.4277444922
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/30.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_aliasing.229708995
Short name T226
Test name
Test status
Simulation time 2119497850 ps
CPU time 78.32 seconds
Started Sep 11 04:53:21 PM UTC 24
Finished Sep 11 04:54:42 PM UTC 24
Peak memory 250320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229708995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/al
ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.229708995
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_intr_timeout.4099743430
Short name T13
Test name
Test status
Simulation time 934514462 ps
CPU time 31.46 seconds
Started Sep 11 01:56:32 PM UTC 24
Finished Sep 11 01:57:04 PM UTC 24
Peak memory 269036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099743430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.4099743430
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3186506685
Short name T185
Test name
Test status
Simulation time 5999575397 ps
CPU time 616.14 seconds
Started Sep 11 04:57:01 PM UTC 24
Finished Sep 11 05:07:26 PM UTC 24
Peak memory 279444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186506685 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shado
w_reg_errors_with_csr_rw.3186506685
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_intr_test.3472357311
Short name T255
Test name
Test status
Simulation time 12259589 ps
CPU time 2.06 seconds
Started Sep 11 04:54:02 PM UTC 24
Finished Sep 11 04:54:05 PM UTC 24
Peak memory 250528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472357311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3472357311
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/21.alert_handler_entropy.2684062285
Short name T307
Test name
Test status
Simulation time 30035785555 ps
CPU time 877.96 seconds
Started Sep 11 02:35:45 PM UTC 24
Finished Sep 11 02:50:34 PM UTC 24
Peak memory 297848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684062285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2684062285
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/21.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/24.alert_handler_ping_timeout.1990774573
Short name T342
Test name
Test status
Simulation time 104112336915 ps
CPU time 274.59 seconds
Started Sep 11 02:41:36 PM UTC 24
Finished Sep 11 02:46:15 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990774573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1990774573
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/24.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg.2330117662
Short name T365
Test name
Test status
Simulation time 144644393587 ps
CPU time 2526.69 seconds
Started Sep 11 02:46:46 PM UTC 24
Finished Sep 11 03:29:22 PM UTC 24
Peak memory 304680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330117662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.2330117662
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/26.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all.3679489848
Short name T301
Test name
Test status
Simulation time 74660011829 ps
CPU time 1688.78 seconds
Started Sep 11 02:44:33 PM UTC 24
Finished Sep 11 03:13:02 PM UTC 24
Peak memory 301940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679489848 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_stress_all.3679489848
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/25.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.254614137
Short name T175
Test name
Test status
Simulation time 3256983597 ps
CPU time 211.63 seconds
Started Sep 11 04:55:02 PM UTC 24
Finished Sep 11 04:58:37 PM UTC 24
Peak memory 279584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254614137 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors.254614137
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2082585791
Short name T212
Test name
Test status
Simulation time 32892469 ps
CPU time 3.23 seconds
Started Sep 11 04:59:49 PM UTC 24
Finished Sep 11 04:59:53 PM UTC 24
Peak memory 250520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082585791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2082585791
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/17.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2082807928
Short name T182
Test name
Test status
Simulation time 5911015068 ps
CPU time 633.95 seconds
Started Sep 11 04:53:19 PM UTC 24
Finished Sep 11 05:04:01 PM UTC 24
Peak memory 285588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082807928 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shado
w_reg_errors_with_csr_rw.2082807928
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/6.alert_handler_sig_int_fail.632906867
Short name T90
Test name
Test status
Simulation time 7547187597 ps
CPU time 68.17 seconds
Started Sep 11 02:03:23 PM UTC 24
Finished Sep 11 02:04:33 PM UTC 24
Peak memory 269500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632906867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.632906867
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/6.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3551069291
Short name T163
Test name
Test status
Simulation time 3192541584 ps
CPU time 205.01 seconds
Started Sep 11 04:53:20 PM UTC 24
Finished Sep 11 04:56:48 PM UTC 24
Peak memory 279456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551069291 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors.3551069291
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/10.alert_handler_stress_all.2371584560
Short name T273
Test name
Test status
Simulation time 46897559794 ps
CPU time 2713.22 seconds
Started Sep 11 02:13:16 PM UTC 24
Finished Sep 11 02:58:59 PM UTC 24
Peak memory 304672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371584560 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_stress_all.2371584560
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/10.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg.2425716373
Short name T357
Test name
Test status
Simulation time 141442430759 ps
CPU time 2223.44 seconds
Started Sep 11 02:40:17 PM UTC 24
Finished Sep 11 03:17:46 PM UTC 24
Peak memory 288224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425716373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2425716373
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/23.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all_with_rand_reset.2425411463
Short name T282
Test name
Test status
Simulation time 5800587962 ps
CPU time 704.65 seconds
Started Sep 11 03:02:42 PM UTC 24
Finished Sep 11 03:14:36 PM UTC 24
Peak memory 297972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2425411463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.a
lert_handler_stress_all_with_rand_reset.2425411463
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg.1625295485
Short name T374
Test name
Test status
Simulation time 39495840174 ps
CPU time 2642.5 seconds
Started Sep 11 03:23:37 PM UTC 24
Finished Sep 11 04:08:11 PM UTC 24
Peak memory 288224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625295485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1625295485
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/42.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_intr_timeout.2855691137
Short name T97
Test name
Test status
Simulation time 3489869268 ps
CPU time 64.86 seconds
Started Sep 11 02:08:28 PM UTC 24
Finished Sep 11 02:09:34 PM UTC 24
Peak memory 269172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855691137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2855691137
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/9.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/9.alert_handler_ping_timeout.3078807656
Short name T79
Test name
Test status
Simulation time 51438178785 ps
CPU time 380.69 seconds
Started Sep 11 02:09:54 PM UTC 24
Finished Sep 11 02:16:20 PM UTC 24
Peak memory 263228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078807656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3078807656
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/9.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg_stub_clk.2921594028
Short name T299
Test name
Test status
Simulation time 29208053267 ps
CPU time 1188.42 seconds
Started Sep 11 01:57:05 PM UTC 24
Finished Sep 11 02:17:08 PM UTC 24
Peak memory 285820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921594028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2921594028
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/0.alert_handler_alert_accum_saturation.1257468646
Short name T1
Test name
Test status
Simulation time 329647923 ps
CPU time 5.45 seconds
Started Sep 11 01:56:33 PM UTC 24
Finished Sep 11 01:56:39 PM UTC 24
Peak memory 263228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257468646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1257468646
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/1.alert_handler_alert_accum_saturation.3832968318
Short name T23
Test name
Test status
Simulation time 164682622 ps
CPU time 5.79 seconds
Started Sep 11 01:57:05 PM UTC 24
Finished Sep 11 01:57:12 PM UTC 24
Peak memory 263236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832968318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3832968318
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/12.alert_handler_alert_accum_saturation.1954460333
Short name T246
Test name
Test status
Simulation time 101052943 ps
CPU time 7.08 seconds
Started Sep 11 02:17:39 PM UTC 24
Finished Sep 11 02:17:48 PM UTC 24
Peak memory 263168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954460333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1954460333
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/12.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/13.alert_handler_alert_accum_saturation.92862192
Short name T247
Test name
Test status
Simulation time 19425485 ps
CPU time 3.24 seconds
Started Sep 11 02:19:08 PM UTC 24
Finished Sep 11 02:19:12 PM UTC 24
Peak memory 263172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92862192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_h
andler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_h
andler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.92862192
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/13.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all.1811113844
Short name T103
Test name
Test status
Simulation time 157797583781 ps
CPU time 2506.66 seconds
Started Sep 11 01:57:05 PM UTC 24
Finished Sep 11 02:39:21 PM UTC 24
Peak memory 301868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811113844 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_stress_all.1811113844
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/10.alert_handler_ping_timeout.2021577254
Short name T337
Test name
Test status
Simulation time 57300590947 ps
CPU time 479.79 seconds
Started Sep 11 02:12:39 PM UTC 24
Finished Sep 11 02:20:44 PM UTC 24
Peak memory 263040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021577254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2021577254
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all_with_rand_reset.924956279
Short name T157
Test name
Test status
Simulation time 9927085744 ps
CPU time 380.93 seconds
Started Sep 11 02:37:01 PM UTC 24
Finished Sep 11 02:43:27 PM UTC 24
Peak memory 285692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=924956279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.al
ert_handler_stress_all_with_rand_reset.924956279
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all.4124487669
Short name T285
Test name
Test status
Simulation time 67784122521 ps
CPU time 1177.42 seconds
Started Sep 11 03:17:06 PM UTC 24
Finished Sep 11 03:36:58 PM UTC 24
Peak memory 281388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124487669 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_stress_all.4124487669
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/39.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all.1129294642
Short name T290
Test name
Test status
Simulation time 1912531957 ps
CPU time 47.24 seconds
Started Sep 11 03:33:42 PM UTC 24
Finished Sep 11 03:34:31 PM UTC 24
Peak memory 269108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129294642 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_stress_all.1129294642
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/47.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3811524497
Short name T189
Test name
Test status
Simulation time 55391118493 ps
CPU time 974.91 seconds
Started Sep 11 04:59:37 PM UTC 24
Finished Sep 11 05:16:03 PM UTC 24
Peak memory 279444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811524497 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shad
ow_reg_errors_with_csr_rw.3811524497
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/0.alert_handler_sec_cm.3722605583
Short name T4
Test name
Test status
Simulation time 1393778898 ps
CPU time 31.69 seconds
Started Sep 11 01:56:36 PM UTC 24
Finished Sep 11 01:57:09 PM UTC 24
Peak memory 295260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722605583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3722605583
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg.966781529
Short name T34
Test name
Test status
Simulation time 24141107973 ps
CPU time 777.42 seconds
Started Sep 11 03:26:18 PM UTC 24
Finished Sep 11 03:39:26 PM UTC 24
Peak memory 279608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966781529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.966781529
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/43.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_intr_test.2177701663
Short name T202
Test name
Test status
Simulation time 21780221 ps
CPU time 2.29 seconds
Started Sep 11 04:53:20 PM UTC 24
Finished Sep 11 04:53:23 PM UTC 24
Peak memory 250592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177701663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2177701663
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_alert_accum.1264628099
Short name T50
Test name
Test status
Simulation time 2274784577 ps
CPU time 179.21 seconds
Started Sep 11 01:56:32 PM UTC 24
Finished Sep 11 01:59:34 PM UTC 24
Peak memory 269172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264628099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1264628099
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/0.alert_handler_ping_timeout.2526174788
Short name T16
Test name
Test status
Simulation time 11878020189 ps
CPU time 278.06 seconds
Started Sep 11 01:56:32 PM UTC 24
Finished Sep 11 02:01:14 PM UTC 24
Peak memory 263036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526174788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2526174788
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/14.alert_handler_smoke.439223381
Short name T298
Test name
Test status
Simulation time 885411180 ps
CPU time 73.63 seconds
Started Sep 11 02:19:20 PM UTC 24
Finished Sep 11 02:20:35 PM UTC 24
Peak memory 269036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439223381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.439223381
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/14.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg.2350472922
Short name T370
Test name
Test status
Simulation time 26521173382 ps
CPU time 1190.93 seconds
Started Sep 11 02:22:21 PM UTC 24
Finished Sep 11 02:42:25 PM UTC 24
Peak memory 285564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350472922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2350472922
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/15.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/18.alert_handler_ping_timeout.1161961325
Short name T346
Test name
Test status
Simulation time 8222817167 ps
CPU time 221.1 seconds
Started Sep 11 02:28:03 PM UTC 24
Finished Sep 11 02:31:47 PM UTC 24
Peak memory 263296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161961325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1161961325
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/18.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all.3185431429
Short name T136
Test name
Test status
Simulation time 135684944684 ps
CPU time 2392.04 seconds
Started Sep 11 01:57:44 PM UTC 24
Finished Sep 11 02:38:03 PM UTC 24
Peak memory 301940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185431429 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_stress_all.3185431429
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/24.alert_handler_smoke.3584526398
Short name T274
Test name
Test status
Simulation time 2383012986 ps
CPU time 89.37 seconds
Started Sep 11 02:40:38 PM UTC 24
Finished Sep 11 02:42:10 PM UTC 24
Peak memory 269432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584526398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3584526398
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/24.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/28.alert_handler_sig_int_fail.3177405200
Short name T278
Test name
Test status
Simulation time 780974541 ps
CPU time 28.93 seconds
Started Sep 11 02:50:15 PM UTC 24
Finished Sep 11 02:50:45 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177405200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3177405200
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/28.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all.674263012
Short name T284
Test name
Test status
Simulation time 101011411183 ps
CPU time 1562.77 seconds
Started Sep 11 02:54:46 PM UTC 24
Finished Sep 11 03:21:07 PM UTC 24
Peak memory 281388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674263012 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_stress_all.674263012
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/30.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all.2756398842
Short name T275
Test name
Test status
Simulation time 5115776022 ps
CPU time 104.8 seconds
Started Sep 11 03:00:31 PM UTC 24
Finished Sep 11 03:02:18 PM UTC 24
Peak memory 269440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756398842 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_stress_all.2756398842
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/32.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all_with_rand_reset.3036014185
Short name T276
Test name
Test status
Simulation time 10853320365 ps
CPU time 387.85 seconds
Started Sep 11 03:08:12 PM UTC 24
Finished Sep 11 03:14:45 PM UTC 24
Peak memory 281588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3036014185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.a
lert_handler_stress_all_with_rand_reset.3036014185
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/39.alert_handler_sig_int_fail.2894753234
Short name T288
Test name
Test status
Simulation time 999399666 ps
CPU time 19.37 seconds
Started Sep 11 03:16:12 PM UTC 24
Finished Sep 11 03:16:32 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894753234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2894753234
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/39.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/46.alert_handler_sig_int_fail.3411100997
Short name T286
Test name
Test status
Simulation time 1006361555 ps
CPU time 40.19 seconds
Started Sep 11 03:30:57 PM UTC 24
Finished Sep 11 03:31:38 PM UTC 24
Peak memory 269108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411100997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3411100997
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/46.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy.3663052092
Short name T108
Test name
Test status
Simulation time 47661256342 ps
CPU time 1511.61 seconds
Started Sep 11 01:56:55 PM UTC 24
Finished Sep 11 02:22:24 PM UTC 24
Peak memory 302204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663052092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3663052092
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2688651675
Short name T190
Test name
Test status
Simulation time 7594336544 ps
CPU time 291.73 seconds
Started Sep 11 04:59:09 PM UTC 24
Finished Sep 11 05:04:05 PM UTC 24
Peak memory 285588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688651675 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors.2688651675
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/0.alert_handler_smoke.3489012539
Short name T14
Test name
Test status
Simulation time 1041743187 ps
CPU time 32.12 seconds
Started Sep 11 01:56:30 PM UTC 24
Finished Sep 11 01:57:04 PM UTC 24
Peak memory 262892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489012539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3489012539
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_intg_err.4147672128
Short name T207
Test name
Test status
Simulation time 174332046 ps
CPU time 5.53 seconds
Started Sep 11 04:55:35 PM UTC 24
Finished Sep 11 04:55:42 PM UTC 24
Peak memory 250464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147672128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.4147672128
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/5.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_intg_err.726011048
Short name T200
Test name
Test status
Simulation time 943309515 ps
CPU time 98.03 seconds
Started Sep 11 04:53:20 PM UTC 24
Finished Sep 11 04:55:00 PM UTC 24
Peak memory 252508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726011048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.726011048
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3143197708
Short name T205
Test name
Test status
Simulation time 3841014215 ps
CPU time 68.01 seconds
Started Sep 11 04:58:08 PM UTC 24
Finished Sep 11 04:59:17 PM UTC 24
Peak memory 252556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143197708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3143197708
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/12.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3594862906
Short name T214
Test name
Test status
Simulation time 4921366747 ps
CPU time 103.22 seconds
Started Sep 11 04:55:05 PM UTC 24
Finished Sep 11 04:56:50 PM UTC 24
Peak memory 252568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594862906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3594862906
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3642106548
Short name T169
Test name
Test status
Simulation time 3871799446 ps
CPU time 170.36 seconds
Started Sep 11 04:57:42 PM UTC 24
Finished Sep 11 05:00:35 PM UTC 24
Peak memory 283540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642106548 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_errors.3642106548
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_intg_err.4141712880
Short name T215
Test name
Test status
Simulation time 4393707972 ps
CPU time 71.45 seconds
Started Sep 11 04:58:50 PM UTC 24
Finished Sep 11 05:00:04 PM UTC 24
Peak memory 252632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141712880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.4141712880
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/14.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3010264073
Short name T191
Test name
Test status
Simulation time 59480818908 ps
CPU time 920.98 seconds
Started Sep 11 04:59:19 PM UTC 24
Finished Sep 11 05:14:51 PM UTC 24
Peak memory 279584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010264073 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shad
ow_reg_errors_with_csr_rw.3010264073
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2143472121
Short name T213
Test name
Test status
Simulation time 91926906 ps
CPU time 7.38 seconds
Started Sep 11 05:00:06 PM UTC 24
Finished Sep 11 05:00:15 PM UTC 24
Peak memory 250384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143472121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2143472121
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/18.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3561724909
Short name T172
Test name
Test status
Simulation time 1662546039 ps
CPU time 106.62 seconds
Started Sep 11 05:00:16 PM UTC 24
Finished Sep 11 05:02:05 PM UTC 24
Peak memory 279316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561724909 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors.3561724909
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_intg_err.19805703
Short name T210
Test name
Test status
Simulation time 190131039 ps
CPU time 4.42 seconds
Started Sep 11 04:57:08 PM UTC 24
Finished Sep 11 04:57:13 PM UTC 24
Peak memory 250388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19805703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.19805703
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/9.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3002163276
Short name T208
Test name
Test status
Simulation time 37018061 ps
CPU time 4.7 seconds
Started Sep 11 04:57:27 PM UTC 24
Finished Sep 11 04:57:33 PM UTC 24
Peak memory 250376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002163276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3002163276
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/10.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1462108118
Short name T221
Test name
Test status
Simulation time 60043772 ps
CPU time 3.52 seconds
Started Sep 11 04:57:43 PM UTC 24
Finished Sep 11 04:57:48 PM UTC 24
Peak memory 250520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462108118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1462108118
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/11.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1074708883
Short name T209
Test name
Test status
Simulation time 187588173 ps
CPU time 2.62 seconds
Started Sep 11 04:59:26 PM UTC 24
Finished Sep 11 04:59:30 PM UTC 24
Peak memory 250520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074708883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1074708883
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/16.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2255093399
Short name T216
Test name
Test status
Simulation time 92426948 ps
CPU time 8.03 seconds
Started Sep 11 05:00:23 PM UTC 24
Finished Sep 11 05:00:32 PM UTC 24
Peak memory 250388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255093399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2255093399
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/19.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3710615867
Short name T201
Test name
Test status
Simulation time 1879688693 ps
CPU time 33.59 seconds
Started Sep 11 04:54:41 PM UTC 24
Finished Sep 11 04:55:16 PM UTC 24
Peak memory 252440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710615867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3710615867
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3417861814
Short name T220
Test name
Test status
Simulation time 187209186 ps
CPU time 3.87 seconds
Started Sep 11 04:56:17 PM UTC 24
Finished Sep 11 04:56:22 PM UTC 24
Peak memory 252576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417861814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3417861814
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/6.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3036925274
Short name T206
Test name
Test status
Simulation time 102984252 ps
CPU time 4.56 seconds
Started Sep 11 04:56:38 PM UTC 24
Finished Sep 11 04:56:43 PM UTC 24
Peak memory 250392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036925274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3036925274
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/7.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1062208056
Short name T219
Test name
Test status
Simulation time 2447687920 ps
CPU time 50.53 seconds
Started Sep 11 04:56:49 PM UTC 24
Finished Sep 11 04:57:41 PM UTC 24
Peak memory 252568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062208056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1062208056
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/8.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg_stub_clk.2964147413
Short name T33
Test name
Test status
Simulation time 14509526945 ps
CPU time 971.7 seconds
Started Sep 11 02:12:57 PM UTC 24
Finished Sep 11 02:29:21 PM UTC 24
Peak memory 285568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964147413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2964147413
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/10.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3304743966
Short name T722
Test name
Test status
Simulation time 6530363824 ps
CPU time 201.17 seconds
Started Sep 11 04:53:21 PM UTC 24
Finished Sep 11 04:56:46 PM UTC 24
Peak memory 252500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304743966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3304743966
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3901498100
Short name T203
Test name
Test status
Simulation time 137764769 ps
CPU time 7.76 seconds
Started Sep 11 04:53:20 PM UTC 24
Finished Sep 11 04:53:29 PM UTC 24
Peak memory 262676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901498100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3901498100
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1113692720
Short name T218
Test name
Test status
Simulation time 34044897 ps
CPU time 8.14 seconds
Started Sep 11 04:53:22 PM UTC 24
Finished Sep 11 04:53:32 PM UTC 24
Peak memory 252496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113692720 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_mem_
rw_with_rand_reset.1113692720
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_rw.1838992009
Short name T217
Test name
Test status
Simulation time 67192615 ps
CPU time 8.04 seconds
Started Sep 11 04:53:21 PM UTC 24
Finished Sep 11 04:53:30 PM UTC 24
Peak memory 250344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838992009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1838992009
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.419695924
Short name T225
Test name
Test status
Simulation time 186714918 ps
CPU time 31.76 seconds
Started Sep 11 04:53:21 PM UTC 24
Finished Sep 11 04:53:54 PM UTC 24
Peak memory 260624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419695924 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outstanding.419695924
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_errors.1141022848
Short name T268
Test name
Test status
Simulation time 164042569 ps
CPU time 6.88 seconds
Started Sep 11 04:53:20 PM UTC 24
Finished Sep 11 04:53:28 PM UTC 24
Peak memory 262884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141022848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1141022848
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3980332500
Short name T234
Test name
Test status
Simulation time 2146591774 ps
CPU time 87.05 seconds
Started Sep 11 04:53:34 PM UTC 24
Finished Sep 11 04:55:03 PM UTC 24
Peak memory 250316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980332500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3980332500
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2057393466
Short name T741
Test name
Test status
Simulation time 13631699909 ps
CPU time 244.52 seconds
Started Sep 11 04:53:34 PM UTC 24
Finished Sep 11 04:57:42 PM UTC 24
Peak memory 250452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057393466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2057393466
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2661514094
Short name T238
Test name
Test status
Simulation time 333393304 ps
CPU time 6.25 seconds
Started Sep 11 04:53:31 PM UTC 24
Finished Sep 11 04:53:38 PM UTC 24
Peak memory 252364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661514094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2661514094
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.619812006
Short name T390
Test name
Test status
Simulation time 34266666 ps
CPU time 7.42 seconds
Started Sep 11 04:53:39 PM UTC 24
Finished Sep 11 04:53:48 PM UTC 24
Peak memory 252252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619812006 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_mem_r
w_with_rand_reset.619812006
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_rw.2626815116
Short name T237
Test name
Test status
Simulation time 120100805 ps
CPU time 5 seconds
Started Sep 11 04:53:32 PM UTC 24
Finished Sep 11 04:53:38 PM UTC 24
Peak memory 250320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626815116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2626815116
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_intr_test.3141631756
Short name T204
Test name
Test status
Simulation time 12306775 ps
CPU time 2.33 seconds
Started Sep 11 04:53:30 PM UTC 24
Finished Sep 11 04:53:33 PM UTC 24
Peak memory 250468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141631756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3141631756
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1832483654
Short name T233
Test name
Test status
Simulation time 635903295 ps
CPU time 65.95 seconds
Started Sep 11 04:53:39 PM UTC 24
Finished Sep 11 04:54:47 PM UTC 24
Peak memory 260324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832483654 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outstanding.1832483654
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2811702105
Short name T196
Test name
Test status
Simulation time 135468670351 ps
CPU time 1058.95 seconds
Started Sep 11 04:53:22 PM UTC 24
Finished Sep 11 05:11:14 PM UTC 24
Peak memory 279448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811702105 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shado
w_reg_errors_with_csr_rw.2811702105
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_errors.1154455126
Short name T267
Test name
Test status
Simulation time 426722603 ps
CPU time 7.51 seconds
Started Sep 11 04:53:25 PM UTC 24
Finished Sep 11 04:53:33 PM UTC 24
Peak memory 264868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154455126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1154455126
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3091067314
Short name T742
Test name
Test status
Simulation time 386401118 ps
CPU time 11.71 seconds
Started Sep 11 04:57:35 PM UTC 24
Finished Sep 11 04:57:48 PM UTC 24
Peak memory 252628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091067314 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_mem
_rw_with_rand_reset.3091067314
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_rw.4214830591
Short name T739
Test name
Test status
Simulation time 67144501 ps
CPU time 5.24 seconds
Started Sep 11 04:57:34 PM UTC 24
Finished Sep 11 04:57:40 PM UTC 24
Peak memory 252504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214830591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.4214830591
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/10.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_intr_test.504734837
Short name T737
Test name
Test status
Simulation time 9418892 ps
CPU time 2.08 seconds
Started Sep 11 04:57:30 PM UTC 24
Finished Sep 11 04:57:33 PM UTC 24
Peak memory 250400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504734837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.504734837
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/10.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1299414833
Short name T747
Test name
Test status
Simulation time 448894298 ps
CPU time 31.82 seconds
Started Sep 11 04:57:34 PM UTC 24
Finished Sep 11 04:58:07 PM UTC 24
Peak memory 260696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299414833 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_outstanding.1299414833
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/10.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1391390885
Short name T824
Test name
Test status
Simulation time 17023864588 ps
CPU time 1134.17 seconds
Started Sep 11 04:57:23 PM UTC 24
Finished Sep 11 05:16:31 PM UTC 24
Peak memory 279448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391390885 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shad
ow_reg_errors_with_csr_rw.1391390885
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_errors.4073599751
Short name T738
Test name
Test status
Simulation time 471135317 ps
CPU time 6.14 seconds
Started Sep 11 04:57:26 PM UTC 24
Finished Sep 11 04:57:34 PM UTC 24
Peak memory 268964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073599751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.4073599751
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/10.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.779394313
Short name T748
Test name
Test status
Simulation time 595049730 ps
CPU time 17.18 seconds
Started Sep 11 04:57:51 PM UTC 24
Finished Sep 11 04:58:09 PM UTC 24
Peak memory 264852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779394313 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_mem_
rw_with_rand_reset.779394313
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_rw.1639851174
Short name T746
Test name
Test status
Simulation time 83337066 ps
CPU time 8.54 seconds
Started Sep 11 04:57:49 PM UTC 24
Finished Sep 11 04:57:58 PM UTC 24
Peak memory 252368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639851174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1639851174
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/11.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_intr_test.345355674
Short name T744
Test name
Test status
Simulation time 21072477 ps
CPU time 2.62 seconds
Started Sep 11 04:57:49 PM UTC 24
Finished Sep 11 04:57:52 PM UTC 24
Peak memory 250324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345355674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.345355674
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/11.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1130086651
Short name T749
Test name
Test status
Simulation time 333260674 ps
CPU time 21.12 seconds
Started Sep 11 04:57:50 PM UTC 24
Finished Sep 11 04:58:12 PM UTC 24
Peak memory 260620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130086651 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_outstanding.1130086651
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/11.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.610392741
Short name T393
Test name
Test status
Simulation time 68693183011 ps
CPU time 1228.02 seconds
Started Sep 11 04:57:41 PM UTC 24
Finished Sep 11 05:18:24 PM UTC 24
Peak memory 279448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610392741 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shado
w_reg_errors_with_csr_rw.610392741
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_errors.2965176722
Short name T743
Test name
Test status
Simulation time 50646638 ps
CPU time 6.19 seconds
Started Sep 11 04:57:42 PM UTC 24
Finished Sep 11 04:57:49 PM UTC 24
Peak memory 262884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965176722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2965176722
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/11.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.687059093
Short name T753
Test name
Test status
Simulation time 89788459 ps
CPU time 7.74 seconds
Started Sep 11 04:58:18 PM UTC 24
Finished Sep 11 04:58:27 PM UTC 24
Peak memory 252492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687059093 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_mem_
rw_with_rand_reset.687059093
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_rw.378506066
Short name T752
Test name
Test status
Simulation time 65448912 ps
CPU time 7.87 seconds
Started Sep 11 04:58:13 PM UTC 24
Finished Sep 11 04:58:22 PM UTC 24
Peak memory 252368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378506066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.378506066
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/12.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_intr_test.3052939865
Short name T750
Test name
Test status
Simulation time 13805132 ps
CPU time 1.53 seconds
Started Sep 11 04:58:11 PM UTC 24
Finished Sep 11 04:58:14 PM UTC 24
Peak memory 248772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052939865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3052939865
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/12.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.705254693
Short name T757
Test name
Test status
Simulation time 175107867 ps
CPU time 22.74 seconds
Started Sep 11 04:58:15 PM UTC 24
Finished Sep 11 04:58:39 PM UTC 24
Peak memory 260760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705254693 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_outstanding.705254693
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/12.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2515367570
Short name T177
Test name
Test status
Simulation time 8890504518 ps
CPU time 208.34 seconds
Started Sep 11 04:57:54 PM UTC 24
Finished Sep 11 05:01:26 PM UTC 24
Peak memory 279452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515367570 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors.2515367570
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.379675448
Short name T184
Test name
Test status
Simulation time 29351475862 ps
CPU time 473.63 seconds
Started Sep 11 04:57:53 PM UTC 24
Finished Sep 11 05:05:53 PM UTC 24
Peak memory 279452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379675448 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shado
w_reg_errors_with_csr_rw.379675448
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_errors.1630386794
Short name T751
Test name
Test status
Simulation time 379461310 ps
CPU time 16.46 seconds
Started Sep 11 04:57:59 PM UTC 24
Finished Sep 11 04:58:17 PM UTC 24
Peak memory 262936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630386794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1630386794
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/12.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1862443543
Short name T760
Test name
Test status
Simulation time 631373907 ps
CPU time 9.88 seconds
Started Sep 11 04:58:39 PM UTC 24
Finished Sep 11 04:58:50 PM UTC 24
Peak memory 254540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862443543 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_mem
_rw_with_rand_reset.1862443543
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_rw.3535675740
Short name T759
Test name
Test status
Simulation time 19489297 ps
CPU time 3.58 seconds
Started Sep 11 04:58:36 PM UTC 24
Finished Sep 11 04:58:40 PM UTC 24
Peak memory 250456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535675740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3535675740
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/13.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_intr_test.796842457
Short name T756
Test name
Test status
Simulation time 10874845 ps
CPU time 2.39 seconds
Started Sep 11 04:58:34 PM UTC 24
Finished Sep 11 04:58:38 PM UTC 24
Peak memory 250464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796842457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.796842457
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/13.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2804933979
Short name T764
Test name
Test status
Simulation time 368871453 ps
CPU time 28.91 seconds
Started Sep 11 04:58:38 PM UTC 24
Finished Sep 11 04:59:08 PM UTC 24
Peak memory 260632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804933979 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_outstanding.2804933979
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/13.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1408822943
Short name T166
Test name
Test status
Simulation time 3112511972 ps
CPU time 114.08 seconds
Started Sep 11 04:58:25 PM UTC 24
Finished Sep 11 05:00:22 PM UTC 24
Peak memory 279584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408822943 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_errors.1408822943
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3685784282
Short name T195
Test name
Test status
Simulation time 32981537498 ps
CPU time 531.61 seconds
Started Sep 11 04:58:23 PM UTC 24
Finished Sep 11 05:07:22 PM UTC 24
Peak memory 279584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685784282 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shad
ow_reg_errors_with_csr_rw.3685784282
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_errors.1638120603
Short name T758
Test name
Test status
Simulation time 432667267 ps
CPU time 10.41 seconds
Started Sep 11 04:58:28 PM UTC 24
Finished Sep 11 04:58:40 PM UTC 24
Peak memory 262808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638120603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1638120603
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/13.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3847097355
Short name T754
Test name
Test status
Simulation time 35873313 ps
CPU time 2.85 seconds
Started Sep 11 04:58:29 PM UTC 24
Finished Sep 11 04:58:33 PM UTC 24
Peak memory 250380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847097355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3847097355
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/13.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2446956006
Short name T769
Test name
Test status
Simulation time 98024337 ps
CPU time 11.1 seconds
Started Sep 11 04:59:08 PM UTC 24
Finished Sep 11 04:59:20 PM UTC 24
Peak memory 252492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446956006 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_mem
_rw_with_rand_reset.2446956006
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_rw.2888948173
Short name T763
Test name
Test status
Simulation time 620782000 ps
CPU time 13.97 seconds
Started Sep 11 04:58:53 PM UTC 24
Finished Sep 11 04:59:08 PM UTC 24
Peak memory 250392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888948173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2888948173
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/14.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_intr_test.3181514189
Short name T762
Test name
Test status
Simulation time 13734025 ps
CPU time 1.55 seconds
Started Sep 11 04:58:53 PM UTC 24
Finished Sep 11 04:58:55 PM UTC 24
Peak memory 248840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181514189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3181514189
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/14.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.975419265
Short name T765
Test name
Test status
Simulation time 318136079 ps
CPU time 16.66 seconds
Started Sep 11 04:58:56 PM UTC 24
Finished Sep 11 04:59:14 PM UTC 24
Peak memory 260620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975419265 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_outstanding.975419265
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/14.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2493485664
Short name T186
Test name
Test status
Simulation time 7819132099 ps
CPU time 420.79 seconds
Started Sep 11 04:58:41 PM UTC 24
Finished Sep 11 05:05:48 PM UTC 24
Peak memory 279448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493485664 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_errors.2493485664
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_errors.2005782769
Short name T761
Test name
Test status
Simulation time 105247858 ps
CPU time 9.42 seconds
Started Sep 11 04:58:41 PM UTC 24
Finished Sep 11 04:58:52 PM UTC 24
Peak memory 266844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005782769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2005782769
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/14.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.4068208364
Short name T771
Test name
Test status
Simulation time 112342301 ps
CPU time 12.18 seconds
Started Sep 11 04:59:19 PM UTC 24
Finished Sep 11 04:59:32 PM UTC 24
Peak memory 266900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068208364 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_mem
_rw_with_rand_reset.4068208364
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_rw.714821299
Short name T770
Test name
Test status
Simulation time 67109864 ps
CPU time 7.97 seconds
Started Sep 11 04:59:16 PM UTC 24
Finished Sep 11 04:59:25 PM UTC 24
Peak memory 250316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714821299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.714821299
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/15.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_intr_test.1112445969
Short name T768
Test name
Test status
Simulation time 7740433 ps
CPU time 2.06 seconds
Started Sep 11 04:59:14 PM UTC 24
Finished Sep 11 04:59:17 PM UTC 24
Peak memory 250468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112445969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1112445969
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/15.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1018671938
Short name T776
Test name
Test status
Simulation time 354815287 ps
CPU time 33.95 seconds
Started Sep 11 04:59:18 PM UTC 24
Finished Sep 11 04:59:53 PM UTC 24
Peak memory 260696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018671938 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_outstanding.1018671938
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/15.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3825942193
Short name T392
Test name
Test status
Simulation time 30628817224 ps
CPU time 598.13 seconds
Started Sep 11 04:59:09 PM UTC 24
Finished Sep 11 05:09:15 PM UTC 24
Peak memory 279584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825942193 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shad
ow_reg_errors_with_csr_rw.3825942193
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_errors.3286718026
Short name T767
Test name
Test status
Simulation time 113583583 ps
CPU time 6.62 seconds
Started Sep 11 04:59:09 PM UTC 24
Finished Sep 11 04:59:17 PM UTC 24
Peak memory 262736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286718026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3286718026
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/15.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_intg_err.6642228
Short name T766
Test name
Test status
Simulation time 54154202 ps
CPU time 5.48 seconds
Started Sep 11 04:59:09 PM UTC 24
Finished Sep 11 04:59:16 PM UTC 24
Peak memory 250380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6642228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.6642228
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/15.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3913393308
Short name T775
Test name
Test status
Simulation time 186972590 ps
CPU time 11.92 seconds
Started Sep 11 04:59:35 PM UTC 24
Finished Sep 11 04:59:48 PM UTC 24
Peak memory 252692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913393308 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_mem
_rw_with_rand_reset.3913393308
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_rw.3162271970
Short name T773
Test name
Test status
Simulation time 60644595 ps
CPU time 4.24 seconds
Started Sep 11 04:59:30 PM UTC 24
Finished Sep 11 04:59:36 PM UTC 24
Peak memory 252368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162271970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3162271970
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/16.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_intr_test.2026648494
Short name T772
Test name
Test status
Simulation time 11374168 ps
CPU time 2.58 seconds
Started Sep 11 04:59:30 PM UTC 24
Finished Sep 11 04:59:34 PM UTC 24
Peak memory 249904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026648494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2026648494
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/16.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2366544936
Short name T779
Test name
Test status
Simulation time 2091574131 ps
CPU time 24.43 seconds
Started Sep 11 04:59:33 PM UTC 24
Finished Sep 11 04:59:58 PM UTC 24
Peak memory 260824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366544936 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_outstanding.2366544936
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/16.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3565312003
Short name T171
Test name
Test status
Simulation time 2079703743 ps
CPU time 163.17 seconds
Started Sep 11 04:59:19 PM UTC 24
Finished Sep 11 05:02:05 PM UTC 24
Peak memory 281364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565312003 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_errors.3565312003
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_errors.3993754020
Short name T774
Test name
Test status
Simulation time 340094775 ps
CPU time 17.64 seconds
Started Sep 11 04:59:21 PM UTC 24
Finished Sep 11 04:59:40 PM UTC 24
Peak memory 262820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993754020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3993754020
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/16.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2312548492
Short name T782
Test name
Test status
Simulation time 308883757 ps
CPU time 9.66 seconds
Started Sep 11 04:59:54 PM UTC 24
Finished Sep 11 05:00:05 PM UTC 24
Peak memory 252492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312548492 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_mem
_rw_with_rand_reset.2312548492
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_rw.1845281195
Short name T780
Test name
Test status
Simulation time 149815240 ps
CPU time 8.35 seconds
Started Sep 11 04:59:53 PM UTC 24
Finished Sep 11 05:00:03 PM UTC 24
Peak memory 252368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845281195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1845281195
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/17.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_intr_test.2130410134
Short name T778
Test name
Test status
Simulation time 10148607 ps
CPU time 2.5 seconds
Started Sep 11 04:59:51 PM UTC 24
Finished Sep 11 04:59:55 PM UTC 24
Peak memory 250332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130410134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2130410134
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/17.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1106047152
Short name T788
Test name
Test status
Simulation time 2753625829 ps
CPU time 38.12 seconds
Started Sep 11 04:59:54 PM UTC 24
Finished Sep 11 05:00:34 PM UTC 24
Peak memory 262736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106047152 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_outstanding.1106047152
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/17.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_errors.2408742302
Short name T777
Test name
Test status
Simulation time 219601317 ps
CPU time 9.71 seconds
Started Sep 11 04:59:43 PM UTC 24
Finished Sep 11 04:59:54 PM UTC 24
Peak memory 266980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408742302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2408742302
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/17.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.370218046
Short name T786
Test name
Test status
Simulation time 663488316 ps
CPU time 16.63 seconds
Started Sep 11 05:00:10 PM UTC 24
Finished Sep 11 05:00:27 PM UTC 24
Peak memory 254540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370218046 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_mem_
rw_with_rand_reset.370218046
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.563535737
Short name T785
Test name
Test status
Simulation time 652667690 ps
CPU time 14.35 seconds
Started Sep 11 05:00:06 PM UTC 24
Finished Sep 11 05:00:22 PM UTC 24
Peak memory 250316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563535737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.563535737
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/18.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.3693787216
Short name T784
Test name
Test status
Simulation time 11470862 ps
CPU time 2.24 seconds
Started Sep 11 05:00:06 PM UTC 24
Finished Sep 11 05:00:10 PM UTC 24
Peak memory 250468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693787216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3693787216
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/18.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2446086080
Short name T791
Test name
Test status
Simulation time 1628578208 ps
CPU time 29.34 seconds
Started Sep 11 05:00:06 PM UTC 24
Finished Sep 11 05:00:37 PM UTC 24
Peak memory 260620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446086080 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_outstanding.2446086080
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/18.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2354056668
Short name T183
Test name
Test status
Simulation time 7542073281 ps
CPU time 212.91 seconds
Started Sep 11 04:59:57 PM UTC 24
Finished Sep 11 05:03:33 PM UTC 24
Peak memory 279444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354056668 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors.2354056668
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2176068635
Short name T192
Test name
Test status
Simulation time 10077127417 ps
CPU time 548.58 seconds
Started Sep 11 04:59:56 PM UTC 24
Finished Sep 11 05:09:12 PM UTC 24
Peak memory 279520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176068635 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shad
ow_reg_errors_with_csr_rw.2176068635
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.692384505
Short name T783
Test name
Test status
Simulation time 58846944 ps
CPU time 8.94 seconds
Started Sep 11 04:59:59 PM UTC 24
Finished Sep 11 05:00:09 PM UTC 24
Peak memory 268888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692384505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.692384505
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/18.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.68054426
Short name T799
Test name
Test status
Simulation time 570065847 ps
CPU time 7.85 seconds
Started Sep 11 05:00:35 PM UTC 24
Finished Sep 11 05:00:45 PM UTC 24
Peak memory 268880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68054426 -assert nop
ostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_mem_r
w_with_rand_reset.68054426
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.830483961
Short name T794
Test name
Test status
Simulation time 115647526 ps
CPU time 7.67 seconds
Started Sep 11 05:00:32 PM UTC 24
Finished Sep 11 05:00:41 PM UTC 24
Peak memory 250316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830483961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.830483961
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/19.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.3214636332
Short name T787
Test name
Test status
Simulation time 11157346 ps
CPU time 2.49 seconds
Started Sep 11 05:00:28 PM UTC 24
Finished Sep 11 05:00:32 PM UTC 24
Peak memory 250328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214636332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3214636332
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/19.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.859112599
Short name T823
Test name
Test status
Simulation time 751969011 ps
CPU time 32.84 seconds
Started Sep 11 05:00:33 PM UTC 24
Finished Sep 11 05:01:08 PM UTC 24
Peak memory 260628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859112599 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_outstanding.859112599
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/19.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.4027334555
Short name T188
Test name
Test status
Simulation time 4538212681 ps
CPU time 677.85 seconds
Started Sep 11 05:00:11 PM UTC 24
Finished Sep 11 05:11:38 PM UTC 24
Peak memory 279444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027334555 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shad
ow_reg_errors_with_csr_rw.4027334555
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.3817191174
Short name T789
Test name
Test status
Simulation time 52808760 ps
CPU time 10.58 seconds
Started Sep 11 05:00:23 PM UTC 24
Finished Sep 11 05:00:35 PM UTC 24
Peak memory 262744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817191174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3817191174
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/19.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1165686640
Short name T736
Test name
Test status
Simulation time 4219247540 ps
CPU time 192.2 seconds
Started Sep 11 04:54:13 PM UTC 24
Finished Sep 11 04:57:29 PM UTC 24
Peak memory 250444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165686640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1165686640
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3963549245
Short name T755
Test name
Test status
Simulation time 1706653904 ps
CPU time 256.41 seconds
Started Sep 11 04:54:13 PM UTC 24
Finished Sep 11 04:58:34 PM UTC 24
Peak memory 252364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963549245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3963549245
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3783969684
Short name T240
Test name
Test status
Simulation time 287880233 ps
CPU time 12.34 seconds
Started Sep 11 04:54:02 PM UTC 24
Finished Sep 11 04:54:16 PM UTC 24
Peak memory 262740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783969684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3783969684
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1791326052
Short name T265
Test name
Test status
Simulation time 77572734 ps
CPU time 8.23 seconds
Started Sep 11 04:54:17 PM UTC 24
Finished Sep 11 04:54:26 PM UTC 24
Peak memory 252496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791326052 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_mem_
rw_with_rand_reset.1791326052
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_rw.2606744290
Short name T239
Test name
Test status
Simulation time 68279682 ps
CPU time 5.21 seconds
Started Sep 11 04:54:06 PM UTC 24
Finished Sep 11 04:54:13 PM UTC 24
Peak memory 250316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606744290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2606744290
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2424839247
Short name T227
Test name
Test status
Simulation time 512671242 ps
CPU time 35.48 seconds
Started Sep 11 04:54:17 PM UTC 24
Finished Sep 11 04:54:53 PM UTC 24
Peak memory 260620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424839247 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outstanding.2424839247
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2993084083
Short name T162
Test name
Test status
Simulation time 4019104265 ps
CPU time 141.14 seconds
Started Sep 11 04:53:51 PM UTC 24
Finished Sep 11 04:56:14 PM UTC 24
Peak memory 281632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993084083 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors.2993084083
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_errors.2038224138
Short name T711
Test name
Test status
Simulation time 404292099 ps
CPU time 15.11 seconds
Started Sep 11 04:53:56 PM UTC 24
Finished Sep 11 04:54:12 PM UTC 24
Peak memory 266840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038224138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2038224138
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.3520999693
Short name T792
Test name
Test status
Simulation time 13894384 ps
CPU time 1.96 seconds
Started Sep 11 05:00:36 PM UTC 24
Finished Sep 11 05:00:39 PM UTC 24
Peak memory 246788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520999693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3520999693
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/20.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.949349886
Short name T790
Test name
Test status
Simulation time 10231438 ps
CPU time 2.44 seconds
Started Sep 11 05:00:37 PM UTC 24
Finished Sep 11 05:00:40 PM UTC 24
Peak memory 250464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949349886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.949349886
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/21.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.3697584501
Short name T793
Test name
Test status
Simulation time 14869826 ps
CPU time 1.87 seconds
Started Sep 11 05:00:38 PM UTC 24
Finished Sep 11 05:00:41 PM UTC 24
Peak memory 248836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697584501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3697584501
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/22.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.1462229980
Short name T795
Test name
Test status
Simulation time 33016229 ps
CPU time 2.15 seconds
Started Sep 11 05:00:40 PM UTC 24
Finished Sep 11 05:00:43 PM UTC 24
Peak memory 250332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462229980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1462229980
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/23.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.4117011982
Short name T796
Test name
Test status
Simulation time 15629692 ps
CPU time 2.37 seconds
Started Sep 11 05:00:40 PM UTC 24
Finished Sep 11 05:00:43 PM UTC 24
Peak memory 250328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117011982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.4117011982
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/24.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.1811625099
Short name T797
Test name
Test status
Simulation time 8246073 ps
CPU time 2.16 seconds
Started Sep 11 05:00:41 PM UTC 24
Finished Sep 11 05:00:44 PM UTC 24
Peak memory 248280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811625099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1811625099
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/25.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.276188864
Short name T798
Test name
Test status
Simulation time 10053055 ps
CPU time 2.43 seconds
Started Sep 11 05:00:41 PM UTC 24
Finished Sep 11 05:00:44 PM UTC 24
Peak memory 250464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276188864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.276188864
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/26.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.1090937113
Short name T800
Test name
Test status
Simulation time 27411974 ps
CPU time 2.3 seconds
Started Sep 11 05:00:42 PM UTC 24
Finished Sep 11 05:00:46 PM UTC 24
Peak memory 250468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090937113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1090937113
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/27.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.2650443984
Short name T801
Test name
Test status
Simulation time 6607417 ps
CPU time 1.84 seconds
Started Sep 11 05:00:44 PM UTC 24
Finished Sep 11 05:00:47 PM UTC 24
Peak memory 248828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650443984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2650443984
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/28.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.1622432456
Short name T802
Test name
Test status
Simulation time 14128230 ps
CPU time 2.06 seconds
Started Sep 11 05:00:44 PM UTC 24
Finished Sep 11 05:00:48 PM UTC 24
Peak memory 250468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622432456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1622432456
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/29.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2105075943
Short name T235
Test name
Test status
Simulation time 2942031724 ps
CPU time 76.91 seconds
Started Sep 11 04:54:57 PM UTC 24
Finished Sep 11 04:56:16 PM UTC 24
Peak memory 252492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105075943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2105075943
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3403844319
Short name T781
Test name
Test status
Simulation time 5947618898 ps
CPU time 305.29 seconds
Started Sep 11 04:54:55 PM UTC 24
Finished Sep 11 05:00:04 PM UTC 24
Peak memory 250644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403844319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3403844319
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.4243451879
Short name T264
Test name
Test status
Simulation time 488549049 ps
CPU time 14.94 seconds
Started Sep 11 04:54:46 PM UTC 24
Finished Sep 11 04:55:03 PM UTC 24
Peak memory 262676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243451879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.4243451879
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1989773482
Short name T391
Test name
Test status
Simulation time 83523583 ps
CPU time 10.56 seconds
Started Sep 11 04:55:00 PM UTC 24
Finished Sep 11 04:55:12 PM UTC 24
Peak memory 262808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989773482 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_mem_
rw_with_rand_reset.1989773482
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_rw.3195130127
Short name T228
Test name
Test status
Simulation time 296671428 ps
CPU time 7.77 seconds
Started Sep 11 04:54:48 PM UTC 24
Finished Sep 11 04:54:56 PM UTC 24
Peak memory 252504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195130127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3195130127
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3572557600
Short name T229
Test name
Test status
Simulation time 536510719 ps
CPU time 22.48 seconds
Started Sep 11 04:54:57 PM UTC 24
Finished Sep 11 04:55:21 PM UTC 24
Peak memory 262744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572557600 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outstanding.3572557600
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2565032059
Short name T180
Test name
Test status
Simulation time 25863415395 ps
CPU time 483.03 seconds
Started Sep 11 04:54:23 PM UTC 24
Finished Sep 11 05:02:33 PM UTC 24
Peak memory 279444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565032059 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shado
w_reg_errors_with_csr_rw.2565032059
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_errors.4238441029
Short name T712
Test name
Test status
Simulation time 164722090 ps
CPU time 17.95 seconds
Started Sep 11 04:54:37 PM UTC 24
Finished Sep 11 04:54:56 PM UTC 24
Peak memory 262748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238441029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.4238441029
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.83875527
Short name T803
Test name
Test status
Simulation time 19294513 ps
CPU time 2.16 seconds
Started Sep 11 05:00:46 PM UTC 24
Finished Sep 11 05:00:49 PM UTC 24
Peak memory 250332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83875527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handle
r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.83875527
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/30.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.2584690305
Short name T804
Test name
Test status
Simulation time 15335514 ps
CPU time 2.11 seconds
Started Sep 11 05:00:46 PM UTC 24
Finished Sep 11 05:00:49 PM UTC 24
Peak memory 250392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584690305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2584690305
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/31.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.174504370
Short name T805
Test name
Test status
Simulation time 10612401 ps
CPU time 2.5 seconds
Started Sep 11 05:00:46 PM UTC 24
Finished Sep 11 05:00:49 PM UTC 24
Peak memory 250324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174504370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.174504370
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/32.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.2858323302
Short name T807
Test name
Test status
Simulation time 10933924 ps
CPU time 2.24 seconds
Started Sep 11 05:00:47 PM UTC 24
Finished Sep 11 05:00:50 PM UTC 24
Peak memory 250328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858323302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2858323302
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/33.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.4221662521
Short name T806
Test name
Test status
Simulation time 22189091 ps
CPU time 1.92 seconds
Started Sep 11 05:00:47 PM UTC 24
Finished Sep 11 05:00:50 PM UTC 24
Peak memory 248840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221662521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.4221662521
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/34.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.748568128
Short name T809
Test name
Test status
Simulation time 27951237 ps
CPU time 2.23 seconds
Started Sep 11 05:00:48 PM UTC 24
Finished Sep 11 05:00:51 PM UTC 24
Peak memory 250464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748568128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.748568128
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/35.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.1224720210
Short name T808
Test name
Test status
Simulation time 25177215 ps
CPU time 2.07 seconds
Started Sep 11 05:00:48 PM UTC 24
Finished Sep 11 05:00:51 PM UTC 24
Peak memory 250468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224720210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1224720210
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/36.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.1406431304
Short name T810
Test name
Test status
Simulation time 7866089 ps
CPU time 2.11 seconds
Started Sep 11 05:00:50 PM UTC 24
Finished Sep 11 05:00:53 PM UTC 24
Peak memory 250128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406431304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1406431304
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/37.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.476449779
Short name T811
Test name
Test status
Simulation time 20950721 ps
CPU time 2.18 seconds
Started Sep 11 05:00:50 PM UTC 24
Finished Sep 11 05:00:53 PM UTC 24
Peak memory 250012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476449779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.476449779
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/38.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.1268284525
Short name T813
Test name
Test status
Simulation time 9387019 ps
CPU time 2.4 seconds
Started Sep 11 05:00:50 PM UTC 24
Finished Sep 11 05:00:54 PM UTC 24
Peak memory 248280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268284525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1268284525
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/39.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_aliasing.4079307595
Short name T733
Test name
Test status
Simulation time 6495193295 ps
CPU time 119.58 seconds
Started Sep 11 04:55:21 PM UTC 24
Finished Sep 11 04:57:24 PM UTC 24
Peak memory 252564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079307595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.4079307595
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2155147294
Short name T745
Test name
Test status
Simulation time 6807657544 ps
CPU time 150.78 seconds
Started Sep 11 04:55:19 PM UTC 24
Finished Sep 11 04:57:53 PM UTC 24
Peak memory 250452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155147294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2155147294
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2864027531
Short name T231
Test name
Test status
Simulation time 433391051 ps
CPU time 13.63 seconds
Started Sep 11 04:55:17 PM UTC 24
Finished Sep 11 04:55:32 PM UTC 24
Peak memory 262740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864027531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2864027531
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1010356353
Short name T394
Test name
Test status
Simulation time 57689494 ps
CPU time 7.49 seconds
Started Sep 11 04:55:24 PM UTC 24
Finished Sep 11 04:55:33 PM UTC 24
Peak memory 268880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010356353 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_mem_
rw_with_rand_reset.1010356353
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_rw.1582005580
Short name T230
Test name
Test status
Simulation time 447632386 ps
CPU time 11.93 seconds
Started Sep 11 04:55:17 PM UTC 24
Finished Sep 11 04:55:30 PM UTC 24
Peak memory 252368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582005580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1582005580
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_intr_test.519460416
Short name T388
Test name
Test status
Simulation time 9105627 ps
CPU time 1.95 seconds
Started Sep 11 04:55:13 PM UTC 24
Finished Sep 11 04:55:16 PM UTC 24
Peak memory 248836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519460416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.519460416
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3813723104
Short name T232
Test name
Test status
Simulation time 8273239164 ps
CPU time 51.02 seconds
Started Sep 11 04:55:22 PM UTC 24
Finished Sep 11 04:56:16 PM UTC 24
Peak memory 260888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813723104 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outstanding.3813723104
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3649624228
Short name T194
Test name
Test status
Simulation time 52606024296 ps
CPU time 932.8 seconds
Started Sep 11 04:55:01 PM UTC 24
Finished Sep 11 05:10:45 PM UTC 24
Peak memory 279444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649624228 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shado
w_reg_errors_with_csr_rw.3649624228
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_errors.2989774555
Short name T266
Test name
Test status
Simulation time 230625208 ps
CPU time 18.39 seconds
Started Sep 11 04:55:03 PM UTC 24
Finished Sep 11 04:55:23 PM UTC 24
Peak memory 262944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989774555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2989774555
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.1420181088
Short name T812
Test name
Test status
Simulation time 7975490 ps
CPU time 2.15 seconds
Started Sep 11 05:00:50 PM UTC 24
Finished Sep 11 05:00:54 PM UTC 24
Peak memory 250320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420181088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.1420181088
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/40.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.692381556
Short name T815
Test name
Test status
Simulation time 10278733 ps
CPU time 2.06 seconds
Started Sep 11 05:00:51 PM UTC 24
Finished Sep 11 05:00:55 PM UTC 24
Peak memory 250208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692381556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.692381556
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/41.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.3828536779
Short name T814
Test name
Test status
Simulation time 7618591 ps
CPU time 2.08 seconds
Started Sep 11 05:00:52 PM UTC 24
Finished Sep 11 05:00:55 PM UTC 24
Peak memory 250288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828536779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3828536779
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/42.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.2374961418
Short name T816
Test name
Test status
Simulation time 7393274 ps
CPU time 2.1 seconds
Started Sep 11 05:00:52 PM UTC 24
Finished Sep 11 05:00:55 PM UTC 24
Peak memory 250468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374961418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2374961418
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/43.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.190300875
Short name T820
Test name
Test status
Simulation time 11371844 ps
CPU time 2.21 seconds
Started Sep 11 05:00:55 PM UTC 24
Finished Sep 11 05:00:58 PM UTC 24
Peak memory 250528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190300875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.190300875
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/44.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.1705377347
Short name T818
Test name
Test status
Simulation time 7847990 ps
CPU time 2.22 seconds
Started Sep 11 05:00:55 PM UTC 24
Finished Sep 11 05:00:58 PM UTC 24
Peak memory 250328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705377347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1705377347
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/45.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.2069230292
Short name T819
Test name
Test status
Simulation time 6285099 ps
CPU time 2.16 seconds
Started Sep 11 05:00:55 PM UTC 24
Finished Sep 11 05:00:58 PM UTC 24
Peak memory 250328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069230292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2069230292
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/46.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.3995055223
Short name T817
Test name
Test status
Simulation time 10424875 ps
CPU time 1.54 seconds
Started Sep 11 05:00:55 PM UTC 24
Finished Sep 11 05:00:58 PM UTC 24
Peak memory 246776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995055223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3995055223
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/47.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.244626760
Short name T821
Test name
Test status
Simulation time 17536305 ps
CPU time 2.09 seconds
Started Sep 11 05:00:56 PM UTC 24
Finished Sep 11 05:00:59 PM UTC 24
Peak memory 250400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244626760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.244626760
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/48.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.401414809
Short name T822
Test name
Test status
Simulation time 18796167 ps
CPU time 2.32 seconds
Started Sep 11 05:00:56 PM UTC 24
Finished Sep 11 05:00:59 PM UTC 24
Peak memory 248284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401414809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.401414809
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/49.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.297210179
Short name T715
Test name
Test status
Simulation time 603731134 ps
CPU time 15.36 seconds
Started Sep 11 04:56:01 PM UTC 24
Finished Sep 11 04:56:18 PM UTC 24
Peak memory 254544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297210179 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_mem_r
w_with_rand_reset.297210179
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_rw.3071720984
Short name T713
Test name
Test status
Simulation time 32328415 ps
CPU time 5.19 seconds
Started Sep 11 04:55:47 PM UTC 24
Finished Sep 11 04:55:53 PM UTC 24
Peak memory 250520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071720984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3071720984
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/5.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_intr_test.2033978530
Short name T389
Test name
Test status
Simulation time 17841225 ps
CPU time 2.17 seconds
Started Sep 11 04:55:43 PM UTC 24
Finished Sep 11 04:55:46 PM UTC 24
Peak memory 250404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033978530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2033978530
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/5.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3289710696
Short name T236
Test name
Test status
Simulation time 264127182 ps
CPU time 27.74 seconds
Started Sep 11 04:55:54 PM UTC 24
Finished Sep 11 04:56:23 PM UTC 24
Peak memory 260628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289710696 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outstanding.3289710696
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/5.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2760581351
Short name T165
Test name
Test status
Simulation time 2130255722 ps
CPU time 173.09 seconds
Started Sep 11 04:55:33 PM UTC 24
Finished Sep 11 04:58:29 PM UTC 24
Peak memory 279320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760581351 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors.2760581351
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1312455814
Short name T197
Test name
Test status
Simulation time 200475571436 ps
CPU time 842.98 seconds
Started Sep 11 04:55:32 PM UTC 24
Finished Sep 11 05:09:45 PM UTC 24
Peak memory 285728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312455814 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shado
w_reg_errors_with_csr_rw.1312455814
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_errors.2327508892
Short name T714
Test name
Test status
Simulation time 309204573 ps
CPU time 28.62 seconds
Started Sep 11 04:55:34 PM UTC 24
Finished Sep 11 04:56:04 PM UTC 24
Peak memory 262744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327508892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2327508892
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/5.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.182100155
Short name T717
Test name
Test status
Simulation time 161478057 ps
CPU time 13 seconds
Started Sep 11 04:56:22 PM UTC 24
Finished Sep 11 04:56:36 PM UTC 24
Peak memory 268956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182100155 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_mem_r
w_with_rand_reset.182100155
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_rw.801294922
Short name T716
Test name
Test status
Simulation time 184979084 ps
CPU time 6.95 seconds
Started Sep 11 04:56:19 PM UTC 24
Finished Sep 11 04:56:27 PM UTC 24
Peak memory 250392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801294922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.801294922
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/6.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_intr_test.595466139
Short name T386
Test name
Test status
Simulation time 10969013 ps
CPU time 2.12 seconds
Started Sep 11 04:56:17 PM UTC 24
Finished Sep 11 04:56:20 PM UTC 24
Peak memory 250468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595466139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.595466139
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/6.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1799032298
Short name T718
Test name
Test status
Simulation time 90645586 ps
CPU time 14.82 seconds
Started Sep 11 04:56:21 PM UTC 24
Finished Sep 11 04:56:37 PM UTC 24
Peak memory 252432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799032298 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outstanding.1799032298
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/6.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.7536994
Short name T168
Test name
Test status
Simulation time 2220310230 ps
CPU time 156.76 seconds
Started Sep 11 04:56:12 PM UTC 24
Finished Sep 11 04:58:51 PM UTC 24
Peak memory 279376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7536994 -assert nopostproc +UVM_TESTNAME=alert_handler_bas
e_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors.7536994
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.844890244
Short name T187
Test name
Test status
Simulation time 110037812056 ps
CPU time 496.13 seconds
Started Sep 11 04:56:04 PM UTC 24
Finished Sep 11 05:04:27 PM UTC 24
Peak memory 281504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844890244 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow
_reg_errors_with_csr_rw.844890244
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_errors.3292598962
Short name T721
Test name
Test status
Simulation time 291457114 ps
CPU time 27.93 seconds
Started Sep 11 04:56:16 PM UTC 24
Finished Sep 11 04:56:45 PM UTC 24
Peak memory 268888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292598962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3292598962
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/6.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1337516304
Short name T725
Test name
Test status
Simulation time 65828561 ps
CPU time 11.89 seconds
Started Sep 11 04:56:43 PM UTC 24
Finished Sep 11 04:56:56 PM UTC 24
Peak memory 264784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337516304 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_mem_
rw_with_rand_reset.1337516304
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_rw.3333507704
Short name T723
Test name
Test status
Simulation time 20594612 ps
CPU time 5.11 seconds
Started Sep 11 04:56:41 PM UTC 24
Finished Sep 11 04:56:47 PM UTC 24
Peak memory 250320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333507704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3333507704
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/7.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_intr_test.2320260939
Short name T720
Test name
Test status
Simulation time 36642597 ps
CPU time 2.2 seconds
Started Sep 11 04:56:38 PM UTC 24
Finished Sep 11 04:56:41 PM UTC 24
Peak memory 250400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320260939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2320260939
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/7.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.758455059
Short name T728
Test name
Test status
Simulation time 600022471 ps
CPU time 19.02 seconds
Started Sep 11 04:56:42 PM UTC 24
Finished Sep 11 04:57:02 PM UTC 24
Peak memory 252432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758455059 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outstanding.758455059
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/7.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.622100407
Short name T178
Test name
Test status
Simulation time 3029481124 ps
CPU time 190.98 seconds
Started Sep 11 04:56:27 PM UTC 24
Finished Sep 11 04:59:41 PM UTC 24
Peak memory 279520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622100407 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors.622100407
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_errors.3299130387
Short name T719
Test name
Test status
Simulation time 160336907 ps
CPU time 8.57 seconds
Started Sep 11 04:56:31 PM UTC 24
Finished Sep 11 04:56:40 PM UTC 24
Peak memory 262744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299130387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3299130387
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/7.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1243855139
Short name T729
Test name
Test status
Simulation time 188996293 ps
CPU time 7.96 seconds
Started Sep 11 04:56:57 PM UTC 24
Finished Sep 11 04:57:06 PM UTC 24
Peak memory 252496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243855139 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_mem_
rw_with_rand_reset.1243855139
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_rw.3596225134
Short name T726
Test name
Test status
Simulation time 327270848 ps
CPU time 7.85 seconds
Started Sep 11 04:56:51 PM UTC 24
Finished Sep 11 04:57:00 PM UTC 24
Peak memory 252504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596225134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3596225134
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/8.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_intr_test.2734840269
Short name T724
Test name
Test status
Simulation time 9151101 ps
CPU time 2.35 seconds
Started Sep 11 04:56:49 PM UTC 24
Finished Sep 11 04:56:52 PM UTC 24
Peak memory 250468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734840269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2734840269
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/8.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2962812160
Short name T732
Test name
Test status
Simulation time 1079532460 ps
CPU time 27.61 seconds
Started Sep 11 04:56:53 PM UTC 24
Finished Sep 11 04:57:22 PM UTC 24
Peak memory 252432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962812160 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outstanding.2962812160
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/8.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1484009690
Short name T173
Test name
Test status
Simulation time 8747157688 ps
CPU time 96.72 seconds
Started Sep 11 04:56:45 PM UTC 24
Finished Sep 11 04:58:25 PM UTC 24
Peak memory 279584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484009690 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors.1484009690
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_errors.2754406493
Short name T727
Test name
Test status
Simulation time 290621287 ps
CPU time 13.16 seconds
Started Sep 11 04:56:47 PM UTC 24
Finished Sep 11 04:57:01 PM UTC 24
Peak memory 262744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754406493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2754406493
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/8.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3165065501
Short name T734
Test name
Test status
Simulation time 98496873 ps
CPU time 7.09 seconds
Started Sep 11 04:57:17 PM UTC 24
Finished Sep 11 04:57:25 PM UTC 24
Peak memory 252568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165065501 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_mem_
rw_with_rand_reset.3165065501
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_rw.2901465071
Short name T735
Test name
Test status
Simulation time 97700455 ps
CPU time 12 seconds
Started Sep 11 04:57:14 PM UTC 24
Finished Sep 11 04:57:27 PM UTC 24
Peak memory 252568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901465071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2901465071
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/9.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_intr_test.3994769076
Short name T731
Test name
Test status
Simulation time 11292698 ps
CPU time 1.99 seconds
Started Sep 11 04:57:13 PM UTC 24
Finished Sep 11 04:57:16 PM UTC 24
Peak memory 248840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994769076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3994769076
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/9.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3279971522
Short name T740
Test name
Test status
Simulation time 173678951 ps
CPU time 24.19 seconds
Started Sep 11 04:57:16 PM UTC 24
Finished Sep 11 04:57:41 PM UTC 24
Peak memory 260624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279971522 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outstanding.3279971522
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/9.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3597685322
Short name T174
Test name
Test status
Simulation time 16372328944 ps
CPU time 316.61 seconds
Started Sep 11 04:57:02 PM UTC 24
Finished Sep 11 05:02:24 PM UTC 24
Peak memory 279584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597685322 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_10/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors.3597685322
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_errors.3103432121
Short name T730
Test name
Test status
Simulation time 84953755 ps
CPU time 10.26 seconds
Started Sep 11 04:57:03 PM UTC 24
Finished Sep 11 04:57:15 PM UTC 24
Peak memory 262744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103432121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3103432121
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/9.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg.3576630723
Short name T327
Test name
Test status
Simulation time 28264315504 ps
CPU time 1464.75 seconds
Started Sep 11 01:56:32 PM UTC 24
Finished Sep 11 02:21:16 PM UTC 24
Peak memory 300152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576630723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3576630723
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_alerts.2253138144
Short name T9
Test name
Test status
Simulation time 488212088 ps
CPU time 25.89 seconds
Started Sep 11 01:56:30 PM UTC 24
Finished Sep 11 01:56:58 PM UTC 24
Peak memory 262960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253138144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2253138144
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_classes.1782214964
Short name T10
Test name
Test status
Simulation time 222808815 ps
CPU time 29.61 seconds
Started Sep 11 01:56:30 PM UTC 24
Finished Sep 11 01:57:01 PM UTC 24
Peak memory 262996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782214964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.1782214964
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all.3568338667
Short name T71
Test name
Test status
Simulation time 261531422071 ps
CPU time 3354.95 seconds
Started Sep 11 01:56:33 PM UTC 24
Finished Sep 11 02:53:04 PM UTC 24
Peak memory 304604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568338667 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_stress_all.3568338667
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy_stress.3290519020
Short name T5
Test name
Test status
Simulation time 165876452 ps
CPU time 14.67 seconds
Started Sep 11 01:57:05 PM UTC 24
Finished Sep 11 01:57:21 PM UTC 24
Peak memory 262968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290519020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3290519020
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_alert_accum.31963393
Short name T44
Test name
Test status
Simulation time 157636607 ps
CPU time 24.76 seconds
Started Sep 11 01:56:52 PM UTC 24
Finished Sep 11 01:57:18 PM UTC 24
Peak memory 269360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31963393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc
_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.31963393
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/1.alert_handler_ping_timeout.1658692340
Short name T15
Test name
Test status
Simulation time 16995841182 ps
CPU time 134.13 seconds
Started Sep 11 01:56:58 PM UTC 24
Finished Sep 11 01:59:15 PM UTC 24
Peak memory 263164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658692340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1658692340
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_alerts.4139633673
Short name T43
Test name
Test status
Simulation time 1726965722 ps
CPU time 32.01 seconds
Started Sep 11 01:56:43 PM UTC 24
Finished Sep 11 01:57:17 PM UTC 24
Peak memory 269360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139633673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.4139633673
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/1.alert_handler_sig_int_fail.2685195320
Short name T12
Test name
Test status
Simulation time 125183646 ps
CPU time 9.38 seconds
Started Sep 11 01:56:54 PM UTC 24
Finished Sep 11 01:57:04 PM UTC 24
Peak memory 263256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685195320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2685195320
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/1.alert_handler_smoke.951584284
Short name T11
Test name
Test status
Simulation time 589997293 ps
CPU time 33.93 seconds
Started Sep 11 01:56:40 PM UTC 24
Finished Sep 11 01:57:15 PM UTC 24
Peak memory 262896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951584284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.951584284
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/1.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/10.alert_handler_alert_accum_saturation.621955482
Short name T154
Test name
Test status
Simulation time 87621368 ps
CPU time 4.94 seconds
Started Sep 11 02:13:39 PM UTC 24
Finished Sep 11 02:13:45 PM UTC 24
Peak memory 263244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621955482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.621955482
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/10.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy.2150211073
Short name T135
Test name
Test status
Simulation time 136164387208 ps
CPU time 1399.84 seconds
Started Sep 11 02:12:36 PM UTC 24
Finished Sep 11 02:36:13 PM UTC 24
Peak memory 302200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150211073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2150211073
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/10.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy_stress.1067699317
Short name T153
Test name
Test status
Simulation time 171196606 ps
CPU time 14.98 seconds
Started Sep 11 02:12:59 PM UTC 24
Finished Sep 11 02:13:15 PM UTC 24
Peak memory 262976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067699317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1067699317
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/10.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_alert_accum.3276927143
Short name T156
Test name
Test status
Simulation time 3316300497 ps
CPU time 147.52 seconds
Started Sep 11 02:12:12 PM UTC 24
Finished Sep 11 02:14:42 PM UTC 24
Peak memory 269172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276927143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3276927143
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/10.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_intr_timeout.1953818608
Short name T98
Test name
Test status
Simulation time 1815705625 ps
CPU time 25.17 seconds
Started Sep 11 02:12:08 PM UTC 24
Finished Sep 11 02:12:34 PM UTC 24
Peak memory 262924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953818608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1953818608
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/10.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg.1910544548
Short name T326
Test name
Test status
Simulation time 9580591734 ps
CPU time 1048.99 seconds
Started Sep 11 02:12:42 PM UTC 24
Finished Sep 11 02:30:24 PM UTC 24
Peak memory 285564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910544548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1910544548
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/10.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_alerts.2515521809
Short name T152
Test name
Test status
Simulation time 4585489502 ps
CPU time 37.46 seconds
Started Sep 11 02:12:02 PM UTC 24
Finished Sep 11 02:12:41 PM UTC 24
Peak memory 269172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515521809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2515521809
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/10.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_classes.2394784857
Short name T138
Test name
Test status
Simulation time 1703146063 ps
CPU time 33.09 seconds
Started Sep 11 02:12:03 PM UTC 24
Finished Sep 11 02:12:38 PM UTC 24
Peak memory 262908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394784857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2394784857
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/10.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/10.alert_handler_sig_int_fail.235943229
Short name T86
Test name
Test status
Simulation time 256390682 ps
CPU time 41.92 seconds
Started Sep 11 02:12:12 PM UTC 24
Finished Sep 11 02:12:56 PM UTC 24
Peak memory 262928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235943229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.235943229
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/10.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/10.alert_handler_smoke.717836421
Short name T400
Test name
Test status
Simulation time 587935626 ps
CPU time 50.74 seconds
Started Sep 11 02:11:08 PM UTC 24
Finished Sep 11 02:12:00 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717836421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.717836421
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/10.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/11.alert_handler_alert_accum_saturation.41152194
Short name T78
Test name
Test status
Simulation time 17761373 ps
CPU time 4.06 seconds
Started Sep 11 02:15:51 PM UTC 24
Finished Sep 11 02:15:56 PM UTC 24
Peak memory 263236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41152194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_h
andler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_h
andler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.41152194
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/11.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy.1589055661
Short name T62
Test name
Test status
Simulation time 5754153540 ps
CPU time 705.43 seconds
Started Sep 11 02:15:34 PM UTC 24
Finished Sep 11 02:27:29 PM UTC 24
Peak memory 285488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589055661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1589055661
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/11.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy_stress.1047319358
Short name T80
Test name
Test status
Simulation time 840552523 ps
CPU time 30.62 seconds
Started Sep 11 02:15:50 PM UTC 24
Finished Sep 11 02:16:22 PM UTC 24
Peak memory 262900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047319358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1047319358
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/11.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_alert_accum.763739317
Short name T409
Test name
Test status
Simulation time 22302230652 ps
CPU time 223.04 seconds
Started Sep 11 02:15:01 PM UTC 24
Finished Sep 11 02:18:48 PM UTC 24
Peak memory 269156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763739317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.763739317
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/11.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_intr_timeout.3782175548
Short name T75
Test name
Test status
Simulation time 1448483943 ps
CPU time 36.61 seconds
Started Sep 11 02:15:01 PM UTC 24
Finished Sep 11 02:15:39 PM UTC 24
Peak memory 269088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782175548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3782175548
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/11.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg.2607225305
Short name T352
Test name
Test status
Simulation time 17690199792 ps
CPU time 1462.19 seconds
Started Sep 11 02:15:36 PM UTC 24
Finished Sep 11 02:40:16 PM UTC 24
Peak memory 285492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607225305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2607225305
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/11.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg_stub_clk.625133143
Short name T313
Test name
Test status
Simulation time 22971198056 ps
CPU time 1446.49 seconds
Started Sep 11 02:15:48 PM UTC 24
Finished Sep 11 02:40:12 PM UTC 24
Peak memory 285492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625133143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.625133143
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/11.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_alerts.3550404484
Short name T73
Test name
Test status
Simulation time 7518450969 ps
CPU time 53.35 seconds
Started Sep 11 02:14:36 PM UTC 24
Finished Sep 11 02:15:31 PM UTC 24
Peak memory 263284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550404484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3550404484
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/11.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_classes.3544015960
Short name T58
Test name
Test status
Simulation time 271536095 ps
CPU time 34.91 seconds
Started Sep 11 02:14:44 PM UTC 24
Finished Sep 11 02:15:20 PM UTC 24
Peak memory 269396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544015960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3544015960
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/11.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/11.alert_handler_sig_int_fail.1261817465
Short name T77
Test name
Test status
Simulation time 358065014 ps
CPU time 24.64 seconds
Started Sep 11 02:15:22 PM UTC 24
Finished Sep 11 02:15:48 PM UTC 24
Peak memory 269036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261817465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1261817465
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/11.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/11.alert_handler_smoke.3668613256
Short name T74
Test name
Test status
Simulation time 9930340310 ps
CPU time 78.57 seconds
Started Sep 11 02:14:14 PM UTC 24
Finished Sep 11 02:15:35 PM UTC 24
Peak memory 269104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668613256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3668613256
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/11.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all.3399868928
Short name T289
Test name
Test status
Simulation time 91882898230 ps
CPU time 2740.13 seconds
Started Sep 11 02:15:51 PM UTC 24
Finished Sep 11 03:02:00 PM UTC 24
Peak memory 304600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399868928 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_stress_all.3399868928
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/11.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all_with_rand_reset.685169393
Short name T60
Test name
Test status
Simulation time 7558867512 ps
CPU time 417 seconds
Started Sep 11 02:16:00 PM UTC 24
Finished Sep 11 02:23:02 PM UTC 24
Peak memory 283568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=685169393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.al
ert_handler_stress_all_with_rand_reset.685169393
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy.2383508750
Short name T500
Test name
Test status
Simulation time 642253826204 ps
CPU time 2369.98 seconds
Started Sep 11 02:17:02 PM UTC 24
Finished Sep 11 02:57:01 PM UTC 24
Peak memory 288548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383508750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2383508750
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/12.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy_stress.3040965899
Short name T404
Test name
Test status
Simulation time 1139235246 ps
CPU time 18.68 seconds
Started Sep 11 02:17:21 PM UTC 24
Finished Sep 11 02:17:41 PM UTC 24
Peak memory 262976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040965899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3040965899
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/12.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_alert_accum.4025371895
Short name T406
Test name
Test status
Simulation time 1140202758 ps
CPU time 88.69 seconds
Started Sep 11 02:16:43 PM UTC 24
Finished Sep 11 02:18:13 PM UTC 24
Peak memory 269108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025371895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.4025371895
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/12.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_intr_timeout.2140648278
Short name T32
Test name
Test status
Simulation time 3021884991 ps
CPU time 55.66 seconds
Started Sep 11 02:16:23 PM UTC 24
Finished Sep 11 02:17:21 PM UTC 24
Peak memory 263192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140648278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2140648278
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/12.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg.7876492
Short name T324
Test name
Test status
Simulation time 662299807088 ps
CPU time 2177.97 seconds
Started Sep 11 02:17:07 PM UTC 24
Finished Sep 11 02:53:51 PM UTC 24
Peak memory 296120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7876492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +
UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.7876492
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/12.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg_stub_clk.2904341404
Short name T478
Test name
Test status
Simulation time 30288633629 ps
CPU time 1886.67 seconds
Started Sep 11 02:17:10 PM UTC 24
Finished Sep 11 02:48:59 PM UTC 24
Peak memory 285824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904341404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2904341404
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/12.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/12.alert_handler_ping_timeout.140984970
Short name T338
Test name
Test status
Simulation time 6012333304 ps
CPU time 118.83 seconds
Started Sep 11 02:17:07 PM UTC 24
Finished Sep 11 02:19:08 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140984970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.140984970
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/12.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_alerts.127940785
Short name T403
Test name
Test status
Simulation time 3872244132 ps
CPU time 63.75 seconds
Started Sep 11 02:16:01 PM UTC 24
Finished Sep 11 02:17:07 PM UTC 24
Peak memory 269468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127940785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.127940785
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/12.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_classes.2055698375
Short name T401
Test name
Test status
Simulation time 981691762 ps
CPU time 24.33 seconds
Started Sep 11 02:16:21 PM UTC 24
Finished Sep 11 02:16:47 PM UTC 24
Peak memory 262924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055698375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2055698375
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/12.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/12.alert_handler_sig_int_fail.3002002968
Short name T260
Test name
Test status
Simulation time 315686033 ps
CPU time 47.24 seconds
Started Sep 11 02:16:48 PM UTC 24
Finished Sep 11 02:17:38 PM UTC 24
Peak memory 262892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002002968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3002002968
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/12.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/12.alert_handler_smoke.4229667368
Short name T402
Test name
Test status
Simulation time 1231027918 ps
CPU time 64.61 seconds
Started Sep 11 02:16:00 PM UTC 24
Finished Sep 11 02:17:06 PM UTC 24
Peak memory 269112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229667368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.4229667368
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/12.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy.3675834225
Short name T372
Test name
Test status
Simulation time 12716594773 ps
CPU time 1220.62 seconds
Started Sep 11 02:18:15 PM UTC 24
Finished Sep 11 02:38:50 PM UTC 24
Peak memory 300152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675834225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3675834225
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/13.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy_stress.1070939653
Short name T411
Test name
Test status
Simulation time 136879241 ps
CPU time 10.08 seconds
Started Sep 11 02:18:55 PM UTC 24
Finished Sep 11 02:19:07 PM UTC 24
Peak memory 262976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070939653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1070939653
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/13.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_alert_accum.4225995524
Short name T309
Test name
Test status
Simulation time 5430005885 ps
CPU time 127.07 seconds
Started Sep 11 02:18:10 PM UTC 24
Finished Sep 11 02:20:20 PM UTC 24
Peak memory 264996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225995524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.4225995524
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/13.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_intr_timeout.2674712484
Short name T410
Test name
Test status
Simulation time 1260308352 ps
CPU time 44.12 seconds
Started Sep 11 02:18:08 PM UTC 24
Finished Sep 11 02:18:54 PM UTC 24
Peak memory 263000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674712484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2674712484
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/13.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg_stub_clk.2338466401
Short name T489
Test name
Test status
Simulation time 27880222403 ps
CPU time 2025.68 seconds
Started Sep 11 02:18:55 PM UTC 24
Finished Sep 11 02:53:06 PM UTC 24
Peak memory 299832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338466401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2338466401
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/13.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/13.alert_handler_ping_timeout.1116544229
Short name T343
Test name
Test status
Simulation time 2628952053 ps
CPU time 163.44 seconds
Started Sep 11 02:18:39 PM UTC 24
Finished Sep 11 02:21:25 PM UTC 24
Peak memory 263296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116544229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1116544229
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/13.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_alerts.3390162143
Short name T408
Test name
Test status
Simulation time 1037930156 ps
CPU time 41.44 seconds
Started Sep 11 02:17:54 PM UTC 24
Finished Sep 11 02:18:37 PM UTC 24
Peak memory 269036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390162143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3390162143
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/13.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_classes.1389396042
Short name T407
Test name
Test status
Simulation time 134005942 ps
CPU time 19.15 seconds
Started Sep 11 02:17:54 PM UTC 24
Finished Sep 11 02:18:15 PM UTC 24
Peak memory 262924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389396042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1389396042
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/13.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/13.alert_handler_sig_int_fail.1096049775
Short name T26
Test name
Test status
Simulation time 1882017712 ps
CPU time 89.47 seconds
Started Sep 11 02:18:14 PM UTC 24
Finished Sep 11 02:19:46 PM UTC 24
Peak memory 269036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096049775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1096049775
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/13.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/13.alert_handler_smoke.1401880805
Short name T405
Test name
Test status
Simulation time 145308312 ps
CPU time 19.46 seconds
Started Sep 11 02:17:48 PM UTC 24
Finished Sep 11 02:18:09 PM UTC 24
Peak memory 269040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401880805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1401880805
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/13.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all.2786115772
Short name T271
Test name
Test status
Simulation time 2438013469 ps
CPU time 105.61 seconds
Started Sep 11 02:19:02 PM UTC 24
Finished Sep 11 02:20:50 PM UTC 24
Peak memory 269104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786115772 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_stress_all.2786115772
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/13.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all_with_rand_reset.3018935889
Short name T27
Test name
Test status
Simulation time 3966268375 ps
CPU time 104.9 seconds
Started Sep 11 02:19:09 PM UTC 24
Finished Sep 11 02:20:56 PM UTC 24
Peak memory 279468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3018935889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.a
lert_handler_stress_all_with_rand_reset.3018935889
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/14.alert_handler_alert_accum_saturation.3270833275
Short name T248
Test name
Test status
Simulation time 167245086 ps
CPU time 6.15 seconds
Started Sep 11 02:20:57 PM UTC 24
Finished Sep 11 02:21:04 PM UTC 24
Peak memory 263560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270833275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3270833275
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/14.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy.2295487682
Short name T339
Test name
Test status
Simulation time 44307051993 ps
CPU time 1225.5 seconds
Started Sep 11 02:20:01 PM UTC 24
Finished Sep 11 02:40:42 PM UTC 24
Peak memory 296056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295487682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2295487682
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/14.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy_stress.2040538587
Short name T413
Test name
Test status
Simulation time 455108042 ps
CPU time 17.89 seconds
Started Sep 11 02:20:45 PM UTC 24
Finished Sep 11 02:21:04 PM UTC 24
Peak memory 263104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040538587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2040538587
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/14.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_alert_accum.4287863808
Short name T420
Test name
Test status
Simulation time 13188067653 ps
CPU time 245.28 seconds
Started Sep 11 02:19:47 PM UTC 24
Finished Sep 11 02:23:56 PM UTC 24
Peak memory 265072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287863808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.4287863808
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/14.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_intr_timeout.2760444162
Short name T99
Test name
Test status
Simulation time 3491520034 ps
CPU time 35.54 seconds
Started Sep 11 02:19:26 PM UTC 24
Finished Sep 11 02:20:03 PM UTC 24
Peak memory 269528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760444162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2760444162
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/14.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg.3062657626
Short name T362
Test name
Test status
Simulation time 30919213119 ps
CPU time 1770.92 seconds
Started Sep 11 02:20:21 PM UTC 24
Finished Sep 11 02:50:12 PM UTC 24
Peak memory 285492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062657626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3062657626
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/14.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg_stub_clk.54630163
Short name T312
Test name
Test status
Simulation time 10103338580 ps
CPU time 836.57 seconds
Started Sep 11 02:20:36 PM UTC 24
Finished Sep 11 02:34:42 PM UTC 24
Peak memory 285820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54630163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.54630163
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/14.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/14.alert_handler_ping_timeout.2367082041
Short name T323
Test name
Test status
Simulation time 9348727028 ps
CPU time 450.24 seconds
Started Sep 11 02:20:03 PM UTC 24
Finished Sep 11 02:27:39 PM UTC 24
Peak memory 262968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367082041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2367082041
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/14.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_alerts.309375360
Short name T412
Test name
Test status
Simulation time 240664506 ps
CPU time 4.99 seconds
Started Sep 11 02:19:20 PM UTC 24
Finished Sep 11 02:19:26 PM UTC 24
Peak memory 265264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309375360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.309375360
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/14.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_classes.2735647321
Short name T134
Test name
Test status
Simulation time 1608766099 ps
CPU time 36.42 seconds
Started Sep 11 02:19:22 PM UTC 24
Finished Sep 11 02:20:00 PM UTC 24
Peak memory 269036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735647321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2735647321
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/14.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/14.alert_handler_sig_int_fail.2561590342
Short name T258
Test name
Test status
Simulation time 910238431 ps
CPU time 59.46 seconds
Started Sep 11 02:20:00 PM UTC 24
Finished Sep 11 02:21:02 PM UTC 24
Peak memory 262892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561590342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2561590342
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/14.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all.3513107638
Short name T61
Test name
Test status
Simulation time 10643942754 ps
CPU time 177.77 seconds
Started Sep 11 02:20:50 PM UTC 24
Finished Sep 11 02:23:51 PM UTC 24
Peak memory 269104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513107638 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_stress_all.3513107638
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/14.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all_with_rand_reset.2020782649
Short name T222
Test name
Test status
Simulation time 4037501608 ps
CPU time 137.32 seconds
Started Sep 11 02:21:03 PM UTC 24
Finished Sep 11 02:23:22 PM UTC 24
Peak memory 279540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2020782649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.a
lert_handler_stress_all_with_rand_reset.2020782649
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/15.alert_handler_alert_accum_saturation.1457520059
Short name T249
Test name
Test status
Simulation time 52565849 ps
CPU time 3.55 seconds
Started Sep 11 02:22:42 PM UTC 24
Finished Sep 11 02:22:47 PM UTC 24
Peak memory 263496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457520059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1457520059
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/15.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy.1277651932
Short name T569
Test name
Test status
Simulation time 49175912995 ps
CPU time 3246.72 seconds
Started Sep 11 02:21:41 PM UTC 24
Finished Sep 11 03:16:25 PM UTC 24
Peak memory 304604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277651932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1277651932
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/15.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy_stress.1395172046
Short name T416
Test name
Test status
Simulation time 167586529 ps
CPU time 11.08 seconds
Started Sep 11 02:22:28 PM UTC 24
Finished Sep 11 02:22:41 PM UTC 24
Peak memory 263292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395172046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1395172046
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/15.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_alert_accum.1162396609
Short name T417
Test name
Test status
Simulation time 7048018717 ps
CPU time 87.8 seconds
Started Sep 11 02:21:37 PM UTC 24
Finished Sep 11 02:23:07 PM UTC 24
Peak memory 269488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162396609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1162396609
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/15.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_intr_timeout.443335935
Short name T414
Test name
Test status
Simulation time 197624811 ps
CPU time 18.81 seconds
Started Sep 11 02:21:20 PM UTC 24
Finished Sep 11 02:21:40 PM UTC 24
Peak memory 267096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443335935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.443335935
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/15.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg_stub_clk.593679077
Short name T520
Test name
Test status
Simulation time 179378815369 ps
CPU time 2458.16 seconds
Started Sep 11 02:22:26 PM UTC 24
Finished Sep 11 03:03:53 PM UTC 24
Peak memory 304608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593679077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.593679077
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/15.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/15.alert_handler_ping_timeout.2865249480
Short name T106
Test name
Test status
Simulation time 48504555063 ps
CPU time 455.66 seconds
Started Sep 11 02:22:03 PM UTC 24
Finished Sep 11 02:29:44 PM UTC 24
Peak memory 262968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865249480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2865249480
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/15.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_alerts.1632704379
Short name T59
Test name
Test status
Simulation time 914283345 ps
CPU time 72.86 seconds
Started Sep 11 02:21:06 PM UTC 24
Finished Sep 11 02:22:20 PM UTC 24
Peak memory 262892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632704379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1632704379
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/15.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_classes.528392620
Short name T143
Test name
Test status
Simulation time 1240299826 ps
CPU time 103.18 seconds
Started Sep 11 02:21:20 PM UTC 24
Finished Sep 11 02:23:05 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528392620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.528392620
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/15.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/15.alert_handler_sig_int_fail.4286755273
Short name T300
Test name
Test status
Simulation time 2764211251 ps
CPU time 62.58 seconds
Started Sep 11 02:21:37 PM UTC 24
Finished Sep 11 02:22:42 PM UTC 24
Peak memory 263068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286755273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.4286755273
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/15.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/15.alert_handler_smoke.3350229605
Short name T415
Test name
Test status
Simulation time 4869556537 ps
CPU time 56.33 seconds
Started Sep 11 02:21:05 PM UTC 24
Finished Sep 11 02:22:03 PM UTC 24
Peak memory 269304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350229605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3350229605
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/15.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all.408923678
Short name T317
Test name
Test status
Simulation time 124313218676 ps
CPU time 1680.99 seconds
Started Sep 11 02:22:41 PM UTC 24
Finished Sep 11 02:51:03 PM UTC 24
Peak memory 285556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408923678 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_stress_all.408923678
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/15.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/16.alert_handler_alert_accum_saturation.1701399041
Short name T250
Test name
Test status
Simulation time 131207569 ps
CPU time 5.08 seconds
Started Sep 11 02:24:05 PM UTC 24
Finished Sep 11 02:24:11 PM UTC 24
Peak memory 263240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701399041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1701399041
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/16.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy.343096384
Short name T485
Test name
Test status
Simulation time 94043672712 ps
CPU time 1637.95 seconds
Started Sep 11 02:23:32 PM UTC 24
Finished Sep 11 02:51:10 PM UTC 24
Peak memory 279344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343096384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.343096384
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/16.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy_stress.803709221
Short name T422
Test name
Test status
Simulation time 636478292 ps
CPU time 15.27 seconds
Started Sep 11 02:23:57 PM UTC 24
Finished Sep 11 02:24:14 PM UTC 24
Peak memory 262972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803709221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.803709221
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/16.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_alert_accum.1977568305
Short name T431
Test name
Test status
Simulation time 5950030215 ps
CPU time 283.06 seconds
Started Sep 11 02:23:24 PM UTC 24
Finished Sep 11 02:28:11 PM UTC 24
Peak memory 269424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977568305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1977568305
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/16.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_intr_timeout.2707046174
Short name T100
Test name
Test status
Simulation time 285923381 ps
CPU time 21.33 seconds
Started Sep 11 02:23:21 PM UTC 24
Finished Sep 11 02:23:44 PM UTC 24
Peak memory 263256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707046174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2707046174
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/16.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg.771163644
Short name T368
Test name
Test status
Simulation time 109958986700 ps
CPU time 1528.25 seconds
Started Sep 11 02:23:52 PM UTC 24
Finished Sep 11 02:49:38 PM UTC 24
Peak memory 285488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771163644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.771163644
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/16.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg_stub_clk.1450081948
Short name T475
Test name
Test status
Simulation time 68061926528 ps
CPU time 1436.74 seconds
Started Sep 11 02:23:56 PM UTC 24
Finished Sep 11 02:48:10 PM UTC 24
Peak memory 285492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450081948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1450081948
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/16.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/16.alert_handler_ping_timeout.3203250247
Short name T332
Test name
Test status
Simulation time 2451207615 ps
CPU time 95.65 seconds
Started Sep 11 02:23:45 PM UTC 24
Finished Sep 11 02:25:22 PM UTC 24
Peak memory 262976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203250247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3203250247
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/16.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_alerts.1500786247
Short name T418
Test name
Test status
Simulation time 230248051 ps
CPU time 12.65 seconds
Started Sep 11 02:23:06 PM UTC 24
Finished Sep 11 02:23:20 PM UTC 24
Peak memory 269036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500786247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1500786247
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/16.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_classes.3344948520
Short name T30
Test name
Test status
Simulation time 197969386 ps
CPU time 21.24 seconds
Started Sep 11 02:23:08 PM UTC 24
Finished Sep 11 02:23:31 PM UTC 24
Peak memory 269044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344948520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3344948520
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/16.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/16.alert_handler_sig_int_fail.1634259525
Short name T421
Test name
Test status
Simulation time 418074470 ps
CPU time 31.53 seconds
Started Sep 11 02:23:30 PM UTC 24
Finished Sep 11 02:24:03 PM UTC 24
Peak memory 262892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634259525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1634259525
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/16.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/16.alert_handler_smoke.1123091631
Short name T419
Test name
Test status
Simulation time 758830225 ps
CPU time 49.8 seconds
Started Sep 11 02:23:04 PM UTC 24
Finished Sep 11 02:23:56 PM UTC 24
Peak memory 269112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123091631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1123091631
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/16.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all.1683229069
Short name T105
Test name
Test status
Simulation time 924588551 ps
CPU time 82.06 seconds
Started Sep 11 02:24:04 PM UTC 24
Finished Sep 11 02:25:28 PM UTC 24
Peak memory 269036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683229069 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_stress_all.1683229069
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/16.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/17.alert_handler_alert_accum_saturation.1404044662
Short name T251
Test name
Test status
Simulation time 142321998 ps
CPU time 5.8 seconds
Started Sep 11 02:27:08 PM UTC 24
Finished Sep 11 02:27:14 PM UTC 24
Peak memory 263496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404044662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1404044662
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/17.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy.1493448800
Short name T561
Test name
Test status
Simulation time 89122060616 ps
CPU time 2969.84 seconds
Started Sep 11 02:25:12 PM UTC 24
Finished Sep 11 03:15:17 PM UTC 24
Peak memory 304600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493448800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1493448800
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/17.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy_stress.25941704
Short name T428
Test name
Test status
Simulation time 849212410 ps
CPU time 19.36 seconds
Started Sep 11 02:25:38 PM UTC 24
Finished Sep 11 02:25:59 PM UTC 24
Peak memory 263284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25941704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_h
andler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.25941704
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/17.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_alert_accum.3162067003
Short name T425
Test name
Test status
Simulation time 144976254 ps
CPU time 17.24 seconds
Started Sep 11 02:24:44 PM UTC 24
Finished Sep 11 02:25:03 PM UTC 24
Peak memory 269036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162067003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3162067003
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/17.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_intr_timeout.3489205962
Short name T426
Test name
Test status
Simulation time 4402543996 ps
CPU time 42.47 seconds
Started Sep 11 02:24:28 PM UTC 24
Finished Sep 11 02:25:12 PM UTC 24
Peak memory 269104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489205962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3489205962
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/17.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg_stub_clk.387331074
Short name T451
Test name
Test status
Simulation time 33335192115 ps
CPU time 869.93 seconds
Started Sep 11 02:25:29 PM UTC 24
Finished Sep 11 02:40:10 PM UTC 24
Peak memory 285492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387331074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.387331074
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/17.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_alerts.2113932560
Short name T424
Test name
Test status
Simulation time 1726109229 ps
CPU time 27.2 seconds
Started Sep 11 02:24:15 PM UTC 24
Finished Sep 11 02:24:43 PM UTC 24
Peak memory 269108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113932560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2113932560
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/17.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_classes.3890557822
Short name T427
Test name
Test status
Simulation time 1031350648 ps
CPU time 49.97 seconds
Started Sep 11 02:24:26 PM UTC 24
Finished Sep 11 02:25:17 PM UTC 24
Peak memory 269460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890557822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3890557822
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/17.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/17.alert_handler_sig_int_fail.3945153473
Short name T101
Test name
Test status
Simulation time 2656157534 ps
CPU time 30.86 seconds
Started Sep 11 02:25:04 PM UTC 24
Finished Sep 11 02:25:36 PM UTC 24
Peak memory 263028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945153473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3945153473
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/17.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/17.alert_handler_smoke.1702647966
Short name T423
Test name
Test status
Simulation time 410501609 ps
CPU time 11.46 seconds
Started Sep 11 02:24:15 PM UTC 24
Finished Sep 11 02:24:27 PM UTC 24
Peak memory 269368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702647966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1702647966
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/17.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/17.alert_handler_stress_all.4209134595
Short name T551
Test name
Test status
Simulation time 187155365824 ps
CPU time 2741.47 seconds
Started Sep 11 02:25:59 PM UTC 24
Finished Sep 11 03:12:12 PM UTC 24
Peak memory 314848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209134595 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_stress_all.4209134595
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/17.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/18.alert_handler_alert_accum_saturation.3038193873
Short name T252
Test name
Test status
Simulation time 14215471 ps
CPU time 3.66 seconds
Started Sep 11 02:29:24 PM UTC 24
Finished Sep 11 02:29:28 PM UTC 24
Peak memory 263496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038193873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.3038193873
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/18.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy.3566309064
Short name T455
Test name
Test status
Simulation time 44161368987 ps
CPU time 764.91 seconds
Started Sep 11 02:27:51 PM UTC 24
Finished Sep 11 02:40:45 PM UTC 24
Peak memory 285488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566309064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3566309064
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/18.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy_stress.4244405765
Short name T433
Test name
Test status
Simulation time 2689715428 ps
CPU time 59.75 seconds
Started Sep 11 02:28:25 PM UTC 24
Finished Sep 11 02:29:27 PM UTC 24
Peak memory 263296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244405765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.4244405765
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/18.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_alert_accum.3801030488
Short name T436
Test name
Test status
Simulation time 13501911131 ps
CPU time 201.31 seconds
Started Sep 11 02:27:30 PM UTC 24
Finished Sep 11 02:30:55 PM UTC 24
Peak memory 264996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801030488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3801030488
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/18.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_intr_timeout.1952618524
Short name T124
Test name
Test status
Simulation time 1336452252 ps
CPU time 36.19 seconds
Started Sep 11 02:27:28 PM UTC 24
Finished Sep 11 02:28:05 PM UTC 24
Peak memory 269400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952618524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1952618524
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/18.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg.2556667923
Short name T371
Test name
Test status
Simulation time 34847846977 ps
CPU time 2252.49 seconds
Started Sep 11 02:28:06 PM UTC 24
Finished Sep 11 03:06:04 PM UTC 24
Peak memory 288224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556667923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2556667923
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/18.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg_stub_clk.2315009538
Short name T490
Test name
Test status
Simulation time 63853346528 ps
CPU time 1488.01 seconds
Started Sep 11 02:28:11 PM UTC 24
Finished Sep 11 02:53:18 PM UTC 24
Peak memory 301876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315009538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2315009538
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/18.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_alerts.46809966
Short name T63
Test name
Test status
Simulation time 3383682777 ps
CPU time 80.47 seconds
Started Sep 11 02:27:15 PM UTC 24
Finished Sep 11 02:28:38 PM UTC 24
Peak memory 269176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46809966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ran
dom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.46809966
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/18.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_classes.3829965824
Short name T112
Test name
Test status
Simulation time 1997212316 ps
CPU time 39.01 seconds
Started Sep 11 02:27:22 PM UTC 24
Finished Sep 11 02:28:02 PM UTC 24
Peak memory 269140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829965824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3829965824
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/18.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/18.alert_handler_sig_int_fail.1393045023
Short name T123
Test name
Test status
Simulation time 69608511 ps
CPU time 7.9 seconds
Started Sep 11 02:27:41 PM UTC 24
Finished Sep 11 02:27:50 PM UTC 24
Peak memory 252764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393045023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1393045023
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/18.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/18.alert_handler_smoke.400377418
Short name T430
Test name
Test status
Simulation time 449182280 ps
CPU time 10.32 seconds
Started Sep 11 02:27:15 PM UTC 24
Finished Sep 11 02:27:27 PM UTC 24
Peak memory 265268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400377418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.400377418
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/18.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/19.alert_handler_alert_accum_saturation.3310725031
Short name T253
Test name
Test status
Simulation time 37539628 ps
CPU time 5.52 seconds
Started Sep 11 02:31:27 PM UTC 24
Finished Sep 11 02:31:34 PM UTC 24
Peak memory 263240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310725031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3310725031
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/19.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy.365833476
Short name T470
Test name
Test status
Simulation time 7870075073 ps
CPU time 975.26 seconds
Started Sep 11 02:30:13 PM UTC 24
Finished Sep 11 02:46:40 PM UTC 24
Peak memory 285564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365833476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.365833476
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/19.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy_stress.2516943769
Short name T429
Test name
Test status
Simulation time 2754846856 ps
CPU time 31.12 seconds
Started Sep 11 02:30:56 PM UTC 24
Finished Sep 11 02:31:29 PM UTC 24
Peak memory 262968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516943769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2516943769
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/19.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_alert_accum.495113542
Short name T440
Test name
Test status
Simulation time 3491188773 ps
CPU time 174.56 seconds
Started Sep 11 02:30:08 PM UTC 24
Finished Sep 11 02:33:06 PM UTC 24
Peak memory 269204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495113542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.495113542
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/19.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_intr_timeout.247198631
Short name T434
Test name
Test status
Simulation time 262200329 ps
CPU time 7.48 seconds
Started Sep 11 02:29:59 PM UTC 24
Finished Sep 11 02:30:08 PM UTC 24
Peak memory 252760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247198631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.247198631
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/19.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg_stub_clk.3175829064
Short name T503
Test name
Test status
Simulation time 74032528736 ps
CPU time 1653.88 seconds
Started Sep 11 02:30:51 PM UTC 24
Finished Sep 11 02:58:44 PM UTC 24
Peak memory 301876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175829064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3175829064
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/19.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/19.alert_handler_ping_timeout.408272130
Short name T350
Test name
Test status
Simulation time 10657439050 ps
CPU time 357.24 seconds
Started Sep 11 02:30:23 PM UTC 24
Finished Sep 11 02:36:24 PM UTC 24
Peak memory 263040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408272130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.408272130
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/19.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_alerts.3562381644
Short name T64
Test name
Test status
Simulation time 3837700040 ps
CPU time 21.44 seconds
Started Sep 11 02:29:35 PM UTC 24
Finished Sep 11 02:29:58 PM UTC 24
Peak memory 269100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562381644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3562381644
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/19.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_classes.2012389040
Short name T109
Test name
Test status
Simulation time 680062546 ps
CPU time 25.25 seconds
Started Sep 11 02:29:45 PM UTC 24
Finished Sep 11 02:30:12 PM UTC 24
Peak memory 262924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012389040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2012389040
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/19.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/19.alert_handler_sig_int_fail.3151748270
Short name T340
Test name
Test status
Simulation time 2939760610 ps
CPU time 63.92 seconds
Started Sep 11 02:30:13 PM UTC 24
Finished Sep 11 02:31:18 PM UTC 24
Peak memory 269428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151748270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3151748270
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/19.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/19.alert_handler_smoke.440931323
Short name T435
Test name
Test status
Simulation time 325098042 ps
CPU time 40.72 seconds
Started Sep 11 02:29:30 PM UTC 24
Finished Sep 11 02:30:12 PM UTC 24
Peak memory 269364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440931323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.440931323
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/19.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all.1217785354
Short name T133
Test name
Test status
Simulation time 73105579837 ps
CPU time 3890.67 seconds
Started Sep 11 02:31:19 PM UTC 24
Finished Sep 11 03:36:51 PM UTC 24
Peak memory 318944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217785354 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_stress_all.1217785354
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/19.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all_with_rand_reset.3798655975
Short name T102
Test name
Test status
Simulation time 13974357957 ps
CPU time 331.32 seconds
Started Sep 11 02:31:29 PM UTC 24
Finished Sep 11 02:37:06 PM UTC 24
Peak memory 286004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3798655975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.a
lert_handler_stress_all_with_rand_reset.3798655975
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/2.alert_handler_alert_accum_saturation.1912032319
Short name T46
Test name
Test status
Simulation time 40895198 ps
CPU time 6.26 seconds
Started Sep 11 01:57:46 PM UTC 24
Finished Sep 11 01:57:54 PM UTC 24
Peak memory 263492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912032319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1912032319
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy.2990535921
Short name T259
Test name
Test status
Simulation time 74602726265 ps
CPU time 1207.98 seconds
Started Sep 11 01:57:30 PM UTC 24
Finished Sep 11 02:17:52 PM UTC 24
Peak memory 300220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990535921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2990535921
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy_stress.863263607
Short name T6
Test name
Test status
Simulation time 2528740639 ps
CPU time 16.46 seconds
Started Sep 11 01:57:42 PM UTC 24
Finished Sep 11 01:57:59 PM UTC 24
Peak memory 263292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863263607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.863263607
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_alert_accum.1275220455
Short name T72
Test name
Test status
Simulation time 150847625 ps
CPU time 22.51 seconds
Started Sep 11 01:57:19 PM UTC 24
Finished Sep 11 01:57:43 PM UTC 24
Peak memory 269364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275220455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1275220455
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_intr_timeout.2059176490
Short name T25
Test name
Test status
Simulation time 886328740 ps
CPU time 21.52 seconds
Started Sep 11 01:57:18 PM UTC 24
Finished Sep 11 01:57:41 PM UTC 24
Peak memory 262892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059176490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2059176490
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg_stub_clk.3905946891
Short name T329
Test name
Test status
Simulation time 25631317859 ps
CPU time 1279.58 seconds
Started Sep 11 01:57:39 PM UTC 24
Finished Sep 11 02:19:15 PM UTC 24
Peak memory 285564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905946891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3905946891
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/2.alert_handler_ping_timeout.2766310860
Short name T17
Test name
Test status
Simulation time 7456562234 ps
CPU time 277.72 seconds
Started Sep 11 01:57:30 PM UTC 24
Finished Sep 11 02:02:12 PM UTC 24
Peak memory 263036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766310860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2766310860
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_alerts.1203260852
Short name T24
Test name
Test status
Simulation time 873833235 ps
CPU time 21.16 seconds
Started Sep 11 01:57:16 PM UTC 24
Finished Sep 11 01:57:38 PM UTC 24
Peak memory 269104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203260852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1203260852
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_classes.1102824826
Short name T37
Test name
Test status
Simulation time 670972397 ps
CPU time 12.91 seconds
Started Sep 11 01:57:16 PM UTC 24
Finished Sep 11 01:57:30 PM UTC 24
Peak memory 266988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102824826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1102824826
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/2.alert_handler_sec_cm.1381503160
Short name T8
Test name
Test status
Simulation time 180933112 ps
CPU time 15.24 seconds
Started Sep 11 01:57:54 PM UTC 24
Finished Sep 11 01:58:11 PM UTC 24
Peak memory 295260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381503160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1381503160
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/2.alert_handler_sig_int_fail.3231686320
Short name T94
Test name
Test status
Simulation time 371112435 ps
CPU time 14.07 seconds
Started Sep 11 01:57:22 PM UTC 24
Finished Sep 11 01:57:37 PM UTC 24
Peak memory 269072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231686320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3231686320
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/2.alert_handler_smoke.3070840844
Short name T45
Test name
Test status
Simulation time 916512336 ps
CPU time 15.07 seconds
Started Sep 11 01:57:13 PM UTC 24
Finished Sep 11 01:57:29 PM UTC 24
Peak memory 262892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070840844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3070840844
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/20.alert_handler_entropy.511765636
Short name T546
Test name
Test status
Simulation time 74185817328 ps
CPU time 2273.63 seconds
Started Sep 11 02:32:22 PM UTC 24
Finished Sep 11 03:10:41 PM UTC 24
Peak memory 304680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511765636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.511765636
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/20.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_alert_accum.1379744332
Short name T438
Test name
Test status
Simulation time 329235236 ps
CPU time 19.71 seconds
Started Sep 11 02:32:16 PM UTC 24
Finished Sep 11 02:32:37 PM UTC 24
Peak memory 269032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379744332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1379744332
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/20.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_intr_timeout.3109962042
Short name T439
Test name
Test status
Simulation time 1146272497 ps
CPU time 36.56 seconds
Started Sep 11 02:32:01 PM UTC 24
Finished Sep 11 02:32:39 PM UTC 24
Peak memory 269072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109962042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3109962042
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/20.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg.1768810255
Short name T380
Test name
Test status
Simulation time 34534901749 ps
CPU time 2293 seconds
Started Sep 11 02:32:38 PM UTC 24
Finished Sep 11 03:11:17 PM UTC 24
Peak memory 304608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768810255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1768810255
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/20.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg_stub_clk.1703405261
Short name T554
Test name
Test status
Simulation time 57563283955 ps
CPU time 2464.74 seconds
Started Sep 11 02:32:40 PM UTC 24
Finished Sep 11 03:14:14 PM UTC 24
Peak memory 298604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703405261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1703405261
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/20.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/20.alert_handler_ping_timeout.3970601706
Short name T353
Test name
Test status
Simulation time 115616438560 ps
CPU time 311.57 seconds
Started Sep 11 02:32:31 PM UTC 24
Finished Sep 11 02:37:47 PM UTC 24
Peak memory 267392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970601706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3970601706
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/20.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_alerts.3865955978
Short name T437
Test name
Test status
Simulation time 287732880 ps
CPU time 10.01 seconds
Started Sep 11 02:31:48 PM UTC 24
Finished Sep 11 02:31:59 PM UTC 24
Peak memory 267060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865955978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3865955978
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/20.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_classes.2945476860
Short name T305
Test name
Test status
Simulation time 732267190 ps
CPU time 17.55 seconds
Started Sep 11 02:31:57 PM UTC 24
Finished Sep 11 02:32:15 PM UTC 24
Peak memory 263252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945476860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2945476860
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/20.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/20.alert_handler_sig_int_fail.1637820050
Short name T65
Test name
Test status
Simulation time 3103421812 ps
CPU time 73.89 seconds
Started Sep 11 02:32:18 PM UTC 24
Finished Sep 11 02:33:34 PM UTC 24
Peak memory 269428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637820050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1637820050
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/20.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/20.alert_handler_smoke.4053877273
Short name T308
Test name
Test status
Simulation time 1003718900 ps
CPU time 54.06 seconds
Started Sep 11 02:31:34 PM UTC 24
Finished Sep 11 02:32:30 PM UTC 24
Peak memory 269368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053877273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.4053877273
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/20.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all.583708021
Short name T131
Test name
Test status
Simulation time 13820455267 ps
CPU time 291.29 seconds
Started Sep 11 02:33:07 PM UTC 24
Finished Sep 11 02:38:02 PM UTC 24
Peak memory 269492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583708021 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_stress_all.583708021
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/20.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all_with_rand_reset.1080483296
Short name T104
Test name
Test status
Simulation time 14170291232 ps
CPU time 383.22 seconds
Started Sep 11 02:33:35 PM UTC 24
Finished Sep 11 02:40:04 PM UTC 24
Peak memory 281520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1080483296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.a
lert_handler_stress_all_with_rand_reset.1080483296
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_alert_accum.1515776370
Short name T454
Test name
Test status
Simulation time 7918032869 ps
CPU time 309.28 seconds
Started Sep 11 02:35:21 PM UTC 24
Finished Sep 11 02:40:34 PM UTC 24
Peak memory 269100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515776370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1515776370
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/21.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_intr_timeout.1599706631
Short name T142
Test name
Test status
Simulation time 893956911 ps
CPU time 58.2 seconds
Started Sep 11 02:34:44 PM UTC 24
Finished Sep 11 02:35:44 PM UTC 24
Peak memory 263000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599706631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1599706631
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/21.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg.2186751887
Short name T537
Test name
Test status
Simulation time 260262594516 ps
CPU time 1994.5 seconds
Started Sep 11 02:35:58 PM UTC 24
Finished Sep 11 03:09:35 PM UTC 24
Peak memory 301876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186751887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2186751887
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/21.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg_stub_clk.2525188231
Short name T578
Test name
Test status
Simulation time 43422958027 ps
CPU time 2538 seconds
Started Sep 11 02:36:16 PM UTC 24
Finished Sep 11 03:19:03 PM UTC 24
Peak memory 304608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525188231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2525188231
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/21.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/21.alert_handler_ping_timeout.383512610
Short name T462
Test name
Test status
Simulation time 78762569163 ps
CPU time 354.82 seconds
Started Sep 11 02:35:55 PM UTC 24
Finished Sep 11 02:41:54 PM UTC 24
Peak memory 269184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383512610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.383512610
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_alerts.1688155254
Short name T442
Test name
Test status
Simulation time 171121805 ps
CPU time 27.33 seconds
Started Sep 11 02:34:10 PM UTC 24
Finished Sep 11 02:34:38 PM UTC 24
Peak memory 269108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688155254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1688155254
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/21.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_classes.1687809639
Short name T443
Test name
Test status
Simulation time 1845521826 ps
CPU time 43.13 seconds
Started Sep 11 02:34:40 PM UTC 24
Finished Sep 11 02:35:25 PM UTC 24
Peak memory 262892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687809639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1687809639
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/21.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/21.alert_handler_sig_int_fail.1929328622
Short name T444
Test name
Test status
Simulation time 320786451 ps
CPU time 30.17 seconds
Started Sep 11 02:35:26 PM UTC 24
Finished Sep 11 02:35:57 PM UTC 24
Peak memory 269036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929328622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1929328622
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/21.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/21.alert_handler_smoke.3439636952
Short name T441
Test name
Test status
Simulation time 110199226 ps
CPU time 6.94 seconds
Started Sep 11 02:34:01 PM UTC 24
Finished Sep 11 02:34:09 PM UTC 24
Peak memory 262896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439636952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.3439636952
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/21.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all.2606775137
Short name T598
Test name
Test status
Simulation time 45403256625 ps
CPU time 2823.54 seconds
Started Sep 11 02:36:25 PM UTC 24
Finished Sep 11 03:24:00 PM UTC 24
Peak memory 320984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606775137 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_stress_all.2606775137
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/21.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/22.alert_handler_entropy.2038704965
Short name T542
Test name
Test status
Simulation time 64081358015 ps
CPU time 1921.17 seconds
Started Sep 11 02:38:06 PM UTC 24
Finished Sep 11 03:10:29 PM UTC 24
Peak memory 300152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038704965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2038704965
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/22.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_alert_accum.2364009523
Short name T463
Test name
Test status
Simulation time 13851348618 ps
CPU time 242.78 seconds
Started Sep 11 02:37:52 PM UTC 24
Finished Sep 11 02:41:59 PM UTC 24
Peak memory 269488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364009523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2364009523
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/22.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_intr_timeout.3503968443
Short name T448
Test name
Test status
Simulation time 591201931 ps
CPU time 26.78 seconds
Started Sep 11 02:37:47 PM UTC 24
Finished Sep 11 02:38:16 PM UTC 24
Peak memory 263256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503968443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3503968443
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/22.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg.2819230112
Short name T361
Test name
Test status
Simulation time 131999426109 ps
CPU time 1906.67 seconds
Started Sep 11 02:38:17 PM UTC 24
Finished Sep 11 03:10:25 PM UTC 24
Peak memory 301876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819230112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2819230112
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/22.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/22.alert_handler_ping_timeout.105633231
Short name T303
Test name
Test status
Simulation time 7295649863 ps
CPU time 295.67 seconds
Started Sep 11 02:38:06 PM UTC 24
Finished Sep 11 02:43:06 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105633231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.105633231
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_alerts.4253457347
Short name T445
Test name
Test status
Simulation time 114175245 ps
CPU time 13.34 seconds
Started Sep 11 02:37:26 PM UTC 24
Finished Sep 11 02:37:41 PM UTC 24
Peak memory 269108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253457347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.4253457347
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/22.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_classes.2417283560
Short name T447
Test name
Test status
Simulation time 648261205 ps
CPU time 11.43 seconds
Started Sep 11 02:37:41 PM UTC 24
Finished Sep 11 02:37:54 PM UTC 24
Peak memory 262996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417283560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2417283560
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/22.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/22.alert_handler_sig_int_fail.875382759
Short name T147
Test name
Test status
Simulation time 928589371 ps
CPU time 27.19 seconds
Started Sep 11 02:37:55 PM UTC 24
Finished Sep 11 02:38:23 PM UTC 24
Peak memory 262896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875382759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.875382759
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/22.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/22.alert_handler_smoke.3069501178
Short name T446
Test name
Test status
Simulation time 723153361 ps
CPU time 42.62 seconds
Started Sep 11 02:37:06 PM UTC 24
Finished Sep 11 02:37:51 PM UTC 24
Peak memory 269040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069501178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3069501178
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/22.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all.935982989
Short name T522
Test name
Test status
Simulation time 58486880685 ps
CPU time 1504.67 seconds
Started Sep 11 02:38:52 PM UTC 24
Finished Sep 11 03:04:15 PM UTC 24
Peak memory 312108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935982989 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_stress_all.935982989
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/22.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all_with_rand_reset.3854921753
Short name T69
Test name
Test status
Simulation time 5837137352 ps
CPU time 433.88 seconds
Started Sep 11 02:39:23 PM UTC 24
Finished Sep 11 02:46:43 PM UTC 24
Peak memory 281516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3854921753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.a
lert_handler_stress_all_with_rand_reset.3854921753
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/23.alert_handler_entropy.2822938596
Short name T111
Test name
Test status
Simulation time 10915895881 ps
CPU time 1416.79 seconds
Started Sep 11 02:40:13 PM UTC 24
Finished Sep 11 03:04:08 PM UTC 24
Peak memory 299896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822938596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2822938596
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/23.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_alert_accum.706691708
Short name T458
Test name
Test status
Simulation time 1180956471 ps
CPU time 88.18 seconds
Started Sep 11 02:40:05 PM UTC 24
Finished Sep 11 02:41:35 PM UTC 24
Peak memory 269364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706691708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.706691708
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/23.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_intr_timeout.1631506310
Short name T452
Test name
Test status
Simulation time 95976414 ps
CPU time 11.08 seconds
Started Sep 11 02:40:03 PM UTC 24
Finished Sep 11 02:40:16 PM UTC 24
Peak memory 263252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631506310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1631506310
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/23.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg_stub_clk.4273988342
Short name T484
Test name
Test status
Simulation time 4806925952 ps
CPU time 619.44 seconds
Started Sep 11 02:40:27 PM UTC 24
Finished Sep 11 02:50:55 PM UTC 24
Peak memory 279680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273988342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.4273988342
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/23.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/23.alert_handler_ping_timeout.3982996193
Short name T349
Test name
Test status
Simulation time 17560534440 ps
CPU time 775.59 seconds
Started Sep 11 02:40:17 PM UTC 24
Finished Sep 11 02:53:22 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982996193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3982996193
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/23.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_alerts.2835473503
Short name T450
Test name
Test status
Simulation time 1035115716 ps
CPU time 13.53 seconds
Started Sep 11 02:39:37 PM UTC 24
Finished Sep 11 02:39:51 PM UTC 24
Peak memory 263220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835473503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2835473503
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/23.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_classes.3470601297
Short name T453
Test name
Test status
Simulation time 642092325 ps
CPU time 34.87 seconds
Started Sep 11 02:39:53 PM UTC 24
Finished Sep 11 02:40:29 PM UTC 24
Peak memory 262892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470601297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3470601297
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/23.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/23.alert_handler_sig_int_fail.3867640193
Short name T316
Test name
Test status
Simulation time 524671156 ps
CPU time 13.48 seconds
Started Sep 11 02:40:12 PM UTC 24
Finished Sep 11 02:40:26 PM UTC 24
Peak memory 262892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867640193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3867640193
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/23.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/23.alert_handler_smoke.4251927138
Short name T449
Test name
Test status
Simulation time 17835947 ps
CPU time 4.72 seconds
Started Sep 11 02:39:30 PM UTC 24
Finished Sep 11 02:39:35 PM UTC 24
Peak memory 263224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251927138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.4251927138
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/23.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all.3869209797
Short name T687
Test name
Test status
Simulation time 216527986935 ps
CPU time 4379.19 seconds
Started Sep 11 02:40:30 PM UTC 24
Finished Sep 11 03:54:19 PM UTC 24
Peak memory 314840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869209797 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_stress_all.3869209797
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/23.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/24.alert_handler_entropy.1137973278
Short name T563
Test name
Test status
Simulation time 29378991847 ps
CPU time 2016.58 seconds
Started Sep 11 02:41:22 PM UTC 24
Finished Sep 11 03:15:21 PM UTC 24
Peak memory 285484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137973278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1137973278
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/24.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_alert_accum.3636280634
Short name T467
Test name
Test status
Simulation time 2251478357 ps
CPU time 147.59 seconds
Started Sep 11 02:41:09 PM UTC 24
Finished Sep 11 02:43:39 PM UTC 24
Peak memory 269168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636280634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3636280634
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/24.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_intr_timeout.521617773
Short name T456
Test name
Test status
Simulation time 135180936 ps
CPU time 18.01 seconds
Started Sep 11 02:40:49 PM UTC 24
Finished Sep 11 02:41:08 PM UTC 24
Peak memory 263000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521617773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.521617773
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/24.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg.3666770651
Short name T493
Test name
Test status
Simulation time 10556292644 ps
CPU time 756.46 seconds
Started Sep 11 02:41:42 PM UTC 24
Finished Sep 11 02:54:28 PM UTC 24
Peak memory 285500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666770651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3666770651
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/24.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg_stub_clk.540847301
Short name T539
Test name
Test status
Simulation time 54726973003 ps
CPU time 1668.41 seconds
Started Sep 11 02:41:54 PM UTC 24
Finished Sep 11 03:10:02 PM UTC 24
Peak memory 299904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540847301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.540847301
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/24.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_alerts.3551086209
Short name T457
Test name
Test status
Simulation time 4621720373 ps
CPU time 35.49 seconds
Started Sep 11 02:40:44 PM UTC 24
Finished Sep 11 02:41:21 PM UTC 24
Peak memory 269100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551086209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3551086209
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/24.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_classes.1315963575
Short name T459
Test name
Test status
Simulation time 704302155 ps
CPU time 52.68 seconds
Started Sep 11 02:40:47 PM UTC 24
Finished Sep 11 02:41:42 PM UTC 24
Peak memory 269140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315963575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.1315963575
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/24.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/24.alert_handler_sig_int_fail.352494534
Short name T460
Test name
Test status
Simulation time 307789840 ps
CPU time 35.44 seconds
Started Sep 11 02:41:14 PM UTC 24
Finished Sep 11 02:41:51 PM UTC 24
Peak memory 263000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352494534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.352494534
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/24.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all.2211979198
Short name T68
Test name
Test status
Simulation time 21813167990 ps
CPU time 242.93 seconds
Started Sep 11 02:41:54 PM UTC 24
Finished Sep 11 02:46:00 PM UTC 24
Peak memory 269184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211979198 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_stress_all.2211979198
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/24.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all_with_rand_reset.1769632957
Short name T137
Test name
Test status
Simulation time 9646834458 ps
CPU time 302.31 seconds
Started Sep 11 02:41:55 PM UTC 24
Finished Sep 11 02:47:01 PM UTC 24
Peak memory 281844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1769632957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.a
lert_handler_stress_all_with_rand_reset.1769632957
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/25.alert_handler_entropy.483726901
Short name T570
Test name
Test status
Simulation time 91902030263 ps
CPU time 1975.82 seconds
Started Sep 11 02:43:11 PM UTC 24
Finished Sep 11 03:16:31 PM UTC 24
Peak memory 285820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483726901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.483726901
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/25.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_alert_accum.2343718678
Short name T272
Test name
Test status
Simulation time 2975526563 ps
CPU time 114.76 seconds
Started Sep 11 02:42:53 PM UTC 24
Finished Sep 11 02:44:50 PM UTC 24
Peak memory 269096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343718678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2343718678
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/25.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_intr_timeout.4114223326
Short name T465
Test name
Test status
Simulation time 4531911800 ps
CPU time 41.24 seconds
Started Sep 11 02:42:27 PM UTC 24
Finished Sep 11 02:43:10 PM UTC 24
Peak memory 269140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114223326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.4114223326
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/25.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg.2842449464
Short name T375
Test name
Test status
Simulation time 165600752851 ps
CPU time 2393.93 seconds
Started Sep 11 02:43:31 PM UTC 24
Finished Sep 11 03:23:54 PM UTC 24
Peak memory 304608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842449464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2842449464
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/25.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg_stub_clk.2736454738
Short name T567
Test name
Test status
Simulation time 35338993440 ps
CPU time 1926.26 seconds
Started Sep 11 02:43:40 PM UTC 24
Finished Sep 11 03:16:08 PM UTC 24
Peak memory 285824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736454738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2736454738
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/25.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/25.alert_handler_ping_timeout.205617501
Short name T474
Test name
Test status
Simulation time 5447156863 ps
CPU time 268.08 seconds
Started Sep 11 02:43:28 PM UTC 24
Finished Sep 11 02:48:00 PM UTC 24
Peak memory 269440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205617501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.205617501
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/25.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_alerts.3746719991
Short name T466
Test name
Test status
Simulation time 3331809430 ps
CPU time 77.98 seconds
Started Sep 11 02:42:10 PM UTC 24
Finished Sep 11 02:43:30 PM UTC 24
Peak memory 269172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746719991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3746719991
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/25.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_classes.858271462
Short name T322
Test name
Test status
Simulation time 1595308225 ps
CPU time 39.47 seconds
Started Sep 11 02:42:11 PM UTC 24
Finished Sep 11 02:42:52 PM UTC 24
Peak memory 269364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858271462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.858271462
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/25.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/25.alert_handler_sig_int_fail.927264664
Short name T468
Test name
Test status
Simulation time 4485650219 ps
CPU time 83.24 seconds
Started Sep 11 02:43:07 PM UTC 24
Finished Sep 11 02:44:32 PM UTC 24
Peak memory 269464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927264664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.927264664
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/25.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/25.alert_handler_smoke.401225210
Short name T464
Test name
Test status
Simulation time 164222926 ps
CPU time 9.71 seconds
Started Sep 11 02:42:00 PM UTC 24
Finished Sep 11 02:42:11 PM UTC 24
Peak memory 269108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401225210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.401225210
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/25.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/26.alert_handler_entropy.4005570889
Short name T518
Test name
Test status
Simulation time 97367520757 ps
CPU time 999.28 seconds
Started Sep 11 02:46:42 PM UTC 24
Finished Sep 11 03:03:34 PM UTC 24
Peak memory 285816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005570889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.4005570889
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/26.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_alert_accum.2198346964
Short name T469
Test name
Test status
Simulation time 182091402 ps
CPU time 15.45 seconds
Started Sep 11 02:46:16 PM UTC 24
Finished Sep 11 02:46:32 PM UTC 24
Peak memory 269108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198346964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2198346964
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/26.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_intr_timeout.2124114261
Short name T472
Test name
Test status
Simulation time 4102733881 ps
CPU time 86.44 seconds
Started Sep 11 02:46:02 PM UTC 24
Finished Sep 11 02:47:31 PM UTC 24
Peak memory 269464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124114261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.2124114261
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/26.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg_stub_clk.2506487923
Short name T512
Test name
Test status
Simulation time 28678403647 ps
CPU time 843.87 seconds
Started Sep 11 02:47:03 PM UTC 24
Finished Sep 11 03:01:18 PM UTC 24
Peak memory 285568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506487923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2506487923
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/26.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/26.alert_handler_ping_timeout.800668809
Short name T348
Test name
Test status
Simulation time 8333236433 ps
CPU time 291.07 seconds
Started Sep 11 02:46:43 PM UTC 24
Finished Sep 11 02:51:39 PM UTC 24
Peak memory 263232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800668809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.800668809
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/26.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_alerts.589724389
Short name T471
Test name
Test status
Simulation time 825113309 ps
CPU time 77.53 seconds
Started Sep 11 02:45:46 PM UTC 24
Finished Sep 11 02:47:06 PM UTC 24
Peak memory 269424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589724389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.589724389
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/26.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_classes.2281046418
Short name T314
Test name
Test status
Simulation time 580501428 ps
CPU time 42.13 seconds
Started Sep 11 02:46:01 PM UTC 24
Finished Sep 11 02:46:45 PM UTC 24
Peak memory 269036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281046418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2281046418
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/26.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/26.alert_handler_smoke.1340133046
Short name T318
Test name
Test status
Simulation time 93045223 ps
CPU time 15.19 seconds
Started Sep 11 02:45:45 PM UTC 24
Finished Sep 11 02:46:02 PM UTC 24
Peak memory 262968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340133046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1340133046
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/26.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all.3903578415
Short name T611
Test name
Test status
Simulation time 33612057232 ps
CPU time 2432.39 seconds
Started Sep 11 02:47:05 PM UTC 24
Finished Sep 11 03:28:05 PM UTC 24
Peak memory 304600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903578415 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_stress_all.3903578415
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/26.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/27.alert_handler_entropy.650274694
Short name T616
Test name
Test status
Simulation time 36011031420 ps
CPU time 2394.69 seconds
Started Sep 11 02:48:14 PM UTC 24
Finished Sep 11 03:28:36 PM UTC 24
Peak memory 288296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650274694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.650274694
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/27.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_alert_accum.1072005919
Short name T480
Test name
Test status
Simulation time 3968890483 ps
CPU time 93.26 seconds
Started Sep 11 02:48:11 PM UTC 24
Finished Sep 11 02:49:47 PM UTC 24
Peak memory 269428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072005919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1072005919
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/27.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_intr_timeout.965154633
Short name T476
Test name
Test status
Simulation time 62770756 ps
CPU time 9.63 seconds
Started Sep 11 02:48:01 PM UTC 24
Finished Sep 11 02:48:12 PM UTC 24
Peak memory 263256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965154633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.965154633
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/27.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg.984181847
Short name T382
Test name
Test status
Simulation time 192364079768 ps
CPU time 2409.23 seconds
Started Sep 11 02:48:48 PM UTC 24
Finished Sep 11 03:29:23 PM UTC 24
Peak memory 304604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984181847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.984181847
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/27.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg_stub_clk.1642731390
Short name T608
Test name
Test status
Simulation time 32898886551 ps
CPU time 2269.59 seconds
Started Sep 11 02:48:58 PM UTC 24
Finished Sep 11 03:27:13 PM UTC 24
Peak memory 299832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642731390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1642731390
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/27.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/27.alert_handler_ping_timeout.1720878982
Short name T113
Test name
Test status
Simulation time 29914347918 ps
CPU time 447.78 seconds
Started Sep 11 02:48:34 PM UTC 24
Finished Sep 11 02:56:07 PM UTC 24
Peak memory 263296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720878982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1720878982
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_alerts.436977461
Short name T473
Test name
Test status
Simulation time 65382103 ps
CPU time 6.42 seconds
Started Sep 11 02:47:34 PM UTC 24
Finished Sep 11 02:47:42 PM UTC 24
Peak memory 264944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436977461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.436977461
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/27.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_classes.3546911920
Short name T479
Test name
Test status
Simulation time 4677030137 ps
CPU time 80.18 seconds
Started Sep 11 02:47:42 PM UTC 24
Finished Sep 11 02:49:04 PM UTC 24
Peak memory 269460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546911920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3546911920
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/27.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/27.alert_handler_sig_int_fail.2594189078
Short name T277
Test name
Test status
Simulation time 1185171414 ps
CPU time 32.47 seconds
Started Sep 11 02:48:14 PM UTC 24
Finished Sep 11 02:48:47 PM UTC 24
Peak memory 269148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594189078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2594189078
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/27.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/27.alert_handler_smoke.2528826796
Short name T477
Test name
Test status
Simulation time 484503514 ps
CPU time 37.15 seconds
Started Sep 11 02:47:34 PM UTC 24
Finished Sep 11 02:48:13 PM UTC 24
Peak memory 268972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528826796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2528826796
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/27.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all.2625118865
Short name T320
Test name
Test status
Simulation time 115606779410 ps
CPU time 3097.37 seconds
Started Sep 11 02:49:01 PM UTC 24
Finished Sep 11 03:41:17 PM UTC 24
Peak memory 304684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625118865 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_stress_all.2625118865
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/27.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all_with_rand_reset.379128772
Short name T304
Test name
Test status
Simulation time 6708836961 ps
CPU time 203.76 seconds
Started Sep 11 02:49:05 PM UTC 24
Finished Sep 11 02:52:32 PM UTC 24
Peak memory 281524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=379128772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.al
ert_handler_stress_all_with_rand_reset.379128772
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/28.alert_handler_entropy.4267346446
Short name T534
Test name
Test status
Simulation time 15032059477 ps
CPU time 1049.9 seconds
Started Sep 11 02:50:16 PM UTC 24
Finished Sep 11 03:07:59 PM UTC 24
Peak memory 285488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267346446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.4267346446
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/28.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_alert_accum.1958275344
Short name T310
Test name
Test status
Simulation time 877245232 ps
CPU time 85.1 seconds
Started Sep 11 02:50:15 PM UTC 24
Finished Sep 11 02:51:42 PM UTC 24
Peak memory 269036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958275344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1958275344
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/28.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_intr_timeout.3123109750
Short name T483
Test name
Test status
Simulation time 279600178 ps
CPU time 14.37 seconds
Started Sep 11 02:49:58 PM UTC 24
Finished Sep 11 02:50:14 PM UTC 24
Peak memory 262996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123109750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3123109750
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/28.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg.411304209
Short name T538
Test name
Test status
Simulation time 10567999414 ps
CPU time 1118.85 seconds
Started Sep 11 02:50:45 PM UTC 24
Finished Sep 11 03:09:38 PM UTC 24
Peak memory 285488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411304209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.411304209
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/28.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg_stub_clk.2043017470
Short name T621
Test name
Test status
Simulation time 72675305412 ps
CPU time 2285.8 seconds
Started Sep 11 02:50:48 PM UTC 24
Finished Sep 11 03:29:19 PM UTC 24
Peak memory 301884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043017470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2043017470
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/28.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/28.alert_handler_ping_timeout.3758144352
Short name T347
Test name
Test status
Simulation time 33689689522 ps
CPU time 183.08 seconds
Started Sep 11 02:50:36 PM UTC 24
Finished Sep 11 02:53:42 PM UTC 24
Peak memory 263296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758144352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3758144352
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/28.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_alerts.881424670
Short name T482
Test name
Test status
Simulation time 321732559 ps
CPU time 27.67 seconds
Started Sep 11 02:49:43 PM UTC 24
Finished Sep 11 02:50:12 PM UTC 24
Peak memory 269360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881424670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.881424670
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/28.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_classes.923281003
Short name T119
Test name
Test status
Simulation time 2719475738 ps
CPU time 57.5 seconds
Started Sep 11 02:49:47 PM UTC 24
Finished Sep 11 02:50:46 PM UTC 24
Peak memory 269100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923281003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.923281003
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/28.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/28.alert_handler_smoke.1533990197
Short name T481
Test name
Test status
Simulation time 108133581 ps
CPU time 13.38 seconds
Started Sep 11 02:49:43 PM UTC 24
Finished Sep 11 02:49:58 PM UTC 24
Peak memory 263016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533990197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1533990197
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/28.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all.1754736020
Short name T150
Test name
Test status
Simulation time 122616707845 ps
CPU time 1956.91 seconds
Started Sep 11 02:50:56 PM UTC 24
Finished Sep 11 03:23:56 PM UTC 24
Peak memory 299828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754736020 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_stress_all.1754736020
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/28.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/29.alert_handler_entropy.1346807559
Short name T532
Test name
Test status
Simulation time 27887779631 ps
CPU time 852.56 seconds
Started Sep 11 02:52:28 PM UTC 24
Finished Sep 11 03:06:52 PM UTC 24
Peak memory 285488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346807559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.1346807559
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/29.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_alert_accum.2997751132
Short name T496
Test name
Test status
Simulation time 8753227068 ps
CPU time 254.45 seconds
Started Sep 11 02:51:42 PM UTC 24
Finished Sep 11 02:56:01 PM UTC 24
Peak memory 269428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997751132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2997751132
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/29.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_intr_timeout.916292317
Short name T287
Test name
Test status
Simulation time 1442507969 ps
CPU time 59.46 seconds
Started Sep 11 02:51:39 PM UTC 24
Finished Sep 11 02:52:40 PM UTC 24
Peak memory 263000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916292317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.916292317
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/29.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg.1320037730
Short name T381
Test name
Test status
Simulation time 38088362957 ps
CPU time 1796.13 seconds
Started Sep 11 02:52:34 PM UTC 24
Finished Sep 11 03:22:51 PM UTC 24
Peak memory 301876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320037730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1320037730
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/29.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg_stub_clk.957520048
Short name T630
Test name
Test status
Simulation time 40742920229 ps
CPU time 2265.53 seconds
Started Sep 11 02:52:41 PM UTC 24
Finished Sep 11 03:30:53 PM UTC 24
Peak memory 298464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957520048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.957520048
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/29.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/29.alert_handler_ping_timeout.1553032075
Short name T351
Test name
Test status
Simulation time 40023491951 ps
CPU time 493.35 seconds
Started Sep 11 02:52:30 PM UTC 24
Finished Sep 11 03:00:50 PM UTC 24
Peak memory 269108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553032075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1553032075
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/29.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_alerts.1873765554
Short name T487
Test name
Test status
Simulation time 48709736 ps
CPU time 6.29 seconds
Started Sep 11 02:51:20 PM UTC 24
Finished Sep 11 02:51:27 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873765554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1873765554
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/29.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_classes.4258388387
Short name T488
Test name
Test status
Simulation time 173431056 ps
CPU time 11.61 seconds
Started Sep 11 02:51:28 PM UTC 24
Finished Sep 11 02:51:41 PM UTC 24
Peak memory 262996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258388387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.4258388387
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/29.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/29.alert_handler_sig_int_fail.907126791
Short name T295
Test name
Test status
Simulation time 1953298456 ps
CPU time 45.57 seconds
Started Sep 11 02:51:42 PM UTC 24
Finished Sep 11 02:52:29 PM UTC 24
Peak memory 263256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907126791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.907126791
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/29.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/29.alert_handler_smoke.3331481155
Short name T486
Test name
Test status
Simulation time 77926430 ps
CPU time 6.05 seconds
Started Sep 11 02:51:12 PM UTC 24
Finished Sep 11 02:51:19 PM UTC 24
Peak memory 265272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331481155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3331481155
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/29.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all.2973379800
Short name T671
Test name
Test status
Simulation time 50317537562 ps
CPU time 3056.83 seconds
Started Sep 11 02:53:09 PM UTC 24
Finished Sep 11 03:44:39 PM UTC 24
Peak memory 304472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973379800 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_stress_all.2973379800
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/29.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/3.alert_handler_alert_accum_saturation.1693795317
Short name T242
Test name
Test status
Simulation time 16474992 ps
CPU time 3.88 seconds
Started Sep 11 01:59:16 PM UTC 24
Finished Sep 11 01:59:21 PM UTC 24
Peak memory 263492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693795317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1693795317
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy_stress.636097197
Short name T18
Test name
Test status
Simulation time 3098033940 ps
CPU time 43.69 seconds
Started Sep 11 01:59:06 PM UTC 24
Finished Sep 11 01:59:52 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636097197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.636097197
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_alert_accum.2314711325
Short name T52
Test name
Test status
Simulation time 2278780536 ps
CPU time 109.2 seconds
Started Sep 11 01:58:12 PM UTC 24
Finished Sep 11 02:00:03 PM UTC 24
Peak memory 269424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314711325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2314711325
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_intr_timeout.3412770884
Short name T87
Test name
Test status
Simulation time 623830463 ps
CPU time 34.98 seconds
Started Sep 11 01:58:08 PM UTC 24
Finished Sep 11 01:58:44 PM UTC 24
Peak memory 269108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412770884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3412770884
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg_stub_clk.896575147
Short name T302
Test name
Test status
Simulation time 142421146787 ps
CPU time 2157.85 seconds
Started Sep 11 01:58:55 PM UTC 24
Finished Sep 11 02:35:18 PM UTC 24
Peak memory 299824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896575147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.896575147
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/3.alert_handler_ping_timeout.3159543407
Short name T84
Test name
Test status
Simulation time 9401920199 ps
CPU time 348.51 seconds
Started Sep 11 01:58:22 PM UTC 24
Finished Sep 11 02:04:15 PM UTC 24
Peak memory 262960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159543407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3159543407
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_alerts.3954912211
Short name T47
Test name
Test status
Simulation time 85073237 ps
CPU time 6 seconds
Started Sep 11 01:58:00 PM UTC 24
Finished Sep 11 01:58:08 PM UTC 24
Peak memory 252976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954912211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3954912211
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_classes.1883620188
Short name T48
Test name
Test status
Simulation time 465476653 ps
CPU time 14.73 seconds
Started Sep 11 01:58:05 PM UTC 24
Finished Sep 11 01:58:21 PM UTC 24
Peak memory 264940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883620188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1883620188
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/3.alert_handler_sec_cm.1182108316
Short name T40
Test name
Test status
Simulation time 908465859 ps
CPU time 13.08 seconds
Started Sep 11 01:59:31 PM UTC 24
Finished Sep 11 01:59:46 PM UTC 24
Peak memory 295260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182108316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1182108316
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/3.alert_handler_smoke.3432874180
Short name T38
Test name
Test status
Simulation time 422619617 ps
CPU time 20.92 seconds
Started Sep 11 01:57:57 PM UTC 24
Finished Sep 11 01:58:20 PM UTC 24
Peak memory 263220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432874180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3432874180
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all.3848771895
Short name T141
Test name
Test status
Simulation time 69516774832 ps
CPU time 2064.04 seconds
Started Sep 11 01:59:11 PM UTC 24
Finished Sep 11 02:33:58 PM UTC 24
Peak memory 285556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848771895 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_stress_all.3848771895
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/3.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/30.alert_handler_entropy.4143469019
Short name T635
Test name
Test status
Simulation time 36568672585 ps
CPU time 2229.88 seconds
Started Sep 11 02:54:14 PM UTC 24
Finished Sep 11 03:31:51 PM UTC 24
Peak memory 301872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143469019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.4143469019
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/30.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_alert_accum.3051843231
Short name T501
Test name
Test status
Simulation time 11456444493 ps
CPU time 232.82 seconds
Started Sep 11 02:54:06 PM UTC 24
Finished Sep 11 02:58:03 PM UTC 24
Peak memory 269428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051843231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3051843231
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/30.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_intr_timeout.2684640369
Short name T494
Test name
Test status
Simulation time 553409844 ps
CPU time 38.46 seconds
Started Sep 11 02:53:53 PM UTC 24
Finished Sep 11 02:54:33 PM UTC 24
Peak memory 263000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684640369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2684640369
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/30.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg_stub_clk.3237988061
Short name T638
Test name
Test status
Simulation time 80660417398 ps
CPU time 2280.99 seconds
Started Sep 11 02:54:34 PM UTC 24
Finished Sep 11 03:33:00 PM UTC 24
Peak memory 296064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237988061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3237988061
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/30.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/30.alert_handler_ping_timeout.3613288951
Short name T519
Test name
Test status
Simulation time 12294025398 ps
CPU time 564.06 seconds
Started Sep 11 02:54:16 PM UTC 24
Finished Sep 11 03:03:47 PM UTC 24
Peak memory 269376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613288951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3613288951
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/30.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_alerts.3009182908
Short name T492
Test name
Test status
Simulation time 717751721 ps
CPU time 49.65 seconds
Started Sep 11 02:53:23 PM UTC 24
Finished Sep 11 02:54:14 PM UTC 24
Peak memory 263284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009182908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3009182908
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/30.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_classes.615999914
Short name T149
Test name
Test status
Simulation time 7869762300 ps
CPU time 29.15 seconds
Started Sep 11 02:53:43 PM UTC 24
Finished Sep 11 02:54:13 PM UTC 24
Peak memory 269172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615999914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.615999914
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/30.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/30.alert_handler_sig_int_fail.2565023814
Short name T495
Test name
Test status
Simulation time 1081803572 ps
CPU time 30.7 seconds
Started Sep 11 02:54:13 PM UTC 24
Finished Sep 11 02:54:45 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565023814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2565023814
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/30.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/30.alert_handler_smoke.1042282061
Short name T491
Test name
Test status
Simulation time 1059813790 ps
CPU time 50.62 seconds
Started Sep 11 02:53:21 PM UTC 24
Finished Sep 11 02:54:13 PM UTC 24
Peak memory 269112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042282061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1042282061
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/30.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all_with_rand_reset.377837565
Short name T293
Test name
Test status
Simulation time 18230946929 ps
CPU time 348.68 seconds
Started Sep 11 02:54:49 PM UTC 24
Finished Sep 11 03:00:43 PM UTC 24
Peak memory 283576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=377837565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.al
ert_handler_stress_all_with_rand_reset.377837565
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/31.alert_handler_entropy.2783161893
Short name T663
Test name
Test status
Simulation time 190423235131 ps
CPU time 2576.2 seconds
Started Sep 11 02:57:03 PM UTC 24
Finished Sep 11 03:40:29 PM UTC 24
Peak memory 304676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783161893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2783161893
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/31.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_alert_accum.3011023158
Short name T504
Test name
Test status
Simulation time 2399614082 ps
CPU time 128.22 seconds
Started Sep 11 02:56:42 PM UTC 24
Finished Sep 11 02:58:53 PM UTC 24
Peak memory 269092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011023158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3011023158
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/31.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_intr_timeout.2150285688
Short name T292
Test name
Test status
Simulation time 943545920 ps
CPU time 87.53 seconds
Started Sep 11 02:56:42 PM UTC 24
Finished Sep 11 02:58:12 PM UTC 24
Peak memory 263000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150285688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2150285688
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/31.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg.596866843
Short name T367
Test name
Test status
Simulation time 11684106428 ps
CPU time 1079.35 seconds
Started Sep 11 02:58:04 PM UTC 24
Finished Sep 11 03:16:16 PM UTC 24
Peak memory 285488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596866843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.596866843
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/31.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg_stub_clk.1208990054
Short name T553
Test name
Test status
Simulation time 10595831831 ps
CPU time 944.93 seconds
Started Sep 11 02:58:05 PM UTC 24
Finished Sep 11 03:14:02 PM UTC 24
Peak memory 285568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208990054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1208990054
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/31.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/31.alert_handler_ping_timeout.3783412052
Short name T511
Test name
Test status
Simulation time 16285536861 ps
CPU time 167.28 seconds
Started Sep 11 02:58:01 PM UTC 24
Finished Sep 11 03:00:51 PM UTC 24
Peak memory 263040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783412052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3783412052
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/31.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_alerts.4020174439
Short name T498
Test name
Test status
Simulation time 239187057 ps
CPU time 37.96 seconds
Started Sep 11 02:56:02 PM UTC 24
Finished Sep 11 02:56:42 PM UTC 24
Peak memory 262892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020174439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.4020174439
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/31.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_classes.2453607445
Short name T499
Test name
Test status
Simulation time 424419191 ps
CPU time 39.73 seconds
Started Sep 11 02:56:08 PM UTC 24
Finished Sep 11 02:56:50 PM UTC 24
Peak memory 269140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453607445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2453607445
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/31.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/31.alert_handler_sig_int_fail.4097224156
Short name T279
Test name
Test status
Simulation time 703027048 ps
CPU time 71.93 seconds
Started Sep 11 02:56:51 PM UTC 24
Finished Sep 11 02:58:05 PM UTC 24
Peak memory 262892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097224156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.4097224156
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/31.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/31.alert_handler_smoke.4141526106
Short name T497
Test name
Test status
Simulation time 1809208754 ps
CPU time 72.32 seconds
Started Sep 11 02:55:27 PM UTC 24
Finished Sep 11 02:56:41 PM UTC 24
Peak memory 269368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141526106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.4141526106
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/31.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all.2719418146
Short name T269
Test name
Test status
Simulation time 64967293148 ps
CPU time 1484.61 seconds
Started Sep 11 02:58:14 PM UTC 24
Finished Sep 11 03:23:16 PM UTC 24
Peak memory 301940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719418146 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_stress_all.2719418146
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/31.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all_with_rand_reset.241103596
Short name T311
Test name
Test status
Simulation time 5524100148 ps
CPU time 177.72 seconds
Started Sep 11 02:58:14 PM UTC 24
Finished Sep 11 03:01:15 PM UTC 24
Peak memory 279800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=241103596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.al
ert_handler_stress_all_with_rand_reset.241103596
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/32.alert_handler_entropy.468331319
Short name T591
Test name
Test status
Simulation time 23959290853 ps
CPU time 1312.24 seconds
Started Sep 11 02:59:40 PM UTC 24
Finished Sep 11 03:21:47 PM UTC 24
Peak memory 285500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468331319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.468331319
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/32.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_alert_accum.1629019952
Short name T509
Test name
Test status
Simulation time 533908040 ps
CPU time 48.16 seconds
Started Sep 11 02:59:02 PM UTC 24
Finished Sep 11 02:59:52 PM UTC 24
Peak memory 269360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629019952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1629019952
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/32.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_intr_timeout.2254756575
Short name T507
Test name
Test status
Simulation time 346842074 ps
CPU time 40.94 seconds
Started Sep 11 02:58:57 PM UTC 24
Finished Sep 11 02:59:40 PM UTC 24
Peak memory 269400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254756575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2254756575
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/32.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg.89719236
Short name T377
Test name
Test status
Simulation time 26743665519 ps
CPU time 1348.58 seconds
Started Sep 11 02:59:52 PM UTC 24
Finished Sep 11 03:22:37 PM UTC 24
Peak memory 302200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89719236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.89719236
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/32.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg_stub_clk.1898496775
Short name T605
Test name
Test status
Simulation time 17117236923 ps
CPU time 1552.71 seconds
Started Sep 11 03:00:09 PM UTC 24
Finished Sep 11 03:26:21 PM UTC 24
Peak memory 301952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898496775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1898496775
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/32.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/32.alert_handler_ping_timeout.4040791487
Short name T354
Test name
Test status
Simulation time 5030844825 ps
CPU time 212.91 seconds
Started Sep 11 02:59:45 PM UTC 24
Finished Sep 11 03:03:22 PM UTC 24
Peak memory 263360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040791487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.4040791487
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/32.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_alerts.4266084570
Short name T505
Test name
Test status
Simulation time 88257129 ps
CPU time 8.48 seconds
Started Sep 11 02:58:47 PM UTC 24
Finished Sep 11 02:58:56 PM UTC 24
Peak memory 267316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266084570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.4266084570
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/32.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_classes.2221875861
Short name T506
Test name
Test status
Simulation time 163283980 ps
CPU time 20.58 seconds
Started Sep 11 02:58:54 PM UTC 24
Finished Sep 11 02:59:16 PM UTC 24
Peak memory 262924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221875861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2221875861
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/32.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/32.alert_handler_sig_int_fail.4022159943
Short name T508
Test name
Test status
Simulation time 626013463 ps
CPU time 25.91 seconds
Started Sep 11 02:59:17 PM UTC 24
Finished Sep 11 02:59:44 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022159943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.4022159943
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/32.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/32.alert_handler_smoke.3299936160
Short name T510
Test name
Test status
Simulation time 9018329263 ps
CPU time 84.25 seconds
Started Sep 11 02:58:41 PM UTC 24
Finished Sep 11 03:00:07 PM UTC 24
Peak memory 263352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299936160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3299936160
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/32.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all_with_rand_reset.1815112417
Short name T521
Test name
Test status
Simulation time 1260001833 ps
CPU time 199.8 seconds
Started Sep 11 03:00:43 PM UTC 24
Finished Sep 11 03:04:07 PM UTC 24
Peak memory 279480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1815112417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.a
lert_handler_stress_all_with_rand_reset.1815112417
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/33.alert_handler_entropy.3818592693
Short name T620
Test name
Test status
Simulation time 16620021945 ps
CPU time 1621.58 seconds
Started Sep 11 03:01:53 PM UTC 24
Finished Sep 11 03:29:15 PM UTC 24
Peak memory 297772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818592693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3818592693
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/33.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_alert_accum.2097548685
Short name T523
Test name
Test status
Simulation time 9466468226 ps
CPU time 164.3 seconds
Started Sep 11 03:01:44 PM UTC 24
Finished Sep 11 03:04:31 PM UTC 24
Peak memory 263152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097548685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2097548685
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/33.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_intr_timeout.771709517
Short name T515
Test name
Test status
Simulation time 1098572006 ps
CPU time 29.18 seconds
Started Sep 11 03:01:20 PM UTC 24
Finished Sep 11 03:01:51 PM UTC 24
Peak memory 269064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771709517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.771709517
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/33.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg.4109379285
Short name T366
Test name
Test status
Simulation time 45421766628 ps
CPU time 1707.12 seconds
Started Sep 11 03:02:03 PM UTC 24
Finished Sep 11 03:30:51 PM UTC 24
Peak memory 301948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109379285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.4109379285
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/33.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg_stub_clk.575751987
Short name T647
Test name
Test status
Simulation time 122602968646 ps
CPU time 1925.94 seconds
Started Sep 11 03:02:19 PM UTC 24
Finished Sep 11 03:34:46 PM UTC 24
Peak memory 297856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575751987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.575751987
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/33.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/33.alert_handler_ping_timeout.3804484984
Short name T543
Test name
Test status
Simulation time 44363832845 ps
CPU time 500.84 seconds
Started Sep 11 03:02:02 PM UTC 24
Finished Sep 11 03:10:29 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804484984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3804484984
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_alerts.2084783312
Short name T516
Test name
Test status
Simulation time 1393244576 ps
CPU time 68.02 seconds
Started Sep 11 03:00:52 PM UTC 24
Finished Sep 11 03:02:02 PM UTC 24
Peak memory 269428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084783312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2084783312
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/33.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_classes.173577943
Short name T120
Test name
Test status
Simulation time 1595694495 ps
CPU time 75.5 seconds
Started Sep 11 03:01:16 PM UTC 24
Finished Sep 11 03:02:34 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173577943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.173577943
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/33.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/33.alert_handler_sig_int_fail.3491332924
Short name T294
Test name
Test status
Simulation time 2763962993 ps
CPU time 47.78 seconds
Started Sep 11 03:01:52 PM UTC 24
Finished Sep 11 03:02:41 PM UTC 24
Peak memory 269100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491332924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3491332924
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/33.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/33.alert_handler_smoke.3496014017
Short name T513
Test name
Test status
Simulation time 2073455208 ps
CPU time 50.9 seconds
Started Sep 11 03:00:51 PM UTC 24
Finished Sep 11 03:01:43 PM UTC 24
Peak memory 269040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496014017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3496014017
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/33.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all.3456879545
Short name T666
Test name
Test status
Simulation time 207861016632 ps
CPU time 2305.82 seconds
Started Sep 11 03:02:35 PM UTC 24
Finished Sep 11 03:41:29 PM UTC 24
Peak memory 304600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456879545 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_stress_all.3456879545
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/33.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/34.alert_handler_entropy.4207481777
Short name T614
Test name
Test status
Simulation time 62261307059 ps
CPU time 1435.85 seconds
Started Sep 11 03:04:11 PM UTC 24
Finished Sep 11 03:28:22 PM UTC 24
Peak memory 285488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207481777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.4207481777
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/34.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_alert_accum.1824243699
Short name T533
Test name
Test status
Simulation time 3448281050 ps
CPU time 235.03 seconds
Started Sep 11 03:03:56 PM UTC 24
Finished Sep 11 03:07:54 PM UTC 24
Peak memory 269232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824243699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1824243699
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/34.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_intr_timeout.4066645466
Short name T526
Test name
Test status
Simulation time 754365498 ps
CPU time 60.67 seconds
Started Sep 11 03:03:48 PM UTC 24
Finished Sep 11 03:04:50 PM UTC 24
Peak memory 262912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066645466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.4066645466
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/34.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg.2708883396
Short name T369
Test name
Test status
Simulation time 51982415774 ps
CPU time 1584.97 seconds
Started Sep 11 03:04:32 PM UTC 24
Finished Sep 11 03:31:17 PM UTC 24
Peak memory 299828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708883396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2708883396
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/34.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg_stub_clk.2488288192
Short name T673
Test name
Test status
Simulation time 37775262825 ps
CPU time 2420.16 seconds
Started Sep 11 03:04:36 PM UTC 24
Finished Sep 11 03:45:24 PM UTC 24
Peak memory 304684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488288192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.2488288192
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/34.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/34.alert_handler_ping_timeout.3742977517
Short name T345
Test name
Test status
Simulation time 10533991277 ps
CPU time 427.17 seconds
Started Sep 11 03:04:18 PM UTC 24
Finished Sep 11 03:11:31 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742977517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3742977517
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/34.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_alerts.1105476061
Short name T524
Test name
Test status
Simulation time 3025443560 ps
CPU time 67.29 seconds
Started Sep 11 03:03:31 PM UTC 24
Finished Sep 11 03:04:41 PM UTC 24
Peak memory 269172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105476061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1105476061
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/34.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_classes.3336313199
Short name T132
Test name
Test status
Simulation time 1596520774 ps
CPU time 57.09 seconds
Started Sep 11 03:03:36 PM UTC 24
Finished Sep 11 03:04:35 PM UTC 24
Peak memory 269140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336313199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3336313199
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/34.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/34.alert_handler_sig_int_fail.3001367207
Short name T525
Test name
Test status
Simulation time 519805312 ps
CPU time 36.37 seconds
Started Sep 11 03:04:08 PM UTC 24
Finished Sep 11 03:04:46 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001367207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.3001367207
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/34.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/34.alert_handler_smoke.624665554
Short name T517
Test name
Test status
Simulation time 86352993 ps
CPU time 7.35 seconds
Started Sep 11 03:03:22 PM UTC 24
Finished Sep 11 03:03:31 PM UTC 24
Peak memory 262892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624665554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.624665554
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/34.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all.2352017602
Short name T645
Test name
Test status
Simulation time 102007398292 ps
CPU time 1743.39 seconds
Started Sep 11 03:04:41 PM UTC 24
Finished Sep 11 03:34:05 PM UTC 24
Peak memory 299892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352017602 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_stress_all.2352017602
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/34.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all_with_rand_reset.695822705
Short name T121
Test name
Test status
Simulation time 5377315119 ps
CPU time 519.03 seconds
Started Sep 11 03:04:46 PM UTC 24
Finished Sep 11 03:13:32 PM UTC 24
Peak memory 285756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=695822705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.al
ert_handler_stress_all_with_rand_reset.695822705
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/35.alert_handler_entropy.1546659772
Short name T676
Test name
Test status
Simulation time 37097760920 ps
CPU time 2492.02 seconds
Started Sep 11 03:06:22 PM UTC 24
Finished Sep 11 03:48:23 PM UTC 24
Peak memory 302884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546659772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1546659772
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/35.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_alert_accum.4152546563
Short name T535
Test name
Test status
Simulation time 1748400112 ps
CPU time 183.06 seconds
Started Sep 11 03:05:45 PM UTC 24
Finished Sep 11 03:08:52 PM UTC 24
Peak memory 269104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152546563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.4152546563
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/35.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_intr_timeout.1339621268
Short name T530
Test name
Test status
Simulation time 1530720424 ps
CPU time 36.63 seconds
Started Sep 11 03:05:43 PM UTC 24
Finished Sep 11 03:06:21 PM UTC 24
Peak memory 263320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339621268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1339621268
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/35.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg.655460098
Short name T376
Test name
Test status
Simulation time 66810312763 ps
CPU time 1416.02 seconds
Started Sep 11 03:06:54 PM UTC 24
Finished Sep 11 03:30:46 PM UTC 24
Peak memory 302076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655460098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.655460098
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/35.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg_stub_clk.3244482749
Short name T590
Test name
Test status
Simulation time 13926100561 ps
CPU time 812.29 seconds
Started Sep 11 03:07:56 PM UTC 24
Finished Sep 11 03:21:38 PM UTC 24
Peak memory 285564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244482749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3244482749
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/35.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/35.alert_handler_ping_timeout.1692790644
Short name T344
Test name
Test status
Simulation time 1668321712 ps
CPU time 89.98 seconds
Started Sep 11 03:06:38 PM UTC 24
Finished Sep 11 03:08:10 PM UTC 24
Peak memory 267072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692790644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1692790644
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/35.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_alerts.3418196551
Short name T529
Test name
Test status
Simulation time 622969800 ps
CPU time 50.66 seconds
Started Sep 11 03:04:52 PM UTC 24
Finished Sep 11 03:05:44 PM UTC 24
Peak memory 269108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418196551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3418196551
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/35.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_classes.1883636750
Short name T528
Test name
Test status
Simulation time 91123812 ps
CPU time 9.57 seconds
Started Sep 11 03:05:32 PM UTC 24
Finished Sep 11 03:05:43 PM UTC 24
Peak memory 267348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883636750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1883636750
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/35.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/35.alert_handler_sig_int_fail.1118395116
Short name T531
Test name
Test status
Simulation time 1532833073 ps
CPU time 29.71 seconds
Started Sep 11 03:06:06 PM UTC 24
Finished Sep 11 03:06:37 PM UTC 24
Peak memory 262896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118395116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1118395116
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/35.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/35.alert_handler_smoke.3822295537
Short name T527
Test name
Test status
Simulation time 1393252044 ps
CPU time 38.87 seconds
Started Sep 11 03:04:51 PM UTC 24
Finished Sep 11 03:05:31 PM UTC 24
Peak memory 269112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822295537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3822295537
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/35.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all.4100960980
Short name T115
Test name
Test status
Simulation time 62628973427 ps
CPU time 1506.93 seconds
Started Sep 11 03:08:01 PM UTC 24
Finished Sep 11 03:33:26 PM UTC 24
Peak memory 301940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100960980 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_stress_all.4100960980
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/35.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/36.alert_handler_entropy.2285609586
Short name T678
Test name
Test status
Simulation time 84724604812 ps
CPU time 2341.97 seconds
Started Sep 11 03:10:20 PM UTC 24
Finished Sep 11 03:49:49 PM UTC 24
Peak memory 300836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285609586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2285609586
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/36.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_alert_accum.1145216154
Short name T562
Test name
Test status
Simulation time 5953887440 ps
CPU time 312.64 seconds
Started Sep 11 03:10:04 PM UTC 24
Finished Sep 11 03:15:21 PM UTC 24
Peak memory 269100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145216154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1145216154
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/36.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_intr_timeout.2392180763
Short name T545
Test name
Test status
Simulation time 577289176 ps
CPU time 54.19 seconds
Started Sep 11 03:09:41 PM UTC 24
Finished Sep 11 03:10:36 PM UTC 24
Peak memory 269144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392180763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2392180763
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/36.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg.1240350036
Short name T378
Test name
Test status
Simulation time 60992756789 ps
CPU time 860.79 seconds
Started Sep 11 03:10:31 PM UTC 24
Finished Sep 11 03:25:02 PM UTC 24
Peak memory 281396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240350036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1240350036
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/36.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg_stub_clk.765902068
Short name T672
Test name
Test status
Simulation time 67468043049 ps
CPU time 2042.98 seconds
Started Sep 11 03:10:31 PM UTC 24
Finished Sep 11 03:44:57 PM UTC 24
Peak memory 298468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765902068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.765902068
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/36.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/36.alert_handler_ping_timeout.687649299
Short name T564
Test name
Test status
Simulation time 34594235776 ps
CPU time 312.31 seconds
Started Sep 11 03:10:27 PM UTC 24
Finished Sep 11 03:15:44 PM UTC 24
Peak memory 269108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687649299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.687649299
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/36.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_alerts.1819918452
Short name T540
Test name
Test status
Simulation time 1524034719 ps
CPU time 66 seconds
Started Sep 11 03:08:58 PM UTC 24
Finished Sep 11 03:10:06 PM UTC 24
Peak memory 263220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819918452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1819918452
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/36.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_classes.1413585121
Short name T541
Test name
Test status
Simulation time 467008581 ps
CPU time 39.31 seconds
Started Sep 11 03:09:38 PM UTC 24
Finished Sep 11 03:10:19 PM UTC 24
Peak memory 269460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413585121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1413585121
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/36.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/36.alert_handler_sig_int_fail.2013360434
Short name T544
Test name
Test status
Simulation time 137357244 ps
CPU time 22.06 seconds
Started Sep 11 03:10:07 PM UTC 24
Finished Sep 11 03:10:31 PM UTC 24
Peak memory 269108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013360434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2013360434
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/36.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/36.alert_handler_smoke.3004629821
Short name T536
Test name
Test status
Simulation time 28321166 ps
CPU time 3.7 seconds
Started Sep 11 03:08:53 PM UTC 24
Finished Sep 11 03:08:58 PM UTC 24
Peak memory 263224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004629821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3004629821
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/36.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all.518844285
Short name T688
Test name
Test status
Simulation time 96543002262 ps
CPU time 2619.97 seconds
Started Sep 11 03:10:32 PM UTC 24
Finished Sep 11 03:54:41 PM UTC 24
Peak memory 298528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518844285 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_stress_all.518844285
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/36.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all_with_rand_reset.3562755932
Short name T558
Test name
Test status
Simulation time 1944756791 ps
CPU time 242.6 seconds
Started Sep 11 03:10:37 PM UTC 24
Finished Sep 11 03:14:44 PM UTC 24
Peak memory 279604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3562755932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.a
lert_handler_stress_all_with_rand_reset.3562755932
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/37.alert_handler_entropy.3313543292
Short name T683
Test name
Test status
Simulation time 77665988789 ps
CPU time 2396.04 seconds
Started Sep 11 03:12:01 PM UTC 24
Finished Sep 11 03:52:25 PM UTC 24
Peak memory 298532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313543292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3313543292
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/37.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_alert_accum.1711861406
Short name T552
Test name
Test status
Simulation time 1225698766 ps
CPU time 80.18 seconds
Started Sep 11 03:11:32 PM UTC 24
Finished Sep 11 03:12:54 PM UTC 24
Peak memory 269104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711861406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1711861406
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/37.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_intr_timeout.3547542860
Short name T280
Test name
Test status
Simulation time 473086506 ps
CPU time 38.77 seconds
Started Sep 11 03:11:19 PM UTC 24
Finished Sep 11 03:11:59 PM UTC 24
Peak memory 263256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547542860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3547542860
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/37.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg.1271981005
Short name T385
Test name
Test status
Simulation time 51035297657 ps
CPU time 1511.64 seconds
Started Sep 11 03:12:15 PM UTC 24
Finished Sep 11 03:37:45 PM UTC 24
Peak memory 279420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271981005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1271981005
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/37.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg_stub_clk.2483880020
Short name T662
Test name
Test status
Simulation time 29728238829 ps
CPU time 1633.41 seconds
Started Sep 11 03:12:55 PM UTC 24
Finished Sep 11 03:40:27 PM UTC 24
Peak memory 283712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483880020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2483880020
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/37.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/37.alert_handler_ping_timeout.1566678811
Short name T575
Test name
Test status
Simulation time 6852006263 ps
CPU time 379.64 seconds
Started Sep 11 03:12:06 PM UTC 24
Finished Sep 11 03:18:31 PM UTC 24
Peak memory 263040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566678811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1566678811
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_alerts.313544236
Short name T548
Test name
Test status
Simulation time 781826680 ps
CPU time 11.42 seconds
Started Sep 11 03:10:55 PM UTC 24
Finished Sep 11 03:11:08 PM UTC 24
Peak memory 263216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313544236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.313544236
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/37.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_classes.376576805
Short name T549
Test name
Test status
Simulation time 429352380 ps
CPU time 38.25 seconds
Started Sep 11 03:11:08 PM UTC 24
Finished Sep 11 03:11:48 PM UTC 24
Peak memory 262892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376576805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.376576805
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/37.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/37.alert_handler_sig_int_fail.2556383080
Short name T550
Test name
Test status
Simulation time 86815639 ps
CPU time 15.53 seconds
Started Sep 11 03:11:48 PM UTC 24
Finished Sep 11 03:12:05 PM UTC 24
Peak memory 262892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556383080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2556383080
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/37.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/37.alert_handler_smoke.2405623751
Short name T547
Test name
Test status
Simulation time 99212603 ps
CPU time 10.49 seconds
Started Sep 11 03:10:43 PM UTC 24
Finished Sep 11 03:10:55 PM UTC 24
Peak memory 262968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405623751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2405623751
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/37.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/37.alert_handler_stress_all.719934506
Short name T291
Test name
Test status
Simulation time 16507821610 ps
CPU time 1677.84 seconds
Started Sep 11 03:13:04 PM UTC 24
Finished Sep 11 03:41:21 PM UTC 24
Peak memory 301940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719934506 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_stress_all.719934506
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/37.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/38.alert_handler_entropy.1346459730
Short name T698
Test name
Test status
Simulation time 105920452927 ps
CPU time 2860.87 seconds
Started Sep 11 03:14:45 PM UTC 24
Finished Sep 11 04:02:59 PM UTC 24
Peak memory 298456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346459730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.1346459730
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/38.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_alert_accum.2320017438
Short name T571
Test name
Test status
Simulation time 24289816284 ps
CPU time 144.27 seconds
Started Sep 11 03:14:37 PM UTC 24
Finished Sep 11 03:17:04 PM UTC 24
Peak memory 269428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320017438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2320017438
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/38.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_intr_timeout.1956553777
Short name T557
Test name
Test status
Simulation time 397551440 ps
CPU time 15.52 seconds
Started Sep 11 03:14:24 PM UTC 24
Finished Sep 11 03:14:40 PM UTC 24
Peak memory 262896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956553777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1956553777
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/38.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg.3552058181
Short name T358
Test name
Test status
Simulation time 96678273167 ps
CPU time 1870.52 seconds
Started Sep 11 03:14:46 PM UTC 24
Finished Sep 11 03:46:19 PM UTC 24
Peak memory 285564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552058181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3552058181
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/38.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg_stub_clk.1957455061
Short name T692
Test name
Test status
Simulation time 42100587888 ps
CPU time 2529.39 seconds
Started Sep 11 03:15:10 PM UTC 24
Finished Sep 11 03:57:49 PM UTC 24
Peak memory 304612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957455061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1957455061
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/38.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/38.alert_handler_ping_timeout.917882558
Short name T573
Test name
Test status
Simulation time 5166470187 ps
CPU time 188.93 seconds
Started Sep 11 03:14:46 PM UTC 24
Finished Sep 11 03:17:58 PM UTC 24
Peak memory 267060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917882558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.917882558
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_alerts.2297186006
Short name T556
Test name
Test status
Simulation time 65116693 ps
CPU time 6.67 seconds
Started Sep 11 03:14:16 PM UTC 24
Finished Sep 11 03:14:23 PM UTC 24
Peak memory 252724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297186006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2297186006
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/38.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_classes.3277796834
Short name T559
Test name
Test status
Simulation time 3145921054 ps
CPU time 22.72 seconds
Started Sep 11 03:14:22 PM UTC 24
Finished Sep 11 03:14:46 PM UTC 24
Peak memory 263316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277796834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3277796834
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/38.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/38.alert_handler_sig_int_fail.3479701533
Short name T560
Test name
Test status
Simulation time 503141199 ps
CPU time 26.32 seconds
Started Sep 11 03:14:42 PM UTC 24
Finished Sep 11 03:15:09 PM UTC 24
Peak memory 263220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479701533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3479701533
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/38.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/38.alert_handler_smoke.159378654
Short name T555
Test name
Test status
Simulation time 1547359223 ps
CPU time 15.96 seconds
Started Sep 11 03:14:04 PM UTC 24
Finished Sep 11 03:14:21 PM UTC 24
Peak memory 269108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159378654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.159378654
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/38.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all.2304806057
Short name T704
Test name
Test status
Simulation time 131072413831 ps
CPU time 3136.86 seconds
Started Sep 11 03:15:19 PM UTC 24
Finished Sep 11 04:08:14 PM UTC 24
Peak memory 304672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304806057 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_stress_all.2304806057
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/38.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all_with_rand_reset.1867831480
Short name T589
Test name
Test status
Simulation time 9694099954 ps
CPU time 357.2 seconds
Started Sep 11 03:15:24 PM UTC 24
Finished Sep 11 03:21:26 PM UTC 24
Peak memory 285688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1867831480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.a
lert_handler_stress_all_with_rand_reset.1867831480
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/39.alert_handler_entropy.2341077845
Short name T707
Test name
Test status
Simulation time 753151266364 ps
CPU time 3490 seconds
Started Sep 11 03:16:19 PM UTC 24
Finished Sep 11 04:15:07 PM UTC 24
Peak memory 304604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341077845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2341077845
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/39.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_alert_accum.3027186921
Short name T587
Test name
Test status
Simulation time 22650020281 ps
CPU time 280.53 seconds
Started Sep 11 03:16:10 PM UTC 24
Finished Sep 11 03:20:54 PM UTC 24
Peak memory 269096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027186921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3027186921
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/39.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_intr_timeout.1271633187
Short name T572
Test name
Test status
Simulation time 939473182 ps
CPU time 66.28 seconds
Started Sep 11 03:16:01 PM UTC 24
Finished Sep 11 03:17:09 PM UTC 24
Peak memory 262928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271633187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1271633187
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/39.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg.1658818755
Short name T384
Test name
Test status
Simulation time 75760691037 ps
CPU time 1176.02 seconds
Started Sep 11 03:16:33 PM UTC 24
Finished Sep 11 03:36:23 PM UTC 24
Peak memory 285564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658818755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1658818755
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/39.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg_stub_clk.2597226215
Short name T686
Test name
Test status
Simulation time 157743024604 ps
CPU time 2226.97 seconds
Started Sep 11 03:16:33 PM UTC 24
Finished Sep 11 03:54:05 PM UTC 24
Peak memory 300512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597226215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2597226215
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/39.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/39.alert_handler_ping_timeout.110508952
Short name T576
Test name
Test status
Simulation time 4515657211 ps
CPU time 134.04 seconds
Started Sep 11 03:16:28 PM UTC 24
Finished Sep 11 03:18:44 PM UTC 24
Peak memory 269112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110508952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.110508952
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/39.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_alerts.3943848665
Short name T566
Test name
Test status
Simulation time 117003613 ps
CPU time 14.43 seconds
Started Sep 11 03:15:45 PM UTC 24
Finished Sep 11 03:16:01 PM UTC 24
Peak memory 267060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943848665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3943848665
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/39.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_classes.3599258745
Short name T568
Test name
Test status
Simulation time 207309728 ps
CPU time 17.35 seconds
Started Sep 11 03:15:52 PM UTC 24
Finished Sep 11 03:16:11 PM UTC 24
Peak memory 262924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599258745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3599258745
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/39.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/39.alert_handler_smoke.1492593728
Short name T565
Test name
Test status
Simulation time 3594429900 ps
CPU time 26.06 seconds
Started Sep 11 03:15:24 PM UTC 24
Finished Sep 11 03:15:51 PM UTC 24
Peak memory 263032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492593728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.1492593728
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/39.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/4.alert_handler_alert_accum_saturation.2163759062
Short name T116
Test name
Test status
Simulation time 50889375 ps
CPU time 3.99 seconds
Started Sep 11 02:00:44 PM UTC 24
Finished Sep 11 02:00:49 PM UTC 24
Peak memory 263240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163759062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2163759062
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy.4017070961
Short name T461
Test name
Test status
Simulation time 74890847255 ps
CPU time 2476.55 seconds
Started Sep 11 02:00:07 PM UTC 24
Finished Sep 11 02:41:51 PM UTC 24
Peak memory 304604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017070961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.4017070961
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy_stress.242076484
Short name T20
Test name
Test status
Simulation time 261036711 ps
CPU time 23.19 seconds
Started Sep 11 02:00:34 PM UTC 24
Finished Sep 11 02:00:59 PM UTC 24
Peak memory 263292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242076484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.242076484
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_alert_accum.3197139075
Short name T224
Test name
Test status
Simulation time 283572722 ps
CPU time 31.62 seconds
Started Sep 11 01:59:56 PM UTC 24
Finished Sep 11 02:00:29 PM UTC 24
Peak memory 269108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197139075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3197139075
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_intr_timeout.430533971
Short name T223
Test name
Test status
Simulation time 59571703 ps
CPU time 6.6 seconds
Started Sep 11 01:59:52 PM UTC 24
Finished Sep 11 02:00:00 PM UTC 24
Peak memory 262960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430533971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.430533971
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg_stub_clk.1114146719
Short name T315
Test name
Test status
Simulation time 72045339462 ps
CPU time 1832.52 seconds
Started Sep 11 02:00:30 PM UTC 24
Finished Sep 11 02:31:24 PM UTC 24
Peak memory 302204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114146719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1114146719
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_alerts.4079042981
Short name T82
Test name
Test status
Simulation time 6632006109 ps
CPU time 31.73 seconds
Started Sep 11 01:59:44 PM UTC 24
Finished Sep 11 02:00:17 PM UTC 24
Peak memory 269168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079042981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.4079042981
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_classes.1188703624
Short name T51
Test name
Test status
Simulation time 67504330 ps
CPU time 6.93 seconds
Started Sep 11 01:59:47 PM UTC 24
Finished Sep 11 01:59:55 PM UTC 24
Peak memory 252756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188703624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1188703624
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/4.alert_handler_sec_cm.1939618410
Short name T41
Test name
Test status
Simulation time 628492957 ps
CPU time 17.45 seconds
Started Sep 11 02:00:50 PM UTC 24
Finished Sep 11 02:01:09 PM UTC 24
Peak memory 299428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939618410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1939618410
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/4.alert_handler_smoke.2103356950
Short name T241
Test name
Test status
Simulation time 8664583348 ps
CPU time 60.16 seconds
Started Sep 11 01:59:35 PM UTC 24
Finished Sep 11 02:00:37 PM UTC 24
Peak memory 269428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103356950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2103356950
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all.4190986865
Short name T502
Test name
Test status
Simulation time 259994146956 ps
CPU time 3443.26 seconds
Started Sep 11 02:00:38 PM UTC 24
Finished Sep 11 02:58:38 PM UTC 24
Peak memory 304672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190986865 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_stress_all.4190986865
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/40.alert_handler_entropy.3765230597
Short name T695
Test name
Test status
Simulation time 134386926279 ps
CPU time 2362.16 seconds
Started Sep 11 03:18:45 PM UTC 24
Finished Sep 11 03:58:35 PM UTC 24
Peak memory 304932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765230597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3765230597
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/40.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_alert_accum.2582984054
Short name T586
Test name
Test status
Simulation time 3672454079 ps
CPU time 133.62 seconds
Started Sep 11 03:18:31 PM UTC 24
Finished Sep 11 03:20:47 PM UTC 24
Peak memory 269096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582984054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2582984054
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/40.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_intr_timeout.2198884244
Short name T579
Test name
Test status
Simulation time 2134650374 ps
CPU time 50.51 seconds
Started Sep 11 03:18:15 PM UTC 24
Finished Sep 11 03:19:07 PM UTC 24
Peak memory 263256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198884244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2198884244
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/40.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg.337570989
Short name T705
Test name
Test status
Simulation time 95164734816 ps
CPU time 2975.89 seconds
Started Sep 11 03:19:06 PM UTC 24
Finished Sep 11 04:09:17 PM UTC 24
Peak memory 300584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337570989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.337570989
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/40.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg_stub_clk.3277132843
Short name T685
Test name
Test status
Simulation time 41386325272 ps
CPU time 2065.82 seconds
Started Sep 11 03:19:08 PM UTC 24
Finished Sep 11 03:53:56 PM UTC 24
Peak memory 298112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277132843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3277132843
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/40.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/40.alert_handler_ping_timeout.2207576192
Short name T592
Test name
Test status
Simulation time 21845993647 ps
CPU time 187.03 seconds
Started Sep 11 03:18:49 PM UTC 24
Finished Sep 11 03:21:59 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207576192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2207576192
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/40.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_alerts.4276688784
Short name T574
Test name
Test status
Simulation time 666939825 ps
CPU time 41.54 seconds
Started Sep 11 03:17:47 PM UTC 24
Finished Sep 11 03:18:30 PM UTC 24
Peak memory 269040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276688784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.4276688784
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/40.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_classes.3778870913
Short name T577
Test name
Test status
Simulation time 2032344168 ps
CPU time 47.21 seconds
Started Sep 11 03:17:59 PM UTC 24
Finished Sep 11 03:18:48 PM UTC 24
Peak memory 262924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778870913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3778870913
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/40.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/40.alert_handler_sig_int_fail.3983767644
Short name T581
Test name
Test status
Simulation time 681289122 ps
CPU time 55.16 seconds
Started Sep 11 03:18:32 PM UTC 24
Finished Sep 11 03:19:29 PM UTC 24
Peak memory 262892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983767644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3983767644
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/40.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/40.alert_handler_smoke.1642154173
Short name T580
Test name
Test status
Simulation time 1108590569 ps
CPU time 97.08 seconds
Started Sep 11 03:17:45 PM UTC 24
Finished Sep 11 03:19:24 PM UTC 24
Peak memory 269040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642154173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1642154173
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/40.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all.387034416
Short name T690
Test name
Test status
Simulation time 243443145745 ps
CPU time 2205.29 seconds
Started Sep 11 03:19:19 PM UTC 24
Finished Sep 11 03:56:28 PM UTC 24
Peak memory 297776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387034416 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_stress_all.387034416
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/40.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/41.alert_handler_entropy.3968126280
Short name T644
Test name
Test status
Simulation time 26125965738 ps
CPU time 780.82 seconds
Started Sep 11 03:20:48 PM UTC 24
Finished Sep 11 03:33:59 PM UTC 24
Peak memory 285816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968126280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3968126280
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/41.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_alert_accum.1904012598
Short name T600
Test name
Test status
Simulation time 17303301544 ps
CPU time 280.81 seconds
Started Sep 11 03:20:27 PM UTC 24
Finished Sep 11 03:25:12 PM UTC 24
Peak memory 269168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904012598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1904012598
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/41.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_intr_timeout.2149179453
Short name T585
Test name
Test status
Simulation time 102297354 ps
CPU time 20.2 seconds
Started Sep 11 03:20:14 PM UTC 24
Finished Sep 11 03:20:36 PM UTC 24
Peak memory 269144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149179453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2149179453
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/41.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg.1639440194
Short name T674
Test name
Test status
Simulation time 25350699870 ps
CPU time 1468.94 seconds
Started Sep 11 03:21:08 PM UTC 24
Finished Sep 11 03:45:55 PM UTC 24
Peak memory 296060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639440194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1639440194
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/41.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg_stub_clk.1560549314
Short name T699
Test name
Test status
Simulation time 44062961304 ps
CPU time 2572.24 seconds
Started Sep 11 03:21:20 PM UTC 24
Finished Sep 11 04:04:41 PM UTC 24
Peak memory 298536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560549314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1560549314
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/41.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/41.alert_handler_ping_timeout.2916870769
Short name T622
Test name
Test status
Simulation time 50449337575 ps
CPU time 505.85 seconds
Started Sep 11 03:20:55 PM UTC 24
Finished Sep 11 03:29:27 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916870769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2916870769
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/41.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_alerts.2491896966
Short name T584
Test name
Test status
Simulation time 1849984447 ps
CPU time 45.04 seconds
Started Sep 11 03:19:40 PM UTC 24
Finished Sep 11 03:20:27 PM UTC 24
Peak memory 269364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491896966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2491896966
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/41.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_classes.3950927487
Short name T583
Test name
Test status
Simulation time 222157782 ps
CPU time 20.27 seconds
Started Sep 11 03:19:52 PM UTC 24
Finished Sep 11 03:20:14 PM UTC 24
Peak memory 262924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950927487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3950927487
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/41.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/41.alert_handler_sig_int_fail.1956040510
Short name T588
Test name
Test status
Simulation time 309498449 ps
CPU time 41.41 seconds
Started Sep 11 03:20:37 PM UTC 24
Finished Sep 11 03:21:19 PM UTC 24
Peak memory 262892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956040510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1956040510
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/41.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/41.alert_handler_smoke.260599548
Short name T582
Test name
Test status
Simulation time 522214191 ps
CPU time 19.84 seconds
Started Sep 11 03:19:30 PM UTC 24
Finished Sep 11 03:19:51 PM UTC 24
Peak memory 269108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260599548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.260599548
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/41.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all.3659560404
Short name T696
Test name
Test status
Simulation time 160948534815 ps
CPU time 2284.58 seconds
Started Sep 11 03:21:28 PM UTC 24
Finished Sep 11 03:59:58 PM UTC 24
Peak memory 304992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659560404 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_stress_all.3659560404
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/41.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all_with_rand_reset.3791125988
Short name T606
Test name
Test status
Simulation time 2062407721 ps
CPU time 308.25 seconds
Started Sep 11 03:21:40 PM UTC 24
Finished Sep 11 03:26:53 PM UTC 24
Peak memory 281452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3791125988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.a
lert_handler_stress_all_with_rand_reset.3791125988
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/42.alert_handler_entropy.1576445804
Short name T706
Test name
Test status
Simulation time 51309184457 ps
CPU time 2874.74 seconds
Started Sep 11 03:23:18 PM UTC 24
Finished Sep 11 04:11:44 PM UTC 24
Peak memory 304600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576445804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1576445804
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/42.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_alert_accum.1775081637
Short name T612
Test name
Test status
Simulation time 4995722218 ps
CPU time 308.32 seconds
Started Sep 11 03:22:56 PM UTC 24
Finished Sep 11 03:28:09 PM UTC 24
Peak memory 269092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775081637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1775081637
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/42.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_intr_timeout.2090389629
Short name T597
Test name
Test status
Simulation time 3366156269 ps
CPU time 59.86 seconds
Started Sep 11 03:22:53 PM UTC 24
Finished Sep 11 03:23:55 PM UTC 24
Peak memory 263064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090389629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2090389629
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/42.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg_stub_clk.2502469990
Short name T710
Test name
Test status
Simulation time 291638593369 ps
CPU time 3166.28 seconds
Started Sep 11 03:23:56 PM UTC 24
Finished Sep 11 04:17:18 PM UTC 24
Peak memory 298540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502469990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2502469990
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/42.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/42.alert_handler_ping_timeout.731947033
Short name T607
Test name
Test status
Simulation time 9488046098 ps
CPU time 370.79 seconds
Started Sep 11 03:23:28 PM UTC 24
Finished Sep 11 03:29:44 PM UTC 24
Peak memory 262968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731947033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.731947033
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/42.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_alerts.1628732401
Short name T593
Test name
Test status
Simulation time 932442551 ps
CPU time 53.57 seconds
Started Sep 11 03:22:00 PM UTC 24
Finished Sep 11 03:22:55 PM UTC 24
Peak memory 269364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628732401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1628732401
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/42.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_classes.4029224317
Short name T595
Test name
Test status
Simulation time 14454671230 ps
CPU time 46.27 seconds
Started Sep 11 03:22:39 PM UTC 24
Finished Sep 11 03:23:27 PM UTC 24
Peak memory 269100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029224317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.4029224317
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/42.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/42.alert_handler_sig_int_fail.1306068013
Short name T596
Test name
Test status
Simulation time 279658264 ps
CPU time 25.23 seconds
Started Sep 11 03:23:11 PM UTC 24
Finished Sep 11 03:23:37 PM UTC 24
Peak memory 263284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306068013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1306068013
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/42.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/42.alert_handler_smoke.2019904023
Short name T594
Test name
Test status
Simulation time 4468573741 ps
CPU time 79.2 seconds
Started Sep 11 03:21:49 PM UTC 24
Finished Sep 11 03:23:10 PM UTC 24
Peak memory 269104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019904023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2019904023
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/42.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all.2610718901
Short name T682
Test name
Test status
Simulation time 61963322274 ps
CPU time 1632.1 seconds
Started Sep 11 03:23:56 PM UTC 24
Finished Sep 11 03:51:29 PM UTC 24
Peak memory 312108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610718901 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_stress_all.2610718901
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/42.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all_with_rand_reset.554332576
Short name T634
Test name
Test status
Simulation time 6802997465 ps
CPU time 461.38 seconds
Started Sep 11 03:23:59 PM UTC 24
Finished Sep 11 03:31:47 PM UTC 24
Peak memory 279800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=554332576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.al
ert_handler_stress_all_with_rand_reset.554332576
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/43.alert_handler_entropy.2562929087
Short name T689
Test name
Test status
Simulation time 20002181735 ps
CPU time 1731.92 seconds
Started Sep 11 03:25:30 PM UTC 24
Finished Sep 11 03:54:43 PM UTC 24
Peak memory 301868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562929087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2562929087
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/43.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_alert_accum.976598116
Short name T604
Test name
Test status
Simulation time 484247012 ps
CPU time 52.06 seconds
Started Sep 11 03:25:24 PM UTC 24
Finished Sep 11 03:26:18 PM UTC 24
Peak memory 269140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976598116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.976598116
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/43.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_intr_timeout.1607977768
Short name T603
Test name
Test status
Simulation time 477283638 ps
CPU time 18.34 seconds
Started Sep 11 03:25:14 PM UTC 24
Finished Sep 11 03:25:33 PM UTC 24
Peak memory 269144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607977768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1607977768
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/43.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg_stub_clk.741016453
Short name T665
Test name
Test status
Simulation time 20313254775 ps
CPU time 885.15 seconds
Started Sep 11 03:26:23 PM UTC 24
Finished Sep 11 03:41:19 PM UTC 24
Peak memory 285492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741016453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.741016453
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/43.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/43.alert_handler_ping_timeout.1165086679
Short name T625
Test name
Test status
Simulation time 6758995485 ps
CPU time 270.03 seconds
Started Sep 11 03:25:34 PM UTC 24
Finished Sep 11 03:30:08 PM UTC 24
Peak memory 269184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165086679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1165086679
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/43.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_alerts.3903567067
Short name T602
Test name
Test status
Simulation time 448513129 ps
CPU time 41.67 seconds
Started Sep 11 03:24:46 PM UTC 24
Finished Sep 11 03:25:29 PM UTC 24
Peak memory 269364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903567067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3903567067
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/43.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_classes.444905003
Short name T601
Test name
Test status
Simulation time 763422505 ps
CPU time 18.78 seconds
Started Sep 11 03:25:03 PM UTC 24
Finished Sep 11 03:25:23 PM UTC 24
Peak memory 269108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444905003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.444905003
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/43.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/43.alert_handler_sig_int_fail.1417363325
Short name T151
Test name
Test status
Simulation time 3708266206 ps
CPU time 71.73 seconds
Started Sep 11 03:25:24 PM UTC 24
Finished Sep 11 03:26:38 PM UTC 24
Peak memory 263028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417363325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1417363325
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/43.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/43.alert_handler_smoke.3720194013
Short name T599
Test name
Test status
Simulation time 2539512586 ps
CPU time 40.33 seconds
Started Sep 11 03:24:03 PM UTC 24
Finished Sep 11 03:24:45 PM UTC 24
Peak memory 269104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720194013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3720194013
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/43.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all.1301826087
Short name T609
Test name
Test status
Simulation time 1614642337 ps
CPU time 44.73 seconds
Started Sep 11 03:26:38 PM UTC 24
Finished Sep 11 03:27:25 PM UTC 24
Peak memory 269036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301826087 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_stress_all.1301826087
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/43.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/44.alert_handler_entropy.681522864
Short name T667
Test name
Test status
Simulation time 12510422879 ps
CPU time 781.39 seconds
Started Sep 11 03:28:21 PM UTC 24
Finished Sep 11 03:41:33 PM UTC 24
Peak memory 285820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681522864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.681522864
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/44.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_alert_accum.1289236022
Short name T618
Test name
Test status
Simulation time 1084578498 ps
CPU time 44 seconds
Started Sep 11 03:28:08 PM UTC 24
Finished Sep 11 03:28:53 PM UTC 24
Peak memory 269104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289236022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1289236022
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/44.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_intr_timeout.2303061462
Short name T619
Test name
Test status
Simulation time 653863689 ps
CPU time 55.21 seconds
Started Sep 11 03:27:59 PM UTC 24
Finished Sep 11 03:28:56 PM UTC 24
Peak memory 262996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303061462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2303061462
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/44.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg.2936250688
Short name T373
Test name
Test status
Simulation time 181174941930 ps
CPU time 2147.05 seconds
Started Sep 11 03:28:23 PM UTC 24
Finished Sep 11 04:04:34 PM UTC 24
Peak memory 285496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936250688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2936250688
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/44.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg_stub_clk.1683360861
Short name T319
Test name
Test status
Simulation time 153047836025 ps
CPU time 2440.2 seconds
Started Sep 11 03:28:39 PM UTC 24
Finished Sep 11 04:09:46 PM UTC 24
Peak memory 304608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683360861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1683360861
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/44.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/44.alert_handler_ping_timeout.692831396
Short name T643
Test name
Test status
Simulation time 8076148448 ps
CPU time 317.71 seconds
Started Sep 11 03:28:23 PM UTC 24
Finished Sep 11 03:33:45 PM UTC 24
Peak memory 263296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692831396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.692831396
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/44.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_alerts.3407602763
Short name T610
Test name
Test status
Simulation time 1342806637 ps
CPU time 40.37 seconds
Started Sep 11 03:27:16 PM UTC 24
Finished Sep 11 03:27:58 PM UTC 24
Peak memory 263220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407602763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3407602763
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/44.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_classes.3708224700
Short name T613
Test name
Test status
Simulation time 1975198883 ps
CPU time 53.12 seconds
Started Sep 11 03:27:26 PM UTC 24
Finished Sep 11 03:28:21 PM UTC 24
Peak memory 262892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708224700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3708224700
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/44.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/44.alert_handler_sig_int_fail.1511098149
Short name T617
Test name
Test status
Simulation time 304625829 ps
CPU time 29.09 seconds
Started Sep 11 03:28:10 PM UTC 24
Finished Sep 11 03:28:40 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511098149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1511098149
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/44.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/44.alert_handler_smoke.1738912449
Short name T615
Test name
Test status
Simulation time 5347360907 ps
CPU time 64.16 seconds
Started Sep 11 03:27:16 PM UTC 24
Finished Sep 11 03:28:22 PM UTC 24
Peak memory 269104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738912449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1738912449
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/44.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all.3278128617
Short name T283
Test name
Test status
Simulation time 3306854299 ps
CPU time 90.29 seconds
Started Sep 11 03:28:42 PM UTC 24
Finished Sep 11 03:30:14 PM UTC 24
Peak memory 269184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278128617 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_stress_all.3278128617
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/44.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all_with_rand_reset.338006845
Short name T262
Test name
Test status
Simulation time 2840781457 ps
CPU time 237.96 seconds
Started Sep 11 03:28:54 PM UTC 24
Finished Sep 11 03:32:56 PM UTC 24
Peak memory 279736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=338006845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.al
ert_handler_stress_all_with_rand_reset.338006845
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/45.alert_handler_entropy.4224833527
Short name T677
Test name
Test status
Simulation time 52712456533 ps
CPU time 1186.62 seconds
Started Sep 11 03:29:34 PM UTC 24
Finished Sep 11 03:49:35 PM UTC 24
Peak memory 296056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224833527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.4224833527
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/45.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_alert_accum.3791428440
Short name T653
Test name
Test status
Simulation time 15592799692 ps
CPU time 368.33 seconds
Started Sep 11 03:29:27 PM UTC 24
Finished Sep 11 03:35:40 PM UTC 24
Peak memory 269092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791428440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3791428440
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/45.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_intr_timeout.2535212892
Short name T627
Test name
Test status
Simulation time 3378057372 ps
CPU time 55.8 seconds
Started Sep 11 03:29:27 PM UTC 24
Finished Sep 11 03:30:24 PM UTC 24
Peak memory 263064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535212892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2535212892
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/45.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg.1081656863
Short name T684
Test name
Test status
Simulation time 24498277188 ps
CPU time 1372.53 seconds
Started Sep 11 03:29:44 PM UTC 24
Finished Sep 11 03:52:52 PM UTC 24
Peak memory 285564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081656863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.1081656863
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/45.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg_stub_clk.3962923736
Short name T681
Test name
Test status
Simulation time 80479133928 ps
CPU time 1257.08 seconds
Started Sep 11 03:30:08 PM UTC 24
Finished Sep 11 03:51:21 PM UTC 24
Peak memory 285824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962923736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3962923736
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/45.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/45.alert_handler_ping_timeout.4288837634
Short name T355
Test name
Test status
Simulation time 30052789778 ps
CPU time 409.24 seconds
Started Sep 11 03:29:43 PM UTC 24
Finished Sep 11 03:36:38 PM UTC 24
Peak memory 263292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288837634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.4288837634
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/45.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_alerts.2156418245
Short name T626
Test name
Test status
Simulation time 601393048 ps
CPU time 53.35 seconds
Started Sep 11 03:29:17 PM UTC 24
Finished Sep 11 03:30:12 PM UTC 24
Peak memory 269036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156418245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2156418245
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/45.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_classes.3261952187
Short name T629
Test name
Test status
Simulation time 1048031947 ps
CPU time 89.8 seconds
Started Sep 11 03:29:21 PM UTC 24
Finished Sep 11 03:30:53 PM UTC 24
Peak memory 269396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261952187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3261952187
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/45.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/45.alert_handler_sig_int_fail.3162899773
Short name T624
Test name
Test status
Simulation time 212171239 ps
CPU time 12.84 seconds
Started Sep 11 03:29:28 PM UTC 24
Finished Sep 11 03:29:42 PM UTC 24
Peak memory 267356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162899773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3162899773
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/45.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/45.alert_handler_smoke.475148057
Short name T623
Test name
Test status
Simulation time 497878717 ps
CPU time 34.9 seconds
Started Sep 11 03:28:57 PM UTC 24
Finished Sep 11 03:29:33 PM UTC 24
Peak memory 269044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475148057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.475148057
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/45.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/45.alert_handler_stress_all.213413026
Short name T296
Test name
Test status
Simulation time 215709817966 ps
CPU time 3141.6 seconds
Started Sep 11 03:30:14 PM UTC 24
Finished Sep 11 04:23:10 PM UTC 24
Peak memory 304672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213413026 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_stress_all.213413026
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/45.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/46.alert_handler_entropy.3729301751
Short name T691
Test name
Test status
Simulation time 96670406775 ps
CPU time 1565.01 seconds
Started Sep 11 03:31:09 PM UTC 24
Finished Sep 11 03:57:32 PM UTC 24
Peak memory 285488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729301751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3729301751
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/46.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_alert_accum.2037422637
Short name T642
Test name
Test status
Simulation time 5833550385 ps
CPU time 164.26 seconds
Started Sep 11 03:30:54 PM UTC 24
Finished Sep 11 03:33:41 PM UTC 24
Peak memory 269168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037422637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2037422637
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/46.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_intr_timeout.2497782564
Short name T631
Test name
Test status
Simulation time 1273815743 ps
CPU time 12.67 seconds
Started Sep 11 03:30:54 PM UTC 24
Finished Sep 11 03:31:08 PM UTC 24
Peak memory 262896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497782564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2497782564
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/46.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg.1293761229
Short name T703
Test name
Test status
Simulation time 36401984113 ps
CPU time 2168.64 seconds
Started Sep 11 03:31:20 PM UTC 24
Finished Sep 11 04:07:53 PM UTC 24
Peak memory 299904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293761229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1293761229
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/46.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg_stub_clk.2646931594
Short name T694
Test name
Test status
Simulation time 118472256206 ps
CPU time 1600.52 seconds
Started Sep 11 03:31:22 PM UTC 24
Finished Sep 11 03:58:20 PM UTC 24
Peak memory 285496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646931594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2646931594
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/46.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/46.alert_handler_ping_timeout.2709106799
Short name T664
Test name
Test status
Simulation time 14437383920 ps
CPU time 557.34 seconds
Started Sep 11 03:31:16 PM UTC 24
Finished Sep 11 03:40:40 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709106799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2709106799
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_alerts.825914656
Short name T632
Test name
Test status
Simulation time 1407085269 ps
CPU time 30.46 seconds
Started Sep 11 03:30:49 PM UTC 24
Finished Sep 11 03:31:21 PM UTC 24
Peak memory 262888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825914656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.825914656
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/46.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_classes.1079810622
Short name T633
Test name
Test status
Simulation time 2329990715 ps
CPU time 31.68 seconds
Started Sep 11 03:30:50 PM UTC 24
Finished Sep 11 03:31:23 PM UTC 24
Peak memory 269460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079810622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1079810622
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/46.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/46.alert_handler_smoke.6797807
Short name T628
Test name
Test status
Simulation time 131706560 ps
CPU time 22.77 seconds
Started Sep 11 03:30:25 PM UTC 24
Finished Sep 11 03:30:49 PM UTC 24
Peak memory 269432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6797807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.6797807
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/46.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all.660373824
Short name T709
Test name
Test status
Simulation time 72313792375 ps
CPU time 2643.66 seconds
Started Sep 11 03:31:24 PM UTC 24
Finished Sep 11 04:15:58 PM UTC 24
Peak memory 304600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660373824 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_stress_all.660373824
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/46.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all_with_rand_reset.295618123
Short name T661
Test name
Test status
Simulation time 38302742944 ps
CPU time 392.47 seconds
Started Sep 11 03:31:39 PM UTC 24
Finished Sep 11 03:38:17 PM UTC 24
Peak memory 302004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=295618123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.al
ert_handler_stress_all_with_rand_reset.295618123
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/47.alert_handler_entropy.1707418299
Short name T679
Test name
Test status
Simulation time 37253158573 ps
CPU time 1041.86 seconds
Started Sep 11 03:33:08 PM UTC 24
Finished Sep 11 03:50:42 PM UTC 24
Peak memory 295800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707418299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1707418299
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/47.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_alert_accum.945766208
Short name T649
Test name
Test status
Simulation time 2302153543 ps
CPU time 129.41 seconds
Started Sep 11 03:32:57 PM UTC 24
Finished Sep 11 03:35:09 PM UTC 24
Peak memory 269100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945766208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.945766208
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/47.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_intr_timeout.3826662868
Short name T639
Test name
Test status
Simulation time 371289541 ps
CPU time 49.89 seconds
Started Sep 11 03:32:15 PM UTC 24
Finished Sep 11 03:33:07 PM UTC 24
Peak memory 262936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826662868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3826662868
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/47.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg.2269252340
Short name T359
Test name
Test status
Simulation time 26976468932 ps
CPU time 1547.37 seconds
Started Sep 11 03:33:25 PM UTC 24
Finished Sep 11 03:59:30 PM UTC 24
Peak memory 295736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269252340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2269252340
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/47.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg_stub_clk.3618432112
Short name T680
Test name
Test status
Simulation time 24558407434 ps
CPU time 1038.06 seconds
Started Sep 11 03:33:29 PM UTC 24
Finished Sep 11 03:51:00 PM UTC 24
Peak memory 301884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618432112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3618432112
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/47.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/47.alert_handler_ping_timeout.324334846
Short name T669
Test name
Test status
Simulation time 15769357633 ps
CPU time 553.84 seconds
Started Sep 11 03:33:16 PM UTC 24
Finished Sep 11 03:42:36 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324334846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.324334846
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/47.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_alerts.2833948132
Short name T637
Test name
Test status
Simulation time 334804826 ps
CPU time 20.3 seconds
Started Sep 11 03:31:53 PM UTC 24
Finished Sep 11 03:32:15 PM UTC 24
Peak memory 267060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833948132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2833948132
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/47.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_classes.779061555
Short name T640
Test name
Test status
Simulation time 3133934299 ps
CPU time 71.05 seconds
Started Sep 11 03:32:02 PM UTC 24
Finished Sep 11 03:33:15 PM UTC 24
Peak memory 262956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779061555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.779061555
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/47.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/47.alert_handler_sig_int_fail.3608299036
Short name T641
Test name
Test status
Simulation time 163204570 ps
CPU time 20.6 seconds
Started Sep 11 03:33:02 PM UTC 24
Finished Sep 11 03:33:24 PM UTC 24
Peak memory 269108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608299036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3608299036
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/47.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/47.alert_handler_smoke.3473657407
Short name T636
Test name
Test status
Simulation time 362884610 ps
CPU time 11.71 seconds
Started Sep 11 03:31:48 PM UTC 24
Finished Sep 11 03:32:01 PM UTC 24
Peak memory 265336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473657407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3473657407
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/47.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/48.alert_handler_entropy.3685573329
Short name T702
Test name
Test status
Simulation time 64265943158 ps
CPU time 1793.38 seconds
Started Sep 11 03:35:10 PM UTC 24
Finished Sep 11 04:05:24 PM UTC 24
Peak memory 285816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685573329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3685573329
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/48.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_alert_accum.1568989556
Short name T659
Test name
Test status
Simulation time 8877894623 ps
CPU time 172.66 seconds
Started Sep 11 03:34:48 PM UTC 24
Finished Sep 11 03:37:44 PM UTC 24
Peak memory 262948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568989556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1568989556
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/48.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_intr_timeout.3269824756
Short name T648
Test name
Test status
Simulation time 983188768 ps
CPU time 13.38 seconds
Started Sep 11 03:34:44 PM UTC 24
Finished Sep 11 03:34:58 PM UTC 24
Peak memory 267000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269824756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.3269824756
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/48.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg.3617388950
Short name T697
Test name
Test status
Simulation time 70931627642 ps
CPU time 1537.29 seconds
Started Sep 11 03:35:23 PM UTC 24
Finished Sep 11 04:01:19 PM UTC 24
Peak memory 301876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617388950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3617388950
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/48.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg_stub_clk.3846497717
Short name T675
Test name
Test status
Simulation time 27255908881 ps
CPU time 701.71 seconds
Started Sep 11 03:35:25 PM UTC 24
Finished Sep 11 03:47:15 PM UTC 24
Peak memory 285568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846497717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3846497717
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/48.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/48.alert_handler_ping_timeout.1107940947
Short name T657
Test name
Test status
Simulation time 5922105140 ps
CPU time 102.39 seconds
Started Sep 11 03:35:20 PM UTC 24
Finished Sep 11 03:37:04 PM UTC 24
Peak memory 263356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107940947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1107940947
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/48.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_alerts.918419749
Short name T650
Test name
Test status
Simulation time 1105587651 ps
CPU time 69.16 seconds
Started Sep 11 03:34:08 PM UTC 24
Finished Sep 11 03:35:18 PM UTC 24
Peak memory 263216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918419749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.918419749
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/48.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_classes.420483176
Short name T646
Test name
Test status
Simulation time 144071115 ps
CPU time 10.41 seconds
Started Sep 11 03:34:32 PM UTC 24
Finished Sep 11 03:34:43 PM UTC 24
Peak memory 264944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420483176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.420483176
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/48.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/48.alert_handler_sig_int_fail.1805586968
Short name T652
Test name
Test status
Simulation time 268119765 ps
CPU time 23.68 seconds
Started Sep 11 03:34:59 PM UTC 24
Finished Sep 11 03:35:24 PM UTC 24
Peak memory 262892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805586968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1805586968
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/48.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/48.alert_handler_smoke.4064991829
Short name T651
Test name
Test status
Simulation time 981532721 ps
CPU time 78.66 seconds
Started Sep 11 03:34:01 PM UTC 24
Finished Sep 11 03:35:22 PM UTC 24
Peak memory 269368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064991829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.4064991829
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/48.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all.1074495245
Short name T708
Test name
Test status
Simulation time 63909553823 ps
CPU time 2374.88 seconds
Started Sep 11 03:35:40 PM UTC 24
Finished Sep 11 04:15:41 PM UTC 24
Peak memory 304736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074495245 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_stress_all.1074495245
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/48.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/49.alert_handler_entropy.3104562097
Short name T701
Test name
Test status
Simulation time 60808032223 ps
CPU time 1686.46 seconds
Started Sep 11 03:36:56 PM UTC 24
Finished Sep 11 04:05:22 PM UTC 24
Peak memory 302264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104562097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3104562097
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/49.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_alert_accum.989163210
Short name T668
Test name
Test status
Simulation time 3526963234 ps
CPU time 290.44 seconds
Started Sep 11 03:36:39 PM UTC 24
Finished Sep 11 03:41:34 PM UTC 24
Peak memory 269120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989163210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.989163210
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/49.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_intr_timeout.3889366259
Short name T660
Test name
Test status
Simulation time 2800114763 ps
CPU time 68.91 seconds
Started Sep 11 03:36:37 PM UTC 24
Finished Sep 11 03:37:48 PM UTC 24
Peak memory 269104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889366259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3889366259
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/49.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg.3118638772
Short name T379
Test name
Test status
Simulation time 34127126015 ps
CPU time 1028 seconds
Started Sep 11 03:37:05 PM UTC 24
Finished Sep 11 03:54:26 PM UTC 24
Peak memory 285564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118638772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3118638772
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/49.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg_stub_clk.151380464
Short name T693
Test name
Test status
Simulation time 14651108962 ps
CPU time 1243.95 seconds
Started Sep 11 03:37:15 PM UTC 24
Finished Sep 11 03:58:14 PM UTC 24
Peak memory 302208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151380464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.151380464
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/49.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/49.alert_handler_ping_timeout.2261273050
Short name T670
Test name
Test status
Simulation time 15553102811 ps
CPU time 424.44 seconds
Started Sep 11 03:37:00 PM UTC 24
Finished Sep 11 03:44:10 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261273050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2261273050
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_alerts.1808230790
Short name T656
Test name
Test status
Simulation time 767313802 ps
CPU time 27.17 seconds
Started Sep 11 03:36:25 PM UTC 24
Finished Sep 11 03:36:53 PM UTC 24
Peak memory 263220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808230790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1808230790
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/49.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_classes.478938648
Short name T655
Test name
Test status
Simulation time 112048380 ps
CPU time 5.83 seconds
Started Sep 11 03:36:29 PM UTC 24
Finished Sep 11 03:36:36 PM UTC 24
Peak memory 263284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478938648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.478938648
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/49.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/49.alert_handler_sig_int_fail.218357597
Short name T658
Test name
Test status
Simulation time 385279635 ps
CPU time 17.8 seconds
Started Sep 11 03:36:54 PM UTC 24
Finished Sep 11 03:37:13 PM UTC 24
Peak memory 269464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218357597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.218357597
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/49.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/49.alert_handler_smoke.3790147608
Short name T654
Test name
Test status
Simulation time 211919300 ps
CPU time 11.18 seconds
Started Sep 11 03:36:16 PM UTC 24
Finished Sep 11 03:36:28 PM UTC 24
Peak memory 262968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790147608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3790147608
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/49.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all_with_rand_reset.505767412
Short name T263
Test name
Test status
Simulation time 2352285857 ps
CPU time 81.08 seconds
Started Sep 11 03:37:47 PM UTC 24
Finished Sep 11 03:39:10 PM UTC 24
Peak memory 279868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=505767412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.al
ert_handler_stress_all_with_rand_reset.505767412
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/5.alert_handler_alert_accum_saturation.614848127
Short name T144
Test name
Test status
Simulation time 47500492 ps
CPU time 3.88 seconds
Started Sep 11 02:02:07 PM UTC 24
Finished Sep 11 02:02:12 PM UTC 24
Peak memory 263496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614848127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.614848127
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/5.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy.239234251
Short name T117
Test name
Test status
Simulation time 141890666364 ps
CPU time 2363.45 seconds
Started Sep 11 02:01:21 PM UTC 24
Finished Sep 11 02:41:11 PM UTC 24
Peak memory 301888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239234251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.239234251
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/5.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy_stress.1314824381
Short name T21
Test name
Test status
Simulation time 2955046972 ps
CPU time 13.08 seconds
Started Sep 11 02:01:43 PM UTC 24
Finished Sep 11 02:01:57 PM UTC 24
Peak memory 263292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314824381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1314824381
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/5.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_alert_accum.3352660007
Short name T146
Test name
Test status
Simulation time 4904615370 ps
CPU time 91.69 seconds
Started Sep 11 02:01:12 PM UTC 24
Finished Sep 11 02:02:46 PM UTC 24
Peak memory 269264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352660007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3352660007
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/5.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_intr_timeout.1358876573
Short name T89
Test name
Test status
Simulation time 4190651679 ps
CPU time 71.86 seconds
Started Sep 11 02:01:12 PM UTC 24
Finished Sep 11 02:02:26 PM UTC 24
Peak memory 269092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358876573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1358876573
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/5.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg.2259853121
Short name T321
Test name
Test status
Simulation time 14655751507 ps
CPU time 1025.37 seconds
Started Sep 11 02:01:35 PM UTC 24
Finished Sep 11 02:18:53 PM UTC 24
Peak memory 295724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259853121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2259853121
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/5.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg_stub_clk.3514344770
Short name T331
Test name
Test status
Simulation time 37358143014 ps
CPU time 1160.56 seconds
Started Sep 11 02:01:42 PM UTC 24
Finished Sep 11 02:21:17 PM UTC 24
Peak memory 295728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514344770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3514344770
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/5.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/5.alert_handler_ping_timeout.1942998929
Short name T335
Test name
Test status
Simulation time 93576184299 ps
CPU time 563.65 seconds
Started Sep 11 02:01:25 PM UTC 24
Finished Sep 11 02:10:55 PM UTC 24
Peak memory 262960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942998929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1942998929
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_alerts.522320679
Short name T395
Test name
Test status
Simulation time 486302496 ps
CPU time 29.57 seconds
Started Sep 11 02:01:12 PM UTC 24
Finished Sep 11 02:01:43 PM UTC 24
Peak memory 262900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522320679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.522320679
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/5.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_classes.2712815321
Short name T88
Test name
Test status
Simulation time 149304964 ps
CPU time 7.5 seconds
Started Sep 11 02:01:12 PM UTC 24
Finished Sep 11 02:01:21 PM UTC 24
Peak memory 252608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712815321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2712815321
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/5.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/5.alert_handler_sig_int_fail.2668214966
Short name T257
Test name
Test status
Simulation time 3672991988 ps
CPU time 26 seconds
Started Sep 11 02:01:14 PM UTC 24
Finished Sep 11 02:01:42 PM UTC 24
Peak memory 263064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668214966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2668214966
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/5.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/5.alert_handler_smoke.938485646
Short name T83
Test name
Test status
Simulation time 199092544 ps
CPU time 6.98 seconds
Started Sep 11 02:01:01 PM UTC 24
Finished Sep 11 02:01:09 PM UTC 24
Peak memory 262896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938485646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.938485646
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/5.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/6.alert_handler_alert_accum_saturation.1242871166
Short name T243
Test name
Test status
Simulation time 199483704 ps
CPU time 6.05 seconds
Started Sep 11 02:04:13 PM UTC 24
Finished Sep 11 02:04:20 PM UTC 24
Peak memory 263160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242871166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1242871166
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/6.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy.1625727818
Short name T341
Test name
Test status
Simulation time 114673727349 ps
CPU time 1709.89 seconds
Started Sep 11 02:03:27 PM UTC 24
Finished Sep 11 02:32:17 PM UTC 24
Peak memory 300028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625727818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1625727818
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/6.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy_stress.195464319
Short name T19
Test name
Test status
Simulation time 299959023 ps
CPU time 13.16 seconds
Started Sep 11 02:03:58 PM UTC 24
Finished Sep 11 02:04:12 PM UTC 24
Peak memory 262896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195464319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.195464319
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/6.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_alert_accum.2503961982
Short name T125
Test name
Test status
Simulation time 1864137050 ps
CPU time 171.51 seconds
Started Sep 11 02:02:47 PM UTC 24
Finished Sep 11 02:05:42 PM UTC 24
Peak memory 269036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503961982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2503961982
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/6.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_intr_timeout.842859900
Short name T35
Test name
Test status
Simulation time 1612499022 ps
CPU time 79.37 seconds
Started Sep 11 02:02:46 PM UTC 24
Finished Sep 11 02:04:08 PM UTC 24
Peak memory 269360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842859900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.842859900
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/6.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg.2870850352
Short name T29
Test name
Test status
Simulation time 17642435960 ps
CPU time 1106.24 seconds
Started Sep 11 02:03:47 PM UTC 24
Finished Sep 11 02:22:26 PM UTC 24
Peak memory 285816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870850352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2870850352
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/6.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg_stub_clk.191978746
Short name T306
Test name
Test status
Simulation time 43194133469 ps
CPU time 1156.53 seconds
Started Sep 11 02:03:58 PM UTC 24
Finished Sep 11 02:23:27 PM UTC 24
Peak memory 301872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191978746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.191978746
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/6.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_alerts.1452588823
Short name T55
Test name
Test status
Simulation time 4022203471 ps
CPU time 53.12 seconds
Started Sep 11 02:02:27 PM UTC 24
Finished Sep 11 02:03:22 PM UTC 24
Peak memory 269488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452588823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1452588823
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/6.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_classes.1821894485
Short name T54
Test name
Test status
Simulation time 1693985968 ps
CPU time 41.74 seconds
Started Sep 11 02:02:43 PM UTC 24
Finished Sep 11 02:03:26 PM UTC 24
Peak memory 269460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821894485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1821894485
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/6.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/6.alert_handler_smoke.116456239
Short name T254
Test name
Test status
Simulation time 867808243 ps
CPU time 31.33 seconds
Started Sep 11 02:02:14 PM UTC 24
Finished Sep 11 02:02:47 PM UTC 24
Peak memory 269428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116456239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.116456239
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/6.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all.2545932548
Short name T95
Test name
Test status
Simulation time 28862610420 ps
CPU time 180.69 seconds
Started Sep 11 02:04:09 PM UTC 24
Finished Sep 11 02:07:13 PM UTC 24
Peak memory 267052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545932548 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_stress_all.2545932548
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/6.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/7.alert_handler_alert_accum_saturation.1132245621
Short name T127
Test name
Test status
Simulation time 176584488 ps
CPU time 6.15 seconds
Started Sep 11 02:07:06 PM UTC 24
Finished Sep 11 02:07:13 PM UTC 24
Peak memory 263492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132245621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1132245621
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/7.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy.2973792888
Short name T70
Test name
Test status
Simulation time 172759591586 ps
CPU time 2496.09 seconds
Started Sep 11 02:05:27 PM UTC 24
Finished Sep 11 02:47:32 PM UTC 24
Peak memory 298536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973792888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2973792888
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/7.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy_stress.3497797552
Short name T128
Test name
Test status
Simulation time 8540404850 ps
CPU time 70.07 seconds
Started Sep 11 02:06:03 PM UTC 24
Finished Sep 11 02:07:15 PM UTC 24
Peak memory 263032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497797552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3497797552
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/7.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_alert_accum.2333355645
Short name T126
Test name
Test status
Simulation time 2671403416 ps
CPU time 97.36 seconds
Started Sep 11 02:05:03 PM UTC 24
Finished Sep 11 02:06:42 PM UTC 24
Peak memory 263056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333355645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2333355645
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/7.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_intr_timeout.2832631043
Short name T92
Test name
Test status
Simulation time 833777746 ps
CPU time 72.39 seconds
Started Sep 11 02:04:48 PM UTC 24
Finished Sep 11 02:06:03 PM UTC 24
Peak memory 269364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832631043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2832631043
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/7.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg.1617566641
Short name T363
Test name
Test status
Simulation time 41456326651 ps
CPU time 2565.25 seconds
Started Sep 11 02:05:41 PM UTC 24
Finished Sep 11 02:48:55 PM UTC 24
Peak memory 304600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617566641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1617566641
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/7.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg_stub_clk.2606528539
Short name T432
Test name
Test status
Simulation time 51998780754 ps
CPU time 1343.08 seconds
Started Sep 11 02:05:43 PM UTC 24
Finished Sep 11 02:28:22 PM UTC 24
Peak memory 299900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606528539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2606528539
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/7.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/7.alert_handler_ping_timeout.3072232889
Short name T333
Test name
Test status
Simulation time 71607539595 ps
CPU time 395.39 seconds
Started Sep 11 02:05:30 PM UTC 24
Finished Sep 11 02:12:10 PM UTC 24
Peak memory 262968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072232889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3072232889
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/7.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_alerts.3624056938
Short name T160
Test name
Test status
Simulation time 14896026940 ps
CPU time 50.45 seconds
Started Sep 11 02:04:33 PM UTC 24
Finished Sep 11 02:05:25 PM UTC 24
Peak memory 269424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624056938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3624056938
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/7.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_classes.1534465427
Short name T31
Test name
Test status
Simulation time 472157092 ps
CPU time 38.96 seconds
Started Sep 11 02:04:48 PM UTC 24
Finished Sep 11 02:05:29 PM UTC 24
Peak memory 269140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534465427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1534465427
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/7.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/7.alert_handler_sig_int_fail.3091734196
Short name T91
Test name
Test status
Simulation time 290271228 ps
CPU time 30.25 seconds
Started Sep 11 02:05:08 PM UTC 24
Finished Sep 11 02:05:40 PM UTC 24
Peak memory 263256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091734196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3091734196
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/7.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/7.alert_handler_smoke.4247876880
Short name T159
Test name
Test status
Simulation time 461336027 ps
CPU time 38.98 seconds
Started Sep 11 02:04:21 PM UTC 24
Finished Sep 11 02:05:02 PM UTC 24
Peak memory 269036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247876880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.4247876880
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/7.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all.4018112895
Short name T270
Test name
Test status
Simulation time 66798581613 ps
CPU time 4213.8 seconds
Started Sep 11 02:06:43 PM UTC 24
Finished Sep 11 03:17:43 PM UTC 24
Peak memory 321312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018112895 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_stress_all.4018112895
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/7.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/8.alert_handler_alert_accum_saturation.1049147249
Short name T244
Test name
Test status
Simulation time 33621733 ps
CPU time 5.09 seconds
Started Sep 11 02:08:06 PM UTC 24
Finished Sep 11 02:08:12 PM UTC 24
Peak memory 263236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049147249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1049147249
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/8.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy.2000206057
Short name T118
Test name
Test status
Simulation time 39229942720 ps
CPU time 2423.28 seconds
Started Sep 11 02:07:39 PM UTC 24
Finished Sep 11 02:48:32 PM UTC 24
Peak memory 295732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000206057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2000206057
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/8.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy_stress.1626371724
Short name T161
Test name
Test status
Simulation time 381293449 ps
CPU time 8.86 seconds
Started Sep 11 02:07:57 PM UTC 24
Finished Sep 11 02:08:07 PM UTC 24
Peak memory 262968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626371724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1626371724
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/8.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_alert_accum.311656319
Short name T397
Test name
Test status
Simulation time 482861081 ps
CPU time 59.98 seconds
Started Sep 11 02:07:25 PM UTC 24
Finished Sep 11 02:08:27 PM UTC 24
Peak memory 269140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311656319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.311656319
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/8.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_intr_timeout.3053868344
Short name T96
Test name
Test status
Simulation time 4025538143 ps
CPU time 36.43 seconds
Started Sep 11 02:07:20 PM UTC 24
Finished Sep 11 02:07:58 PM UTC 24
Peak memory 269100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053868344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3053868344
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/8.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg.1666609294
Short name T328
Test name
Test status
Simulation time 31412572048 ps
CPU time 1738.78 seconds
Started Sep 11 02:07:41 PM UTC 24
Finished Sep 11 02:36:59 PM UTC 24
Peak memory 283440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666609294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1666609294
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/8.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg_stub_clk.2783430867
Short name T360
Test name
Test status
Simulation time 11634167889 ps
CPU time 975.23 seconds
Started Sep 11 02:07:45 PM UTC 24
Finished Sep 11 02:24:12 PM UTC 24
Peak memory 299824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783430867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2783430867
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/8.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/8.alert_handler_ping_timeout.547252456
Short name T122
Test name
Test status
Simulation time 4540646929 ps
CPU time 259.26 seconds
Started Sep 11 02:07:39 PM UTC 24
Finished Sep 11 02:12:02 PM UTC 24
Peak memory 263288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547252456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.547252456
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_alerts.1814109758
Short name T107
Test name
Test status
Simulation time 217236443 ps
CPU time 21.44 seconds
Started Sep 11 02:07:17 PM UTC 24
Finished Sep 11 02:07:40 PM UTC 24
Peak memory 262960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814109758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1814109758
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/8.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_classes.1734702353
Short name T129
Test name
Test status
Simulation time 42948746 ps
CPU time 6.1 seconds
Started Sep 11 02:07:17 PM UTC 24
Finished Sep 11 02:07:25 PM UTC 24
Peak memory 253012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734702353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1734702353
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/8.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/8.alert_handler_sig_int_fail.865324701
Short name T261
Test name
Test status
Simulation time 68925964 ps
CPU time 8.91 seconds
Started Sep 11 02:07:34 PM UTC 24
Finished Sep 11 02:07:44 PM UTC 24
Peak memory 252660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865324701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.865324701
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/8.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/8.alert_handler_smoke.3619106359
Short name T396
Test name
Test status
Simulation time 1764856647 ps
CPU time 47.7 seconds
Started Sep 11 02:07:17 PM UTC 24
Finished Sep 11 02:08:07 PM UTC 24
Peak memory 262964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619106359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3619106359
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/8.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all.2728972104
Short name T297
Test name
Test status
Simulation time 39597177407 ps
CPU time 1347.13 seconds
Started Sep 11 02:08:05 PM UTC 24
Finished Sep 11 02:30:48 PM UTC 24
Peak memory 302196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728972104 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_stress_all.2728972104
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/8.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all_with_rand_reset.3995606384
Short name T57
Test name
Test status
Simulation time 4834319850 ps
CPU time 382.78 seconds
Started Sep 11 02:08:07 PM UTC 24
Finished Sep 11 02:14:36 PM UTC 24
Peak memory 285612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3995606384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.al
ert_handler_stress_all_with_rand_reset.3995606384
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/9.alert_handler_alert_accum_saturation.3090171087
Short name T245
Test name
Test status
Simulation time 92578553 ps
CPU time 6.44 seconds
Started Sep 11 02:11:00 PM UTC 24
Finished Sep 11 02:11:08 PM UTC 24
Peak memory 263160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090171087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3090171087
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/9.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy.1647088623
Short name T148
Test name
Test status
Simulation time 396799468426 ps
CPU time 1839.01 seconds
Started Sep 11 02:09:35 PM UTC 24
Finished Sep 11 02:40:36 PM UTC 24
Peak memory 295728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647088623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1647088623
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/9.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy_stress.115321180
Short name T399
Test name
Test status
Simulation time 902418389 ps
CPU time 28.97 seconds
Started Sep 11 02:10:37 PM UTC 24
Finished Sep 11 02:11:07 PM UTC 24
Peak memory 262900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115321180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.115321180
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/9.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_alert_accum.736614580
Short name T256
Test name
Test status
Simulation time 1548108936 ps
CPU time 188.17 seconds
Started Sep 11 02:08:55 PM UTC 24
Finished Sep 11 02:12:07 PM UTC 24
Peak memory 269140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736614580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.736614580
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/9.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg.1395127960
Short name T325
Test name
Test status
Simulation time 13134404034 ps
CPU time 1161.15 seconds
Started Sep 11 02:09:57 PM UTC 24
Finished Sep 11 02:29:32 PM UTC 24
Peak memory 281464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395127960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1395127960
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/9.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg_stub_clk.3081754422
Short name T514
Test name
Test status
Simulation time 198762024909 ps
CPU time 3078.53 seconds
Started Sep 11 02:09:57 PM UTC 24
Finished Sep 11 03:01:50 PM UTC 24
Peak memory 298536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081754422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3081754422
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/9.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_alerts.1565803761
Short name T330
Test name
Test status
Simulation time 2535314036 ps
CPU time 97.77 seconds
Started Sep 11 02:08:17 PM UTC 24
Finished Sep 11 02:09:57 PM UTC 24
Peak memory 262952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565803761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1565803761
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/9.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_classes.3671591840
Short name T85
Test name
Test status
Simulation time 1638754617 ps
CPU time 65.78 seconds
Started Sep 11 02:08:18 PM UTC 24
Finished Sep 11 02:09:25 PM UTC 24
Peak memory 269268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671591840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3671591840
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/9.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/9.alert_handler_sig_int_fail.3792584367
Short name T145
Test name
Test status
Simulation time 1178629795 ps
CPU time 28.91 seconds
Started Sep 11 02:09:26 PM UTC 24
Finished Sep 11 02:09:56 PM UTC 24
Peak memory 269400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792584367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3792584367
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/9.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/9.alert_handler_smoke.1541638821
Short name T398
Test name
Test status
Simulation time 818741535 ps
CPU time 45.23 seconds
Started Sep 11 02:08:07 PM UTC 24
Finished Sep 11 02:08:54 PM UTC 24
Peak memory 269428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541638821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1541638821
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/9.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all.3955233687
Short name T67
Test name
Test status
Simulation time 26008780152 ps
CPU time 1571.07 seconds
Started Sep 11 02:10:56 PM UTC 24
Finished Sep 11 02:37:25 PM UTC 24
Peak memory 285492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955233687 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_stress_all.3955233687
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/9.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all_with_rand_reset.2823586512
Short name T39
Test name
Test status
Simulation time 2831203743 ps
CPU time 107.78 seconds
Started Sep 11 02:11:08 PM UTC 24
Finished Sep 11 02:12:58 PM UTC 24
Peak memory 279468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2823586512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.al
ert_handler_stress_all_with_rand_reset.2823586512
Directory /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest
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