Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52673849	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24889988

1

T1

171

T2

1100

T3

1142

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	12220093	1			T1	76		T2	852		T3	761
values[0x0]	32614684	1			T1	213		T2	1138		T3	1334
values[0x1]	32729060	1			T1	233		T2	1044		T3	1242

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45856520	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

31707317

1

T1

207

T2

1336

T3

1406

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	650475	1			T10	26		T12	1		T16	6
valid_sources[0x01]	230626	1			T10	6		T12	12		T16	6
valid_sources[0x02]	231569	1			T10	20		T14	6		T12	14
valid_sources[0x03]	631306	1			T10	12		T14	4		T16	5
valid_sources[0x04]	260387	1			T10	18		T12	3		T16	4
valid_sources[0x05]	232528	1			T10	3		T14	5		T12	5
valid_sources[0x06]	230981	1			T10	14		T12	33		T16	4
valid_sources[0x07]	238910	1			T10	6		T14	1		T12	10
valid_sources[0x08]	245976	1			T10	14		T14	3		T12	2
valid_sources[0x09]	495900	1			T10	15		T14	5		T12	5
valid_sources[0x0a]	485731	1			T10	8		T14	4		T12	9
valid_sources[0x0b]	235812	1			T10	4		T12	3		T16	5
valid_sources[0x0c]	242246	1			T10	14		T14	1		T12	18
valid_sources[0x0d]	231130	1			T10	9		T14	1		T12	10
valid_sources[0x0e]	767036	1			T10	10		T14	3		T12	17
valid_sources[0x0f]	230641	1			T10	2		T14	1		T12	12
valid_sources[0x10]	231297	1			T10	18		T4	3		T14	4
valid_sources[0x11]	230505	1			T10	5		T14	4		T12	31
valid_sources[0x12]	235939	1			T10	14		T14	6		T16	3
valid_sources[0x13]	234186	1			T10	22		T14	1		T12	9
valid_sources[0x14]	233840	1			T10	6		T14	1		T12	7
valid_sources[0x15]	229993	1			T10	7		T14	1		T12	4
valid_sources[0x16]	233665	1			T10	2		T14	2		T12	34
valid_sources[0x17]	230561	1			T10	9		T14	2		T12	7
valid_sources[0x18]	536460	1			T10	5		T12	5		T16	4
valid_sources[0x19]	232428	1			T10	25		T12	18		T16	6
valid_sources[0x1a]	230201	1			T10	3		T14	1		T12	13
valid_sources[0x1b]	232688	1			T10	24		T14	1		T12	8
valid_sources[0x1c]	235508	1			T10	15		T14	5		T12	4
valid_sources[0x1d]	231854	1			T10	11		T12	8		T16	5
valid_sources[0x1e]	275535	1			T10	30		T14	4		T16	2
valid_sources[0x1f]	232154	1			T10	15		T12	4		T16	1
valid_sources[0x20]	231903	1			T10	19		T12	27		T16	4
valid_sources[0x21]	242312	1			T10	16		T16	3		T27	5
valid_sources[0x22]	232000	1			T10	6		T14	1		T12	2
valid_sources[0x23]	232436	1			T10	11		T12	26		T16	4
valid_sources[0x24]	231675	1			T10	7		T12	8		T16	4
valid_sources[0x25]	233176	1			T10	6		T14	4		T12	3
valid_sources[0x26]	231206	1			T10	9		T14	2		T12	30
valid_sources[0x27]	235100	1			T10	30		T12	10		T16	4
valid_sources[0x28]	236740	1			T10	7		T14	4		T12	18
valid_sources[0x29]	248324	1			T10	1		T14	4		T12	16
valid_sources[0x2a]	244578	1			T10	4		T14	2		T12	2
valid_sources[0x2b]	233902	1			T10	2		T4	21		T12	3
valid_sources[0x2c]	523247	1			T10	15		T14	1		T16	4
valid_sources[0x2d]	233054	1			T10	16		T14	1		T12	21
valid_sources[0x2e]	248234	1			T10	9		T12	15		T16	2
valid_sources[0x2f]	232647	1			T10	9		T12	7		T16	7
valid_sources[0x30]	231824	1			T10	18		T12	10		T16	10
valid_sources[0x31]	235010	1			T10	11		T14	4		T12	2
valid_sources[0x32]	235207	1			T3	3337		T10	5		T12	25
valid_sources[0x33]	653041	1			T10	14		T16	1		T27	3
valid_sources[0x34]	232144	1			T10	12		T14	1		T12	5
valid_sources[0x35]	233171	1			T10	3		T14	1		T12	20
valid_sources[0x36]	242545	1			T10	1		T14	2		T16	5
valid_sources[0x37]	560337	1			T10	18		T14	2		T12	14
valid_sources[0x38]	233137	1			T10	16		T4	37		T12	15
valid_sources[0x39]	236826	1			T10	3		T14	3		T12	26
valid_sources[0x3a]	660903	1			T10	5		T14	4		T16	8
valid_sources[0x3b]	739117	1			T10	13		T12	11		T16	8
valid_sources[0x3c]	901767	1			T10	8		T14	7		T16	4
valid_sources[0x3d]	233034	1			T10	1		T12	1		T16	1
valid_sources[0x3e]	478900	1			T10	5		T12	8		T16	8
valid_sources[0x3f]	233552	1			T10	12		T14	1		T12	10
valid_sources[0x40]	229537	1			T10	11		T14	3		T12	44
valid_sources[0x41]	231806	1			T10	7		T12	12		T16	7
valid_sources[0x42]	236278	1			T14	2		T12	24		T16	3
valid_sources[0x43]	235860	1			T10	16		T14	1		T12	30
valid_sources[0x44]	231167	1			T10	4		T14	1		T12	21
valid_sources[0x45]	245645	1			T10	12		T12	15		T16	3
valid_sources[0x46]	235488	1			T10	6		T4	14		T12	21
valid_sources[0x47]	232703	1			T10	1		T12	20		T16	3
valid_sources[0x48]	231977	1			T10	6		T12	13		T16	3
valid_sources[0x49]	230415	1			T10	12		T14	3		T12	9
valid_sources[0x4a]	278662	1			T10	9		T12	1		T16	6
valid_sources[0x4b]	235289	1			T10	8		T14	4		T12	6
valid_sources[0x4c]	244100	1			T10	2		T14	2		T12	45
valid_sources[0x4d]	236673	1			T10	12		T14	6		T12	13
valid_sources[0x4e]	233076	1			T10	2		T12	11		T16	5
valid_sources[0x4f]	254174	1			T10	23		T4	28		T14	11
valid_sources[0x50]	717456	1			T12	17		T16	7		T27	2
valid_sources[0x51]	454434	1			T10	29		T12	15		T16	2
valid_sources[0x52]	234007	1			T10	8		T14	4		T12	10
valid_sources[0x53]	233610	1			T10	5		T14	4		T12	21
valid_sources[0x54]	236758	1			T10	9		T14	3		T12	18
valid_sources[0x55]	232612	1			T10	11		T14	2		T12	7
valid_sources[0x56]	233011	1			T10	14		T12	1		T16	2
valid_sources[0x57]	231743	1			T10	15		T14	1		T12	18
valid_sources[0x58]	701808	1			T10	5		T12	3		T16	4
valid_sources[0x59]	237604	1			T10	13		T14	5		T12	6
valid_sources[0x5a]	233689	1			T10	21		T4	28		T14	7
valid_sources[0x5b]	446252	1			T10	14		T4	3		T14	1
valid_sources[0x5c]	455185	1			T10	17		T16	6		T27	6
valid_sources[0x5d]	232882	1			T10	6		T14	5		T12	3
valid_sources[0x5e]	235637	1			T10	2		T14	2		T12	8
valid_sources[0x5f]	237326	1			T10	9		T14	1		T12	17
valid_sources[0x60]	232027	1			T10	10		T16	2		T27	1
valid_sources[0x61]	560940	1			T10	15		T12	8		T16	5
valid_sources[0x62]	240353	1			T10	8		T14	4		T12	8
valid_sources[0x63]	234933	1			T10	4		T14	8		T12	30
valid_sources[0x64]	232576	1			T10	3		T14	3		T12	21
valid_sources[0x65]	232307	1			T10	4		T14	3		T12	8
valid_sources[0x66]	231975	1			T10	7		T12	12		T16	4
valid_sources[0x67]	250287	1			T10	6		T14	5		T12	33
valid_sources[0x68]	234758	1			T10	8		T12	4		T16	4
valid_sources[0x69]	234723	1			T10	19		T14	2		T12	11
valid_sources[0x6a]	235927	1			T10	17		T12	39		T16	3
valid_sources[0x6b]	899791	1			T10	12		T14	4		T12	1
valid_sources[0x6c]	236314	1			T12	17		T16	3		T27	3
valid_sources[0x6d]	235963	1			T10	8		T12	19		T16	4
valid_sources[0x6e]	231277	1			T10	8		T14	1		T12	2
valid_sources[0x6f]	234695	1			T10	11		T14	1		T12	24
valid_sources[0x70]	466578	1			T10	18		T14	4		T12	22
valid_sources[0x71]	230117	1			T10	11		T4	25		T12	4
valid_sources[0x72]	1189450	1			T10	4		T14	4		T12	5
valid_sources[0x73]	233321	1			T10	9		T12	9		T16	5
valid_sources[0x74]	235363	1			T10	11		T12	26		T16	3
valid_sources[0x75]	593107	1			T14	1		T16	3		T27	4
valid_sources[0x76]	466714	1			T10	3		T12	1		T16	1
valid_sources[0x77]	231431	1			T10	11		T14	1		T12	15
valid_sources[0x78]	242969	1			T10	2		T12	27		T16	5
valid_sources[0x79]	234026	1			T10	18		T12	6		T16	6
valid_sources[0x7a]	230752	1			T10	7		T14	1		T12	2
valid_sources[0x7b]	234743	1			T10	14		T14	1		T12	4
valid_sources[0x7c]	241766	1			T10	18		T12	20		T16	1
valid_sources[0x7d]	230104	1			T10	11		T12	6		T16	3
valid_sources[0x7e]	232942	1			T10	5		T14	5		T12	25
valid_sources[0x7f]	233047	1			T10	1		T14	2		T12	3
valid_sources[0x80]	239583	1			T10	7		T4	63		T14	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5846416

1

T1

40

T2

405

T3

371

values[0x0]

all_enables

biggest_size

12163159

1

T1

78

T2

465

T3

501

values[0x1]

all_enables

biggest_size

6880413

1

T1

53

T2

230

T3

270