Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.gen_esc_sev[0].u_esc_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_esc_sev[1].u_esc_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_esc_sev[2].u_esc_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_esc_sev[3].u_esc_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_esc_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T7,T8 Yes T4,T7,T8 INPUT
ping_ok_o Yes Yes T4,T7,T8 Yes T4,T7,T8 OUTPUT
integ_fail_o Yes Yes T14,T12,T5 Yes T14,T12,T5 OUTPUT
esc_req_i Yes Yes T2,T3,T10 Yes T2,T3,T10 INPUT
esc_rx_i.resp_n Yes Yes T2,T3,T10 Yes T2,T3,T10 INPUT
esc_rx_i.resp_p Yes Yes T2,T3,T10 Yes T2,T3,T10 INPUT
esc_tx_o.esc_n Yes Yes T2,T3,T10 Yes T2,T3,T10 OUTPUT
esc_tx_o.esc_p Yes Yes T2,T3,T10 Yes T2,T3,T10 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_esc_sev[0].u_esc_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T7,T8 Yes T4,T7,T8 INPUT
ping_ok_o Yes Yes T4,T7,T8 Yes T4,T7,T8 OUTPUT
integ_fail_o Yes Yes T14,T12,T5 Yes T14,T12,T5 OUTPUT
esc_req_i Yes Yes T2,T10,T14 Yes T2,T10,T14 INPUT
esc_rx_i.resp_n Yes Yes T2,T10,T4 Yes T2,T10,T4 INPUT
esc_rx_i.resp_p Yes Yes T2,T10,T4 Yes T2,T10,T4 INPUT
esc_tx_o.esc_n Yes Yes T2,T10,T4 Yes T2,T10,T4 OUTPUT
esc_tx_o.esc_p Yes Yes T2,T10,T4 Yes T2,T10,T4 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_esc_sev[1].u_esc_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T7,T8 Yes T4,T7,T8 INPUT
ping_ok_o Yes Yes T4,T7,T8 Yes T4,T7,T8 OUTPUT
integ_fail_o Yes Yes T14,T12,T5 Yes T14,T12,T5 OUTPUT
esc_req_i Yes Yes T3,T14,T12 Yes T3,T14,T12 INPUT
esc_rx_i.resp_n Yes Yes T3,T4,T12 Yes T3,T4,T12 INPUT
esc_rx_i.resp_p Yes Yes T3,T4,T12 Yes T3,T4,T12 INPUT
esc_tx_o.esc_n Yes Yes T3,T4,T14 Yes T3,T4,T14 OUTPUT
esc_tx_o.esc_p Yes Yes T3,T4,T14 Yes T3,T4,T14 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_esc_sev[2].u_esc_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T7,T8 Yes T4,T7,T8 INPUT
ping_ok_o Yes Yes T4,T7,T8 Yes T4,T7,T8 OUTPUT
integ_fail_o Yes Yes T14,T12,T5 Yes T14,T12,T5 OUTPUT
esc_req_i Yes Yes T2,T14,T12 Yes T2,T14,T12 INPUT
esc_rx_i.resp_n Yes Yes T2,T4,T12 Yes T2,T4,T12 INPUT
esc_rx_i.resp_p Yes Yes T2,T4,T12 Yes T2,T4,T12 INPUT
esc_tx_o.esc_n Yes Yes T2,T4,T14 Yes T2,T4,T14 OUTPUT
esc_tx_o.esc_p Yes Yes T2,T4,T14 Yes T2,T4,T14 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_esc_sev[3].u_esc_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T7,T8 Yes T4,T7,T8 INPUT
ping_ok_o Yes Yes T4,T7,T8 Yes T4,T7,T8 OUTPUT
integ_fail_o Yes Yes T14,T12,T5 Yes T14,T12,T5 OUTPUT
esc_req_i Yes Yes T3,T10,T14 Yes T3,T10,T14 INPUT
esc_rx_i.resp_n Yes Yes T3,T10,T4 Yes T3,T10,T4 INPUT
esc_rx_i.resp_p Yes Yes T3,T10,T4 Yes T3,T10,T4 INPUT
esc_tx_o.esc_n Yes Yes T3,T10,T4 Yes T3,T10,T4 OUTPUT
esc_tx_o.esc_p Yes Yes T3,T10,T4 Yes T3,T10,T4 OUTPUT

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%