Module Definition
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Module Instance : tb.dut.gen_classes[0].u_accu

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_count 100.00 100.00



Module Instance : tb.dut.gen_classes[1].u_accu

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_count 100.00 100.00



Module Instance : tb.dut.gen_classes[2].u_accu

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_count 100.00 100.00



Module Instance : tb.dut.gen_classes[3].u_accu

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_count 100.00 100.00

Line Coverage for Module : alert_handler_accu
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN5611100.00

27 logic trig_gated, accu_en; 28 1/1 assign trig_gated = class_trig_i & class_en_i; Tests: T1 T2 T3  29 1/1 assign accu_en = trig_gated && !(&accu_cnt_o); Tests: T1 T2 T3  30 31 // SEC_CM: ACCU.CTR.REDUN 32 // We employ two redundant counters to guard against FI attacks. 33 // If any of the two is glitched and the two counter states do not agree, 34 // the check_fail_o signal is asserted which will move the corresponding escalation 35 // FSM into a terminal error state where all escalation actions will be permanently asserted. 36 prim_count #( 37 .Width(AccuCntDw), 38 // The alert handler behaves differently than other comportable IP. I.e., instead of sending out 39 // an alert signal, this condition is handled internally in the alert handler. 40 .EnableAlertTriggerSVA(0) 41 ) u_prim_count ( 42 .clk_i, 43 .rst_ni, 44 .clr_i, 45 .set_i(1'b0), 46 .set_cnt_i('0), 47 .incr_en_i(accu_en), 48 .decr_en_i(1'b0), 49 .step_i(AccuCntDw'(1)), 50 .cnt_o(accu_cnt_o), 51 .commit_i(1'b1), 52 .cnt_after_commit_o(), 53 .err_o(accu_fail_o) 54 ); 55 56 1/1 assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated; Tests: T1 T2 T3 

Cond Coverage for Module : alert_handler_accu
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT14,T27,T89
11CoveredT1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT2,T3,T10

Assert Coverage for Module : alert_handler_accu
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CountSaturateStable_A 2147483647 13143 0 0
DisabledNoTrigBkwd_A 2147483647 674568 0 0
DisabledNoTrigFwd_A 2147483647 1237516747 0 0


CountSaturateStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 13143 0 0
T6 45716 0 0 0
T7 38029 0 0 0
T13 48878 0 0 0
T14 5271 1635 0 0
T15 81061 0 0 0
T17 3430 0 0 0
T24 49395 0 0 0
T25 51385 0 0 0
T27 10112 1497 0 0
T28 87384 0 0 0
T43 228590 0 0 0
T44 40961 0 0 0
T51 36483 0 0 0
T54 3951 472 0 0
T55 253249 0 0 0
T56 290011 0 0 0
T57 21699 0 0 0
T75 0 497 0 0
T78 0 1001 0 0
T82 0 419 0 0
T84 17307 0 0 0
T85 63187 0 0 0
T89 0 326 0 0
T91 1766 0 0 0
T127 0 780 0 0
T238 0 663 0 0
T239 0 448 0 0
T240 0 421 0 0
T241 0 550 0 0
T242 0 418 0 0
T243 0 556 0 0
T244 0 363 0 0
T245 0 608 0 0
T246 0 740 0 0
T247 0 1230 0 0
T248 0 110 0 0
T249 0 409 0 0
T250 1681 0 0 0

DisabledNoTrigBkwd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 674568 0 0
T2 18810 5 0 0
T3 28578 9 0 0
T4 46815 0 0 0
T5 70700 0 0 0
T6 22858 0 0 0
T10 68178 1 0 0
T11 37768 6 0 0
T12 93392 9 0 0
T14 21084 40 0 0
T15 0 35 0 0
T16 13988 0 0 0
T17 3430 2 0 0
T27 20224 21 0 0
T28 43692 5 0 0
T30 0 84 0 0
T41 0 4 0 0
T43 114295 60 0 0
T44 0 32 0 0
T46 0 2 0 0
T52 0 75 0 0
T53 0 1 0 0
T54 0 3 0 0
T55 0 1414 0 0
T56 0 4 0 0
T57 0 57 0 0

DisabledNoTrigFwd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1237516747 0 0
T1 27696 21410 0 0
T2 37620 22959 0 0
T3 38104 30534 0 0
T4 62420 16871 0 0
T5 70700 18916 0 0
T10 90904 70065 0 0
T11 37768 30180 0 0
T12 93392 60465 0 0
T14 21084 12897 0 0
T16 13988 8970 0 0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN5611100.00

27 logic trig_gated, accu_en; 28 1/1 assign trig_gated = class_trig_i & class_en_i; Tests: T1 T2 T3  29 1/1 assign accu_en = trig_gated && !(&accu_cnt_o); Tests: T1 T2 T3  30 31 // SEC_CM: ACCU.CTR.REDUN 32 // We employ two redundant counters to guard against FI attacks. 33 // If any of the two is glitched and the two counter states do not agree, 34 // the check_fail_o signal is asserted which will move the corresponding escalation 35 // FSM into a terminal error state where all escalation actions will be permanently asserted. 36 prim_count #( 37 .Width(AccuCntDw), 38 // The alert handler behaves differently than other comportable IP. I.e., instead of sending out 39 // an alert signal, this condition is handled internally in the alert handler. 40 .EnableAlertTriggerSVA(0) 41 ) u_prim_count ( 42 .clk_i, 43 .rst_ni, 44 .clr_i, 45 .set_i(1'b0), 46 .set_cnt_i('0), 47 .incr_en_i(accu_en), 48 .decr_en_i(1'b0), 49 .step_i(AccuCntDw'(1)), 50 .cnt_o(accu_cnt_o), 51 .commit_i(1'b1), 52 .cnt_after_commit_o(), 53 .err_o(accu_fail_o) 54 ); 55 56 1/1 assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----
-1--2-StatusTests
01CoveredT2,T3,T10
10CoveredT1,T2,T3
11CoveredT2,T3,T10

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT27,T240,T243
11CoveredT2,T3,T10

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----
-1--2-StatusTests
01CoveredT2,T3,T12
10CoveredT1,T2,T3
11CoveredT3,T10,T12

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CountSaturateStable_A 554507586 4341 0 0
DisabledNoTrigBkwd_A 554507586 192734 0 0
DisabledNoTrigFwd_A 554507586 276407872 0 0


CountSaturateStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 554507586 4341 0 0
T6 22858 0 0 0
T7 38029 0 0 0
T13 48878 0 0 0
T15 81061 0 0 0
T17 1715 0 0 0
T27 5056 1497 0 0
T28 43692 0 0 0
T43 114295 0 0 0
T44 40961 0 0 0
T51 36483 0 0 0
T240 0 421 0 0
T243 0 556 0 0
T245 0 608 0 0
T246 0 740 0 0
T248 0 110 0 0
T249 0 409 0 0

DisabledNoTrigBkwd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 554507586 192734 0 0
T3 9526 9 0 0
T4 15605 0 0 0
T5 17675 0 0 0
T10 22726 1 0 0
T11 9442 6 0 0
T12 23348 2 0 0
T14 5271 0 0 0
T16 3497 0 0 0
T17 1715 2 0 0
T27 5056 21 0 0
T28 0 5 0 0
T30 0 24 0 0
T43 0 60 0 0
T52 0 75 0 0

DisabledNoTrigFwd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 554507586 276407872 0 0
T1 6924 6861 0 0
T2 9405 6194 0 0
T3 9526 4217 0 0
T4 15605 4186 0 0
T5 17675 4729 0 0
T10 22726 2040 0 0
T11 9442 6522 0 0
T12 23348 5847 0 0
T14 5271 3189 0 0
T16 3497 3404 0 0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN5611100.00

27 logic trig_gated, accu_en; 28 1/1 assign trig_gated = class_trig_i & class_en_i; Tests: T1 T2 T3  29 1/1 assign accu_en = trig_gated && !(&accu_cnt_o); Tests: T1 T2 T3  30 31 // SEC_CM: ACCU.CTR.REDUN 32 // We employ two redundant counters to guard against FI attacks. 33 // If any of the two is glitched and the two counter states do not agree, 34 // the check_fail_o signal is asserted which will move the corresponding escalation 35 // FSM into a terminal error state where all escalation actions will be permanently asserted. 36 prim_count #( 37 .Width(AccuCntDw), 38 // The alert handler behaves differently than other comportable IP. I.e., instead of sending out 39 // an alert signal, this condition is handled internally in the alert handler. 40 .EnableAlertTriggerSVA(0) 41 ) u_prim_count ( 42 .clk_i, 43 .rst_ni, 44 .clr_i, 45 .set_i(1'b0), 46 .set_cnt_i('0), 47 .incr_en_i(accu_en), 48 .decr_en_i(1'b0), 49 .step_i(AccuCntDw'(1)), 50 .cnt_o(accu_cnt_o), 51 .commit_i(1'b1), 52 .cnt_after_commit_o(), 53 .err_o(accu_fail_o) 54 ); 55 56 1/1 assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T12
11CoveredT2,T4,T12

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT54,T82,T244
11CoveredT2,T4,T12

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----
-1--2-StatusTests
01CoveredT2,T12,T16
10CoveredT1,T2,T3
11CoveredT2,T4,T12

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CountSaturateStable_A 554507586 1254 0 0
DisabledNoTrigBkwd_A 554507586 170308 0 0
DisabledNoTrigFwd_A 554507586 303928857 0 0


CountSaturateStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 554507586 1254 0 0
T24 49395 0 0 0
T25 51385 0 0 0
T54 3951 472 0 0
T55 253249 0 0 0
T56 290011 0 0 0
T57 21699 0 0 0
T82 0 419 0 0
T84 17307 0 0 0
T85 63187 0 0 0
T91 1766 0 0 0
T244 0 363 0 0
T250 1681 0 0 0

DisabledNoTrigBkwd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 554507586 170308 0 0
T2 9405 5 0 0
T3 9526 0 0 0
T4 15605 0 0 0
T5 17675 0 0 0
T10 22726 0 0 0
T11 9442 0 0 0
T12 23348 7 0 0
T14 5271 0 0 0
T16 3497 0 0 0
T27 5056 0 0 0
T30 0 3 0 0
T41 0 4 0 0
T46 0 2 0 0
T53 0 1 0 0
T54 0 3 0 0
T55 0 74 0 0
T56 0 4 0 0
T57 0 3 0 0

DisabledNoTrigFwd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 554507586 303928857 0 0
T1 6924 6861 0 0
T2 9405 5823 0 0
T3 9526 8435 0 0
T4 15605 4208 0 0
T5 17675 4729 0 0
T10 22726 22675 0 0
T11 9442 9369 0 0
T12 23348 11822 0 0
T14 5271 3213 0 0
T16 3497 1081 0 0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN5611100.00

27 logic trig_gated, accu_en; 28 1/1 assign trig_gated = class_trig_i & class_en_i; Tests: T1 T2 T3  29 1/1 assign accu_en = trig_gated && !(&accu_cnt_o); Tests: T1 T2 T3  30 31 // SEC_CM: ACCU.CTR.REDUN 32 // We employ two redundant counters to guard against FI attacks. 33 // If any of the two is glitched and the two counter states do not agree, 34 // the check_fail_o signal is asserted which will move the corresponding escalation 35 // FSM into a terminal error state where all escalation actions will be permanently asserted. 36 prim_count #( 37 .Width(AccuCntDw), 38 // The alert handler behaves differently than other comportable IP. I.e., instead of sending out 39 // an alert signal, this condition is handled internally in the alert handler. 40 .EnableAlertTriggerSVA(0) 41 ) u_prim_count ( 42 .clk_i, 43 .rst_ni, 44 .clr_i, 45 .set_i(1'b0), 46 .set_cnt_i('0), 47 .incr_en_i(accu_en), 48 .decr_en_i(1'b0), 49 .step_i(AccuCntDw'(1)), 50 .cnt_o(accu_cnt_o), 51 .commit_i(1'b1), 52 .cnt_after_commit_o(), 53 .err_o(accu_fail_o) 54 ); 55 56 1/1 assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T12,T16
11CoveredT1,T2,T14

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT14,T75,T127
11CoveredT1,T2,T14

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----
-1--2-StatusTests
01CoveredT1,T2,T14
10CoveredT1,T2,T3
11CoveredT14,T15,T44

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CountSaturateStable_A 554507586 3778 0 0
DisabledNoTrigBkwd_A 554507586 161284 0 0
DisabledNoTrigFwd_A 554507586 320725432 0 0


CountSaturateStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 554507586 3778 0 0
T5 17675 0 0 0
T6 22858 0 0 0
T11 9442 0 0 0
T12 23348 0 0 0
T14 5271 1635 0 0
T16 3497 0 0 0
T17 1715 0 0 0
T27 5056 0 0 0
T28 43692 0 0 0
T43 114295 0 0 0
T75 0 497 0 0
T127 0 780 0 0
T239 0 448 0 0
T242 0 418 0 0

DisabledNoTrigBkwd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 554507586 161284 0 0
T5 17675 0 0 0
T6 22858 0 0 0
T11 9442 0 0 0
T12 23348 0 0 0
T14 5271 40 0 0
T15 0 35 0 0
T16 3497 0 0 0
T17 1715 0 0 0
T18 0 1 0 0
T27 5056 0 0 0
T28 43692 0 0 0
T30 0 57 0 0
T31 0 32 0 0
T43 114295 0 0 0
T44 0 32 0 0
T45 0 62 0 0
T55 0 1340 0 0
T57 0 54 0 0
T75 0 6 0 0

DisabledNoTrigFwd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 554507586 320725432 0 0
T1 6924 3834 0 0
T2 9405 8236 0 0
T3 9526 8435 0 0
T4 15605 4233 0 0
T5 17675 4729 0 0
T10 22726 22675 0 0
T11 9442 9369 0 0
T12 23348 19543 0 0
T14 5271 3236 0 0
T16 3497 3404 0 0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN5611100.00

27 logic trig_gated, accu_en; 28 1/1 assign trig_gated = class_trig_i & class_en_i; Tests: T1 T2 T3  29 1/1 assign accu_en = trig_gated && !(&accu_cnt_o); Tests: T1 T2 T3  30 31 // SEC_CM: ACCU.CTR.REDUN 32 // We employ two redundant counters to guard against FI attacks. 33 // If any of the two is glitched and the two counter states do not agree, 34 // the check_fail_o signal is asserted which will move the corresponding escalation 35 // FSM into a terminal error state where all escalation actions will be permanently asserted. 36 prim_count #( 37 .Width(AccuCntDw), 38 // The alert handler behaves differently than other comportable IP. I.e., instead of sending out 39 // an alert signal, this condition is handled internally in the alert handler. 40 .EnableAlertTriggerSVA(0) 41 ) u_prim_count ( 42 .clk_i, 43 .rst_ni, 44 .clr_i, 45 .set_i(1'b0), 46 .set_cnt_i('0), 47 .incr_en_i(accu_en), 48 .decr_en_i(1'b0), 49 .step_i(AccuCntDw'(1)), 50 .cnt_o(accu_cnt_o), 51 .commit_i(1'b1), 52 .cnt_after_commit_o(), 53 .err_o(accu_fail_o) 54 ); 55 56 1/1 assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT2,T12,T16
11CoveredT1,T2,T16

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT89,T78,T238
11CoveredT1,T2,T16

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----
-1--2-StatusTests
01CoveredT1,T2,T16
10CoveredT1,T2,T3
11CoveredT2,T15,T89

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CountSaturateStable_A 554507586 3770 0 0
DisabledNoTrigBkwd_A 554507586 150242 0 0
DisabledNoTrigFwd_A 554507586 336454586 0 0


CountSaturateStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 554507586 3770 0 0
T8 69898 0 0 0
T9 20610 0 0 0
T22 9298 0 0 0
T30 80971 0 0 0
T31 25441 0 0 0
T45 27207 0 0 0
T52 95605 0 0 0
T78 0 1001 0 0
T89 2582 326 0 0
T94 199960 0 0 0
T95 98803 0 0 0
T238 0 663 0 0
T241 0 550 0 0
T247 0 1230 0 0

DisabledNoTrigBkwd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 554507586 150242 0 0
T2 9405 1 0 0
T3 9526 0 0 0
T4 15605 0 0 0
T5 17675 0 0 0
T10 22726 0 0 0
T11 9442 0 0 0
T12 23348 0 0 0
T14 5271 0 0 0
T15 0 23 0 0
T16 3497 0 0 0
T27 5056 0 0 0
T30 0 5 0 0
T31 0 16 0 0
T46 0 8 0 0
T53 0 194 0 0
T74 0 91 0 0
T78 0 16 0 0
T89 0 4 0 0
T94 0 31 0 0

DisabledNoTrigFwd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 554507586 336454586 0 0
T1 6924 3854 0 0
T2 9405 2706 0 0
T3 9526 9447 0 0
T4 15605 4244 0 0
T5 17675 4729 0 0
T10 22726 22675 0 0
T11 9442 4920 0 0
T12 23348 23253 0 0
T14 5271 3259 0 0
T16 3497 1081 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%