Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T2 T3 T10 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T2 T3 T10 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T2 T3 T10 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T13 
159        1/1                    state_d = TimeoutSt;
           Tests:       T1 T2 T13 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T1 T2 T13 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T1 T2 T13 
172        1/1                    state_d    = Phase0St;
           Tests:       T13 T30 T31 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T13 T30 T31 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T13 T30 T31 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T13 T30 T31 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T1 T2 T13 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T13 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T1 T2 T13 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T13 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T3 T10 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T2 T3 T10 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T2 T3 T10 
190        1/1                  esc_state_o = Phase0;
           Tests:       T2 T3 T10 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T2 T3 T10 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T2 T3 T10 
194        1/1                    state_d = IdleSt;
           Tests:       T13 T32 T33 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T32 T33 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T13 T32 T33 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T3 T10 
198        1/1                    state_d = Phase1St;
           Tests:       T2 T3 T10 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T3 T10 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T3 T10 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T3 T10 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T2 T3 T10 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T2 T3 T10 
207        1/1                  esc_state_o = Phase1;
           Tests:       T2 T3 T10 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T2 T3 T10 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T2 T3 T10 
211        1/1                    state_d = IdleSt;
           Tests:       T34 T35 T36 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 T36 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T34 T35 T36 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T3 T10 
215        1/1                    state_d = Phase2St;
           Tests:       T2 T3 T10 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T3 T10 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T3 T10 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T3 T10 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T2 T3 T10 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T2 T3 T10 
224        1/1                  esc_state_o = Phase2;
           Tests:       T2 T3 T10 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T2 T3 T10 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T2 T3 T10 
229        1/1                    state_d = IdleSt;
           Tests:       T2 T37 T38 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T37 T38 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T2 T37 T38 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T3 T10 
233        1/1                    state_d = Phase3St;
           Tests:       T2 T3 T10 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T3 T10 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T3 T10 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T2 T3 T10 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T2 T3 T10 
241        1/1                  esc_state_o = Phase3;
           Tests:       T2 T3 T10 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T2 T3 T10 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T2 T3 T10 
245        1/1                    state_d = IdleSt;
           Tests:       T2 T34 T39 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T34 T39 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T2 T34 T39 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T3 T10 
249        1/1                    state_d = TerminalSt;
           Tests:       T3 T10 T14 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T14 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T3 T10 T14 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T3 T10 T14 
259        1/1                  esc_state_o = Terminal;
           Tests:       T3 T10 T14 
260        1/1                  if (clr_i) begin
           Tests:       T3 T10 T14 
261        1/1                    state_d = IdleSt;
           Tests:       T12 T17 T15 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T5 T6 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T5 T6 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T5 T6 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T5 T6 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T10

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T14,T12,T27
1	1	0	Covered	T2,T12,T11
1	1	1	Covered	T1,T2,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T13
0	1	Covered	T13,T30,T40
1	0	Covered	T31,T41,T26

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T13
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T31,T41,T26

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Covered	T42
1	1	Covered	T13,T30,T40

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T10,T14,T11

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T10,T14
1	Covered	T3,T43,T44

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T12,T17

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T28,T45,T46

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T5,T6,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T10,T14,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T3,T14,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T2,T14,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T3,T10,T14

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T6,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T10
Phase1St	198	Covered	T2,T3,T10
Phase2St	215	Covered	T2,T3,T10
Phase3St	233	Covered	T2,T3,T10
TerminalSt	249	Covered	T3,T10,T14
TimeoutSt	159	Covered	T1,T2,T13

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T5,T6,T9
IdleSt->Phase0St	152	Covered	T2,T3,T10
IdleSt->TimeoutSt	159	Covered	T1,T2,T13
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T13,T26,T47
Phase0St->Phase1St	198	Covered	T2,T3,T10
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T34,T35,T36
Phase1St->Phase2St	215	Covered	T2,T3,T10
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T2,T37,T48
Phase2St->Phase3St	233	Covered	T2,T3,T10
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T2,T34,T39
Phase3St->TerminalSt	249	Covered	T3,T10,T14
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T12,T17,T15
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T2,T13
TimeoutSt->Phase0St	172	Covered	T13,T30,T31

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T13,T30,T31
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T13
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T13,T32,T33
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T10
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T10
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T34,T35,T36
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T10
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T10
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T37,T38
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T10
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T2,T34,T39
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T10,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T10
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T12,T17,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T10,T14
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	761	0	0
CheckAccumTrig0_A	2147483647	2351	0	0
CheckAccumTrig1_A	2147483647	125	0	0
CheckClr_A	2147483647	1174	0	0
CheckEn_A	2147483647	933456250	0	0
CheckPhase0_A	2147483647	2641	0	0
CheckPhase1_A	2147483647	2579	0	0
CheckPhase2_A	2147483647	2516	0	0
CheckPhase3_A	2147483647	2462	0	0
CheckTimeout0_A	2147483647	3561	0	0
CheckTimeoutSt1_A	2147483647	361673	0	0
CheckTimeoutSt2_A	2147483647	3187	0	0
CheckTimeoutStTrig_A	2147483647	235	0	0
ErrorStAllEscAsserted_A	2147483647	3872	0	0
ErrorStIsTerminal_A	2147483647	3152	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	761	0	0
T5	70700	105	0	0
T6	91432	137	0	0
T7	152116	0	0	0
T9	0	137	0	0
T15	324244	0	0	0
T17	6860	0	0	0
T27	20224	0	0	0
T28	174768	0	0	0
T43	457180	0	0	0
T44	163844	0	0	0
T49	0	239	0	0
T50	0	143	0	0
T51	145932	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2351	0	0
T2	18810	2	0	0
T3	28578	1	0	0
T4	46815	0	0	0
T5	70700	0	0	0
T6	22858	0	0	0
T10	68178	1	0	0
T11	37768	1	0	0
T12	93392	2	0	0
T14	21084	1	0	0
T15	0	2	0	0
T16	13988	0	0	0
T17	3430	1	0	0
T27	20224	1	0	0
T28	43692	1	0	0
T30	0	4	0	0
T41	0	1	0	0
T43	114295	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	4	0	0
T56	0	1	0	0
T57	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	125	0	0
T18	432216	0	0	0
T22	9298	0	0	0
T23	21880	0	0	0
T26	0	1	0	0
T31	25441	1	0	0
T32	0	1	0	0
T34	25781	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T39	74554	0	0	0
T40	46010	0	0	0
T41	34028	1	0	0
T49	77280	0	0	0
T50	15564	0	0	0
T58	0	1	0	0
T59	25276	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	42134	0	0	0
T74	15413	0	0	0
T75	2871	0	0	0
T76	109350	0	0	0
T77	111285	0	0	0
T78	3301	0	0	0
T79	162186	0	0	0
T80	80472	0	0	0
T81	8763	0	0	0
T82	3334	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1174	0	0
T2	9405	2	0	0
T3	9526	0	0	0
T4	15605	0	0	0
T5	35350	0	0	0
T6	22858	0	0	0
T7	38029	0	0	0
T10	22726	0	0	0
T11	18884	0	0	0
T12	46696	1	0	0
T13	48878	1	0	0
T14	5271	0	0	0
T15	81061	1	0	0
T16	6994	0	0	0
T17	1715	1	0	0
T26	0	4	0	0
T27	10112	0	0	0
T28	43692	0	0	0
T30	80971	2	0	0
T31	0	1	0	0
T34	0	8	0	0
T37	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T43	114295	0	0	0
T44	40961	0	0	0
T52	95605	0	0	0
T55	0	4	0	0
T57	0	1	0	0
T58	0	1	0	0
T83	0	5	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	0	3	0	0
T89	2582	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	933456250	0	0
T1	27696	21408	0	0
T2	37620	22957	0	0
T3	38104	26896	0	0
T4	62420	16867	0	0
T5	2408	2004	0	0
T10	90904	70062	0	0
T11	37768	30177	0	0
T12	93392	50753	0	0
T14	21084	12897	0	0
T16	13988	8966	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2641	0	0
T2	18810	2	0	0
T3	28578	1	0	0
T4	46815	0	0	0
T5	70700	0	0	0
T6	22858	0	0	0
T10	68178	1	0	0
T11	37768	1	0	0
T12	93392	2	0	0
T14	21084	1	0	0
T15	0	2	0	0
T16	13988	0	0	0
T17	3430	1	0	0
T27	20224	1	0	0
T28	43692	1	0	0
T30	0	5	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	114295	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	4	0	0
T90	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2579	0	0
T2	18810	2	0	0
T3	28578	1	0	0
T4	46815	0	0	0
T5	70700	0	0	0
T6	22858	0	0	0
T10	68178	1	0	0
T11	37768	1	0	0
T12	93392	2	0	0
T14	21084	1	0	0
T15	0	2	0	0
T16	13988	0	0	0
T17	3430	1	0	0
T27	20224	1	0	0
T28	43692	1	0	0
T30	0	5	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	114295	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	4	0	0
T90	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2516	0	0
T2	18810	1	0	0
T3	28578	1	0	0
T4	46815	0	0	0
T5	70700	0	0	0
T6	22858	0	0	0
T10	68178	1	0	0
T11	37768	1	0	0
T12	93392	2	0	0
T14	21084	1	0	0
T15	0	2	0	0
T16	13988	0	0	0
T17	3430	1	0	0
T27	20224	1	0	0
T28	43692	1	0	0
T30	0	5	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	114295	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	4	0	0
T90	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2462	0	0
T2	9405	0	0	0
T3	19052	1	0	0
T4	31210	0	0	0
T5	70700	0	0	0
T6	45716	0	0	0
T7	38029	0	0	0
T10	45452	1	0	0
T11	37768	1	0	0
T12	93392	2	0	0
T14	15813	1	0	0
T15	0	2	0	0
T16	13988	0	0	0
T17	5145	1	0	0
T27	20224	1	0	0
T28	87384	1	0	0
T30	0	5	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	228590	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	4	0	0
T56	0	1	0	0
T90	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3561	0	0
T1	6924	1	0	0
T2	18810	1	0	0
T3	19052	0	0	0
T4	31210	0	0	0
T5	35350	0	0	0
T8	69898	0	0	0
T9	20610	0	0	0
T10	45452	0	0	0
T11	18884	0	0	0
T12	46696	0	0	0
T13	48878	3	0	0
T14	10542	0	0	0
T16	6994	0	0	0
T26	0	6	0	0
T27	5056	0	0	0
T30	80971	1	0	0
T31	25441	6	0	0
T37	0	18	0	0
T40	0	3	0	0
T41	0	1	0	0
T45	27207	0	0	0
T46	0	2	0	0
T52	95605	0	0	0
T53	0	1	0	0
T55	0	5	0	0
T57	0	1	0	0
T58	0	5	0	0
T73	0	1	0	0
T74	0	1	0	0
T86	0	1	0	0
T89	2582	0	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	2	0	0
T93	0	1	0	0
T94	199960	0	0	0
T95	98803	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	361673	0	0
T1	6924	195	0	0
T2	18810	68	0	0
T3	19052	0	0	0
T4	31210	0	0	0
T5	35350	0	0	0
T8	69898	0	0	0
T9	20610	0	0	0
T10	45452	0	0	0
T11	18884	0	0	0
T12	46696	0	0	0
T13	48878	430	0	0
T14	10542	0	0	0
T16	6994	0	0	0
T26	0	875	0	0
T27	5056	0	0	0
T30	80971	0	0	0
T31	25441	457	0	0
T37	0	3920	0	0
T40	0	516	0	0
T45	27207	0	0	0
T46	0	368	0	0
T47	0	41	0	0
T52	95605	0	0	0
T53	0	258	0	0
T55	0	388	0	0
T57	0	820	0	0
T58	0	749	0	0
T73	0	203	0	0
T74	0	456	0	0
T86	0	43	0	0
T89	2582	0	0	0
T90	0	212	0	0
T91	0	98	0	0
T92	0	219	0	0
T93	0	363	0	0
T94	199960	0	0	0
T95	98803	0	0	0
T96	0	804	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3187	0	0
T1	6924	1	0	0
T2	18810	1	0	0
T3	19052	0	0	0
T4	31210	0	0	0
T5	35350	0	0	0
T8	69898	0	0	0
T9	20610	0	0	0
T10	45452	0	0	0
T11	18884	0	0	0
T12	46696	0	0	0
T13	48878	2	0	0
T14	10542	0	0	0
T16	6994	0	0	0
T26	0	3	0	0
T27	5056	0	0	0
T30	80971	0	0	0
T31	25441	5	0	0
T37	0	14	0	0
T40	0	1	0	0
T45	27207	0	0	0
T46	0	2	0	0
T47	0	2	0	0
T52	95605	0	0	0
T55	0	4	0	0
T58	0	4	0	0
T59	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T80	0	1	0	0
T86	0	1	0	0
T89	2582	0	0	0
T91	0	1	0	0
T92	0	2	0	0
T93	0	1	0	0
T94	199960	0	0	0
T95	98803	0	0	0
T96	0	6	0	0
T97	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	235	0	0
T8	139796	0	0	0
T9	41220	0	0	0
T13	48878	1	0	0
T22	9298	0	0	0
T23	21880	0	0	0
T26	0	1	0	0
T30	161942	1	0	0
T31	50882	0	0	0
T37	0	1	0	0
T40	46010	2	0	0
T45	54414	0	0	0
T46	24973	0	0	0
T50	15564	0	0	0
T52	191210	0	0	0
T53	101131	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T61	0	1	0	0
T64	0	4	0	0
T83	34359	0	0	0
T86	0	1	0	0
T89	2582	0	0	0
T90	9197	1	0	0
T93	0	1	0	0
T94	399920	0	0	0
T95	197606	0	0	0
T96	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	2	0	0
T104	0	1	0	0
T105	21024	0	0	0
T106	26778	0	0	0
T107	47666	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3872	0	0
T5	70700	715	0	0
T6	91432	644	0	0
T7	152116	0	0	0
T9	0	632	0	0
T15	324244	0	0	0
T17	6860	0	0	0
T27	20224	0	0	0
T28	174768	0	0	0
T43	457180	0	0	0
T44	163844	0	0	0
T49	0	1242	0	0
T50	0	639	0	0
T51	145932	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3152	0	0
T5	70700	595	0	0
T6	91432	524	0	0
T7	152116	0	0	0
T9	0	512	0	0
T15	324244	0	0	0
T17	6860	0	0	0
T27	20224	0	0	0
T28	174768	0	0	0
T43	457180	0	0	0
T44	163844	0	0	0
T49	0	1002	0	0
T50	0	519	0	0
T51	145932	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	27696	27444	0	0
T2	37620	37276	0	0
T3	38104	37788	0	0
T4	62420	61872	0	0
T5	400	0	0	0
T10	90904	90700	0	0
T11	37768	37476	0	0
T12	93392	93012	0	0
T14	21084	20712	0	0
T16	13988	13616	0	0
T27	0	19832	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	27696	27444	0	0
T2	37620	37276	0	0
T3	38104	37788	0	0
T4	62420	61872	0	0
T5	70700	18916	0	0
T10	90904	90700	0	0
T11	37768	37476	0	0
T12	93392	93012	0	0
T14	21084	20712	0	0
T16	13988	13616	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T3 T10 T12 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T3 T10 T12 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T3 T10 T12 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T13 T31 
159        1/1                    state_d = TimeoutSt;
           Tests:       T2 T13 T31 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T2 T13 T31 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T2 T13 T31 
172        1/1                    state_d    = Phase0St;
           Tests:       T13 T31 T40 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T13 T31 T40 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T13 T31 T40 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T13 T31 T40 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T2 T13 T31 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T13 T31 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T2 T13 T31 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T13 T31 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T3 T10 T12 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T3 T10 T12 
190        1/1                  esc_state_o = Phase0;
           Tests:       T3 T10 T12 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T3 T10 T12 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
194        1/1                    state_d = IdleSt;
           Tests:       T13 T32 T33 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T32 T33 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T13 T32 T33 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
198        1/1                    state_d = Phase1St;
           Tests:       T3 T10 T12 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T10 T12 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T3 T10 T12 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T3 T10 T12 
207        1/1                  esc_state_o = Phase1;
           Tests:       T3 T10 T12 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T3 T10 T12 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
211        1/1                    state_d = IdleSt;
           Tests:       T34 T66 T108 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T66 T108 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T34 T66 T108 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
215        1/1                    state_d = Phase2St;
           Tests:       T3 T10 T12 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T10 T12 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T3 T10 T12 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T3 T10 T12 
224        1/1                  esc_state_o = Phase2;
           Tests:       T3 T10 T12 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T3 T10 T12 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
229        1/1                    state_d = IdleSt;
           Tests:       T37 T38 T109 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T37 T38 T109 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T37 T38 T109 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
233        1/1                    state_d = Phase3St;
           Tests:       T3 T10 T12 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T3 T10 T12 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T3 T10 T12 
241        1/1                  esc_state_o = Phase3;
           Tests:       T3 T10 T12 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T3 T10 T12 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
245        1/1                    state_d = IdleSt;
           Tests:       T34 T39 T83 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T39 T83 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T34 T39 T83 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
249        1/1                    state_d = TerminalSt;
           Tests:       T3 T10 T12 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T3 T10 T12 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
259        1/1                  esc_state_o = Terminal;
           Tests:       T3 T10 T12 
260        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
261        1/1                    state_d = IdleSt;
           Tests:       T12 T17 T31 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T5 T6 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T5 T6 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T5 T6 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T5 T6 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T9
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T10

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T10
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T10
1	0	1	Covered	T12,T27,T94
1	1	0	Covered	T2,T11,T16
1	1	1	Covered	T2,T13,T31

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T31
0	1	Covered	T13,T40,T53
1	0	Covered	T31,T26,T37

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T13,T31
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T31,T26,T37

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T31
1	0	Not Covered
1	1	Covered	T13,T40,T53

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T17
1	Covered	T10,T11,T27

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T12,T11
1	Covered	T3,T43,T30

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T12,T17,T94

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T12
1	Covered	T28,T26,T37

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T5,T6,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T10,T12,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T3,T11,T27

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T12,T27,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T3,T10,T27

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T6,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T10,T12
Phase1St	198	Covered	T3,T10,T12
Phase2St	215	Covered	T3,T10,T12
Phase3St	233	Covered	T3,T10,T12
TerminalSt	249	Covered	T3,T10,T12
TimeoutSt	159	Covered	T2,T13,T31

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T6,T9
IdleSt->Phase0St	152	Covered	T3,T10,T12
IdleSt->TimeoutSt	159	Covered	T2,T13,T31
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T13,T26,T47
Phase0St->Phase1St	198	Covered	T3,T10,T12
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T34,T64,T66
Phase1St->Phase2St	215	Covered	T3,T10,T12
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T37,T48,T38
Phase2St->Phase3St	233	Covered	T3,T10,T12
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T34,T39,T83
Phase3St->TerminalSt	249	Covered	T3,T10,T12
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T12,T17,T31
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T13,T31
TimeoutSt->Phase0St	172	Covered	T13,T31,T40

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T13,T31
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T13,T31,T40
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T13,T31
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T13,T31
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T13,T32,T33
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T10,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T10,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T34,T66,T108
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T10,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T10,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T37,T38,T109
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T10,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T10,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T34,T39,T83
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T10,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T10,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T12,T17,T31
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T10,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	554507586	171	0	0
CheckAccumTrig0_A	554507586	871	0	0
CheckAccumTrig1_A	554507586	61	0	0
CheckClr_A	554507586	474	0	0
CheckEn_A	554394044	205444603	0	0
CheckPhase0_A	554507586	962	0	0
CheckPhase1_A	554507586	935	0	0
CheckPhase2_A	554507586	907	0	0
CheckPhase3_A	554507586	882	0	0
CheckTimeout0_A	554507586	1013	0	0
CheckTimeoutSt1_A	554507586	93741	0	0
CheckTimeoutSt2_A	554507586	887	0	0
CheckTimeoutStTrig_A	554507586	61	0	0
ErrorStAllEscAsserted_A	554507586	976	0	0
ErrorStIsTerminal_A	554507586	796	0	0
EscStateOut_A	554392683	554319245	0	0
u_state_regs_A	554507586	554357095	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	171	0	0
T5	17675	18	0	0
T6	22858	41	0	0
T7	38029	0	0	0
T9	0	37	0	0
T15	81061	0	0	0
T17	1715	0	0	0
T27	5056	0	0	0
T28	43692	0	0	0
T43	114295	0	0	0
T44	40961	0	0	0
T49	0	47	0	0
T50	0	28	0	0
T51	36483	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	871	0	0
T3	9526	1	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	1	0	0
T11	9442	1	0	0
T12	23348	1	0	0
T14	5271	0	0	0
T16	3497	0	0	0
T17	1715	1	0	0
T27	5056	1	0	0
T28	0	1	0	0
T30	0	1	0	0
T43	0	1	0	0
T52	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	61	0	0
T22	9298	0	0	0
T26	0	1	0	0
T31	25441	1	0	0
T34	25781	0	0	0
T37	0	1	0	0
T39	37277	0	0	0
T41	17014	0	0	0
T49	38640	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0
T73	42134	0	0	0
T74	15413	0	0	0
T75	2871	0	0	0
T76	54675	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	474	0	0
T5	17675	0	0	0
T6	22858	0	0	0
T7	38029	0	0	0
T11	9442	0	0	0
T12	23348	1	0	0
T13	0	1	0	0
T16	3497	0	0	0
T17	1715	1	0	0
T27	5056	0	0	0
T28	43692	0	0	0
T31	0	1	0	0
T34	0	8	0	0
T39	0	1	0	0
T43	114295	0	0	0
T55	0	4	0	0
T83	0	5	0	0
T84	0	1	0	0
T85	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554394044	205444603	0	0
T1	6924	6860	0	0
T2	9405	6193	0	0
T3	9526	582	0	0
T4	15605	4185	0	0
T5	602	501	0	0
T10	22726	2040	0	0
T11	9442	6522	0	0
T12	23348	5847	0	0
T14	5271	3189	0	0
T16	3497	3403	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	962	0	0
T3	9526	1	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	1	0	0
T11	9442	1	0	0
T12	23348	1	0	0
T14	5271	0	0	0
T16	3497	0	0	0
T17	1715	1	0	0
T27	5056	1	0	0
T28	0	1	0	0
T30	0	1	0	0
T43	0	1	0	0
T52	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	935	0	0
T3	9526	1	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	1	0	0
T11	9442	1	0	0
T12	23348	1	0	0
T14	5271	0	0	0
T16	3497	0	0	0
T17	1715	1	0	0
T27	5056	1	0	0
T28	0	1	0	0
T30	0	1	0	0
T43	0	1	0	0
T52	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	907	0	0
T3	9526	1	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	1	0	0
T11	9442	1	0	0
T12	23348	1	0	0
T14	5271	0	0	0
T16	3497	0	0	0
T17	1715	1	0	0
T27	5056	1	0	0
T28	0	1	0	0
T30	0	1	0	0
T43	0	1	0	0
T52	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	882	0	0
T3	9526	1	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	1	0	0
T11	9442	1	0	0
T12	23348	1	0	0
T14	5271	0	0	0
T16	3497	0	0	0
T17	1715	1	0	0
T27	5056	1	0	0
T28	0	1	0	0
T30	0	1	0	0
T43	0	1	0	0
T52	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	1013	0	0
T2	9405	1	0	0
T3	9526	0	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	0	0	0
T11	9442	0	0	0
T12	23348	0	0	0
T13	0	2	0	0
T14	5271	0	0	0
T16	3497	0	0	0
T26	0	3	0	0
T27	5056	0	0	0
T31	0	4	0	0
T37	0	9	0	0
T40	0	1	0	0
T53	0	1	0	0
T55	0	5	0	0
T92	0	2	0	0
T93	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	93741	0	0
T2	9405	68	0	0
T3	9526	0	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	0	0	0
T11	9442	0	0	0
T12	23348	0	0	0
T13	0	245	0	0
T14	5271	0	0	0
T16	3497	0	0	0
T26	0	262	0	0
T27	5056	0	0	0
T31	0	297	0	0
T37	0	2567	0	0
T40	0	74	0	0
T53	0	258	0	0
T55	0	388	0	0
T92	0	219	0	0
T93	0	125	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	887	0	0
T2	9405	1	0	0
T3	9526	0	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	0	0	0
T11	9442	0	0	0
T12	23348	0	0	0
T13	0	1	0	0
T14	5271	0	0	0
T16	3497	0	0	0
T27	5056	0	0	0
T31	0	3	0	0
T37	0	6	0	0
T47	0	2	0	0
T55	0	4	0	0
T80	0	1	0	0
T92	0	2	0	0
T96	0	1	0	0
T97	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	61	0	0
T8	69898	0	0	0
T9	20610	0	0	0
T13	48878	1	0	0
T26	0	1	0	0
T30	80971	0	0	0
T31	25441	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T45	27207	0	0	0
T52	95605	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T86	0	1	0	0
T89	2582	0	0	0
T93	0	1	0	0
T94	199960	0	0	0
T95	98803	0	0	0
T96	0	1	0	0
T98	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	976	0	0
T5	17675	198	0	0
T6	22858	162	0	0
T7	38029	0	0	0
T9	0	169	0	0
T15	81061	0	0	0
T17	1715	0	0	0
T27	5056	0	0	0
T28	43692	0	0	0
T43	114295	0	0	0
T44	40961	0	0	0
T49	0	294	0	0
T50	0	153	0	0
T51	36483	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	796	0	0
T5	17675	168	0	0
T6	22858	132	0	0
T7	38029	0	0	0
T9	0	139	0	0
T15	81061	0	0	0
T17	1715	0	0	0
T27	5056	0	0	0
T28	43692	0	0	0
T43	114295	0	0	0
T44	40961	0	0	0
T49	0	234	0	0
T50	0	123	0	0
T51	36483	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554392683	554319245	0	0
T1	6924	6861	0	0
T2	9405	9319	0	0
T3	9526	9447	0	0
T4	15605	15468	0	0
T5	100	0	0	0
T10	22726	22675	0	0
T11	9442	9369	0	0
T12	23348	23253	0	0
T14	5271	5178	0	0
T16	3497	3404	0	0
T27	0	4958	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	554357095	0	0
T1	6924	6861	0	0
T2	9405	9319	0	0
T3	9526	9447	0	0
T4	15605	15468	0	0
T5	17675	4729	0	0
T10	22726	22675	0	0
T11	9442	9369	0	0
T12	23348	23253	0	0
T14	5271	5178	0	0
T16	3497	3404	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T2 T4 T12 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T2 T4 T12 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T2 T4 T12 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T13 T73 T74 
159        1/1                    state_d = TimeoutSt;
           Tests:       T13 T73 T74 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T13 T73 T74 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T13 T73 T74 
172        1/1                    state_d    = Phase0St;
           Tests:       T41 T40 T90 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T41 T40 T90 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T41 T40 T90 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T41 T40 T90 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T13 T73 T74 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T13 T73 T74 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T13 T73 T74 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T73 T74 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T12 T30 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T2 T12 T30 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T2 T12 T30 
190        1/1                  esc_state_o = Phase0;
           Tests:       T2 T12 T30 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T2 T12 T30 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T2 T12 T30 
194        1/1                    state_d = IdleSt;
           Tests:       T110 T111 T112 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T110 T111 T112 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T110 T111 T112 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T12 T30 
198        1/1                    state_d = Phase1St;
           Tests:       T2 T12 T30 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T12 T30 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T12 T30 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T12 T30 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T2 T12 T30 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T2 T12 T30 
207        1/1                  esc_state_o = Phase1;
           Tests:       T2 T12 T30 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T2 T12 T30 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T2 T12 T30 
211        1/1                    state_d = IdleSt;
           Tests:       T35 T36 T113 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T36 T113 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T35 T36 T113 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T12 T30 
215        1/1                    state_d = Phase2St;
           Tests:       T2 T12 T30 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T12 T30 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T12 T30 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T12 T30 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T2 T12 T30 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T2 T12 T30 
224        1/1                  esc_state_o = Phase2;
           Tests:       T2 T12 T30 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T2 T12 T30 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T2 T12 T30 
229        1/1                    state_d = IdleSt;
           Tests:       T2 T36 T114 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T36 T114 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T2 T36 T114 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T12 T30 
233        1/1                    state_d = Phase3St;
           Tests:       T2 T12 T30 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T12 T30 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T12 T30 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T2 T12 T30 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T2 T12 T30 
241        1/1                  esc_state_o = Phase3;
           Tests:       T2 T12 T30 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T2 T12 T30 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T2 T12 T30 
245        1/1                    state_d = IdleSt;
           Tests:       T2 T26 T115 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T26 T115 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T2 T26 T115 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T12 T30 
249        1/1                    state_d = TerminalSt;
           Tests:       T12 T30 T41 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T30 T41 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T12 T30 T41 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T12 T30 T41 
259        1/1                  esc_state_o = Terminal;
           Tests:       T12 T30 T41 
260        1/1                  if (clr_i) begin
           Tests:       T12 T30 T41 
261        1/1                    state_d = IdleSt;
           Tests:       T30 T41 T57 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T5 T6 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T5 T6 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T5 T6 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T5 T6 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T9
1	0	Covered	T2,T4,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T16
1	0	1	Covered	T17,T44,T94
1	1	0	Covered	T2,T16,T15
1	1	1	Covered	T13,T73,T74

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T13,T73,T74
0	1	Covered	T40,T90,T99
1	0	Covered	T41,T58,T62

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T13,T73,T74
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T41,T58,T62

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T73,T74
1	0	Not Covered
1	1	Covered	T40,T90,T99

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T12,T30
1	Covered	T90,T54,T57

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T12,T30
1	Covered	T40,T26,T86

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T40,T90
1	Covered	T2,T12,T30

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T12,T30
1	Covered	T46,T55,T56

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T5,T6,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T12,T30,T53

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T12,T30,T41

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T2,T12,T30

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T12,T30,T40

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T6,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T12,T30
Phase1St	198	Covered	T2,T12,T30
Phase2St	215	Covered	T2,T12,T30
Phase3St	233	Covered	T2,T12,T30
TerminalSt	249	Covered	T12,T30,T41
TimeoutSt	159	Covered	T13,T73,T74

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T6,T9
IdleSt->Phase0St	152	Covered	T2,T12,T30
IdleSt->TimeoutSt	159	Covered	T13,T73,T74
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T26,T32,T110
Phase0St->Phase1St	198	Covered	T2,T12,T30
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T35,T36,T113
Phase1St->Phase2St	215	Covered	T2,T12,T30
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T2,T36,T114
Phase2St->Phase3St	233	Covered	T2,T12,T30
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T2,T26,T115
Phase3St->TerminalSt	249	Covered	T12,T30,T41
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T30,T41,T55
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T13,T73,T74
TimeoutSt->Phase0St	172	Covered	T41,T40,T90

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T73,T74
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T41,T40,T90
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T13,T73,T74
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T13,T73,T74
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T110,T111,T112
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T12,T30
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T12,T30
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T35,T36,T113
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T12,T30
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T30,T41
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T36,T114
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T12,T30
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T12,T30
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T2,T26,T115
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T12,T30,T41
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T12,T30
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T30,T41,T57
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T12,T30,T41
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	554507586	188	0	0
CheckAccumTrig0_A	554507586	476	0	0
CheckAccumTrig1_A	554507586	27	0	0
CheckClr_A	554507586	216	0	0
CheckEn_A	554394044	230573210	0	0
CheckPhase0_A	554507586	548	0	0
CheckPhase1_A	554507586	535	0	0
CheckPhase2_A	554507586	525	0	0
CheckPhase3_A	554507586	517	0	0
CheckTimeout0_A	554507586	820	0	0
CheckTimeoutSt1_A	554507586	82154	0	0
CheckTimeoutSt2_A	554507586	727	0	0
CheckTimeoutStTrig_A	554507586	59	0	0
ErrorStAllEscAsserted_A	554507586	927	0	0
ErrorStIsTerminal_A	554507586	747	0	0
EscStateOut_A	554392683	554319245	0	0
u_state_regs_A	554507586	554357095	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	188	0	0
T5	17675	22	0	0
T6	22858	34	0	0
T7	38029	0	0	0
T9	0	31	0	0
T15	81061	0	0	0
T17	1715	0	0	0
T27	5056	0	0	0
T28	43692	0	0	0
T43	114295	0	0	0
T44	40961	0	0	0
T49	0	79	0	0
T50	0	22	0	0
T51	36483	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	476	0	0
T2	9405	2	0	0
T3	9526	0	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	0	0	0
T11	9442	0	0	0
T12	23348	1	0	0
T14	5271	0	0	0
T16	3497	0	0	0
T27	5056	0	0	0
T30	0	2	0	0
T41	0	1	0	0
T46	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	3	0	0
T56	0	1	0	0
T57	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	27	0	0
T18	432216	0	0	0
T23	21880	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T39	37277	0	0	0
T40	46010	0	0	0
T41	17014	1	0	0
T49	38640	0	0	0
T50	15564	0	0	0
T58	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	1	0	0
T76	54675	0	0	0
T77	111285	0	0	0
T78	3301	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	216	0	0
T2	9405	2	0	0
T3	9526	0	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	0	0	0
T11	9442	0	0	0
T12	23348	0	0	0
T14	5271	0	0	0
T16	3497	0	0	0
T26	0	2	0	0
T27	5056	0	0	0
T30	0	1	0	0
T37	0	1	0	0
T41	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554394044	230573210	0	0
T1	6924	6860	0	0
T2	9405	5823	0	0
T3	9526	8434	0	0
T4	15605	4207	0	0
T5	602	501	0	0
T10	22726	22674	0	0
T11	9442	9368	0	0
T12	23348	2112	0	0
T14	5271	3213	0	0
T16	3497	1080	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	548	0	0
T2	9405	2	0	0
T3	9526	0	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	0	0	0
T11	9442	0	0	0
T12	23348	1	0	0
T14	5271	0	0	0
T16	3497	0	0	0
T27	5056	0	0	0
T30	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T46	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	3	0	0
T90	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	535	0	0
T2	9405	2	0	0
T3	9526	0	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	0	0	0
T11	9442	0	0	0
T12	23348	1	0	0
T14	5271	0	0	0
T16	3497	0	0	0
T27	5056	0	0	0
T30	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T46	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	3	0	0
T90	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	525	0	0
T2	9405	1	0	0
T3	9526	0	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	0	0	0
T11	9442	0	0	0
T12	23348	1	0	0
T14	5271	0	0	0
T16	3497	0	0	0
T27	5056	0	0	0
T30	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T46	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	3	0	0
T90	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	517	0	0
T5	17675	0	0	0
T6	22858	0	0	0
T7	38029	0	0	0
T11	9442	0	0	0
T12	23348	1	0	0
T16	3497	0	0	0
T17	1715	0	0	0
T27	5056	0	0	0
T28	43692	0	0	0
T30	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	114295	0	0	0
T46	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	3	0	0
T56	0	1	0	0
T90	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	820	0	0
T8	69898	0	0	0
T9	20610	0	0	0
T13	48878	1	0	0
T26	0	2	0	0
T30	80971	0	0	0
T31	25441	0	0	0
T37	0	6	0	0
T40	0	2	0	0
T41	0	1	0	0
T45	27207	0	0	0
T52	95605	0	0	0
T58	0	5	0	0
T73	0	1	0	0
T74	0	1	0	0
T89	2582	0	0	0
T90	0	1	0	0
T91	0	1	0	0
T94	199960	0	0	0
T95	98803	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	82154	0	0
T8	69898	0	0	0
T9	20610	0	0	0
T13	48878	185	0	0
T26	0	340	0	0
T30	80971	0	0	0
T31	25441	0	0	0
T37	0	838	0	0
T40	0	442	0	0
T45	27207	0	0	0
T52	95605	0	0	0
T58	0	749	0	0
T73	0	203	0	0
T74	0	456	0	0
T89	2582	0	0	0
T90	0	212	0	0
T91	0	98	0	0
T93	0	238	0	0
T94	199960	0	0	0
T95	98803	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	727	0	0
T8	69898	0	0	0
T9	20610	0	0	0
T13	48878	1	0	0
T26	0	2	0	0
T30	80971	0	0	0
T31	25441	0	0	0
T37	0	5	0	0
T40	0	1	0	0
T45	27207	0	0	0
T52	95605	0	0	0
T58	0	4	0	0
T73	0	1	0	0
T74	0	1	0	0
T89	2582	0	0	0
T91	0	1	0	0
T93	0	1	0	0
T94	199960	0	0	0
T95	98803	0	0	0
T96	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	59	0	0
T23	21880	0	0	0
T40	46010	1	0	0
T46	24973	0	0	0
T50	15564	0	0	0
T53	101131	0	0	0
T61	0	1	0	0
T64	0	1	0	0
T83	34359	0	0	0
T90	9197	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	21024	0	0	0
T106	26778	0	0	0
T107	47666	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	927	0	0
T5	17675	155	0	0
T6	22858	162	0	0
T7	38029	0	0	0
T9	0	134	0	0
T15	81061	0	0	0
T17	1715	0	0	0
T27	5056	0	0	0
T28	43692	0	0	0
T43	114295	0	0	0
T44	40961	0	0	0
T49	0	335	0	0
T50	0	141	0	0
T51	36483	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	747	0	0
T5	17675	125	0	0
T6	22858	132	0	0
T7	38029	0	0	0
T9	0	104	0	0
T15	81061	0	0	0
T17	1715	0	0	0
T27	5056	0	0	0
T28	43692	0	0	0
T43	114295	0	0	0
T44	40961	0	0	0
T49	0	275	0	0
T50	0	111	0	0
T51	36483	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554392683	554319245	0	0
T1	6924	6861	0	0
T2	9405	9319	0	0
T3	9526	9447	0	0
T4	15605	15468	0	0
T5	100	0	0	0
T10	22726	22675	0	0
T11	9442	9369	0	0
T12	23348	23253	0	0
T14	5271	5178	0	0
T16	3497	3404	0	0
T27	0	4958	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	554357095	0	0
T1	6924	6861	0	0
T2	9405	9319	0	0
T3	9526	9447	0	0
T4	15605	15468	0	0
T5	17675	4729	0	0
T10	22726	22675	0	0
T11	9442	9369	0	0
T12	23348	23253	0	0
T14	5271	5178	0	0
T16	3497	3404	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T14 T15 T44 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T14 T15 T44 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T14 T15 T44 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T30 T31 
159        1/1                    state_d = TimeoutSt;
           Tests:       T1 T30 T31 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T1 T30 T31 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T1 T30 T31 
172        1/1                    state_d    = Phase0St;
           Tests:       T30 T57 T47 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T30 T57 T47 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T30 T57 T47 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T30 T57 T47 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T1 T31 T46 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T31 T46 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T1 T31 T46 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T31 T46 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T14 T15 T44 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T14 T15 T44 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T14 T15 T44 
190        1/1                  esc_state_o = Phase0;
           Tests:       T14 T15 T44 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T14 T15 T44 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T14 T15 T44 
194        1/1                    state_d = IdleSt;
           Tests:       T35 T116 T117 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T116 T117 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T35 T116 T117 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T14 T15 T44 
198        1/1                    state_d = Phase1St;
           Tests:       T14 T15 T44 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T14 T15 T44 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T14 T15 T44 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T14 T15 T44 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T14 T15 T44 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T14 T15 T44 
207        1/1                  esc_state_o = Phase1;
           Tests:       T14 T15 T44 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T14 T15 T44 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T14 T15 T44 
211        1/1                    state_d = IdleSt;
           Tests:       T118 T119 T112 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T118 T119 T112 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T118 T119 T112 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T14 T15 T44 
215        1/1                    state_d = Phase2St;
           Tests:       T14 T15 T44 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T14 T15 T44 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T14 T15 T44 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T14 T15 T44 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T14 T15 T44 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T14 T15 T44 
224        1/1                  esc_state_o = Phase2;
           Tests:       T14 T15 T44 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T14 T15 T44 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T14 T15 T44 
229        1/1                    state_d = IdleSt;
           Tests:       T35 T120 T121 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T120 T121 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T35 T120 T121 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T14 T15 T44 
233        1/1                    state_d = Phase3St;
           Tests:       T14 T15 T44 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T14 T15 T44 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T14 T15 T44 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T14 T15 T44 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T14 T15 T44 
241        1/1                  esc_state_o = Phase3;
           Tests:       T14 T15 T44 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T14 T15 T44 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T14 T15 T44 
245        1/1                    state_d = IdleSt;
           Tests:       T122 T123 T124 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T122 T123 T124 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T122 T123 T124 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T14 T15 T44 
249        1/1                    state_d = TerminalSt;
           Tests:       T14 T15 T44 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T14 T15 T44 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T14 T15 T44 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T14 T15 T44 
259        1/1                  esc_state_o = Terminal;
           Tests:       T14 T15 T44 
260        1/1                  if (clr_i) begin
           Tests:       T14 T15 T44 
261        1/1                    state_d = IdleSt;
           Tests:       T15 T30 T26 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T5 T6 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T5 T6 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T5 T6 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T5 T6 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T14,T15
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T44
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T14,T15

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T14,T15,T44

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T14,T12,T44
1	1	0	Covered	T2,T12,T16
1	1	1	Covered	T1,T30,T31

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T31,T46
0	1	Covered	T30,T57,T47
1	0	Covered	T59,T115,T125

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T30,T31
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T59,T115,T125

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T31,T46
1	0	Not Covered
1	1	Covered	T30,T57,T47

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T44,T30,T45
1	Covered	T14,T15,T30

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T14,T15,T30
1	Covered	T44,T30,T31

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T14,T15,T44
1	Covered	T58,T126,T48

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T14,T15,T44
1	Covered	T45,T26,T37

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T5,T6,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T14,T15,T44

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T14,T15,T44

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T14,T75,T127

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T14,T44,T30

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T6,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T14,T15,T44
Phase1St	198	Covered	T14,T15,T44
Phase2St	215	Covered	T14,T15,T44
Phase3St	233	Covered	T14,T15,T44
TerminalSt	249	Covered	T14,T15,T44
TimeoutSt	159	Covered	T1,T30,T31

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T6,T9
IdleSt->Phase0St	152	Covered	T14,T15,T44
IdleSt->TimeoutSt	159	Covered	T1,T30,T31
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T47,T35,T66
Phase0St->Phase1St	198	Covered	T14,T15,T44
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T118,T119,T112
Phase1St->Phase2St	215	Covered	T14,T15,T44
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T35,T120,T128
Phase2St->Phase3St	233	Covered	T14,T15,T44
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T122,T123,T124
Phase3St->TerminalSt	249	Covered	T14,T15,T44
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T15,T30,T55
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T31,T46
TimeoutSt->Phase0St	172	Covered	T30,T57,T47

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T44
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T30,T31
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T30,T57,T47
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T31,T46
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T31,T46
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T35,T116,T117
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T14,T15,T44
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T15,T44,T30
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T118,T119,T112
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T14,T15,T44
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T15,T44,T30
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T35,T120,T121
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T14,T15,T44
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T15,T44,T30
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T122,T123,T124
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T14,T15,T44
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T15,T44,T30
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T15,T30,T26
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T14,T15,T44
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	554507586	217	0	0
CheckAccumTrig0_A	554507586	497	0	0
CheckAccumTrig1_A	554507586	21	0	0
CheckClr_A	554507586	241	0	0
CheckEn_A	554394044	256409559	0	0
CheckPhase0_A	554507586	563	0	0
CheckPhase1_A	554507586	550	0	0
CheckPhase2_A	554507586	537	0	0
CheckPhase3_A	554507586	526	0	0
CheckTimeout0_A	554507586	882	0	0
CheckTimeoutSt1_A	554507586	90440	0	0
CheckTimeoutSt2_A	554507586	803	0	0
CheckTimeoutStTrig_A	554507586	57	0	0
ErrorStAllEscAsserted_A	554507586	958	0	0
ErrorStIsTerminal_A	554507586	778	0	0
EscStateOut_A	554392683	554319245	0	0
u_state_regs_A	554507586	554357095	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	217	0	0
T5	17675	35	0	0
T6	22858	34	0	0
T7	38029	0	0	0
T9	0	45	0	0
T15	81061	0	0	0
T17	1715	0	0	0
T27	5056	0	0	0
T28	43692	0	0	0
T43	114295	0	0	0
T44	40961	0	0	0
T49	0	48	0	0
T50	0	55	0	0
T51	36483	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	497	0	0
T5	17675	0	0	0
T6	22858	0	0	0
T11	9442	0	0	0
T12	23348	0	0	0
T14	5271	1	0	0
T15	0	2	0	0
T16	3497	0	0	0
T17	1715	0	0	0
T18	0	1	0	0
T27	5056	0	0	0
T28	43692	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T43	114295	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T55	0	1	0	0
T75	0	1	0	0
T127	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	21	0	0
T38	20345	0	0	0
T59	25276	1	0	0
T79	162186	0	0	0
T80	80472	0	0	0
T81	8763	0	0	0
T82	3334	0	0	0
T88	67503	0	0	0
T115	0	1	0	0
T125	0	1	0	0
T129	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	0	1	0	0
T136	741779	0	0	0
T137	334504	0	0	0
T138	153495	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	241	0	0
T8	69898	0	0	0
T9	20610	0	0	0
T13	48878	0	0	0
T15	81061	1	0	0
T26	0	2	0	0
T30	80971	1	0	0
T37	0	1	0	0
T44	40961	0	0	0
T45	27207	0	0	0
T48	0	1	0	0
T52	95605	0	0	0
T60	0	1	0	0
T86	0	1	0	0
T88	0	2	0	0
T89	2582	0	0	0
T94	199960	0	0	0
T126	0	1	0	0
T139	0	4	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554394044	256409559	0	0
T1	6924	3834	0	0
T2	9405	8235	0	0
T3	9526	8434	0	0
T4	15605	4232	0	0
T5	602	501	0	0
T10	22726	22674	0	0
T11	9442	9368	0	0
T12	23348	19542	0	0
T14	5271	3236	0	0
T16	3497	3403	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	563	0	0
T5	17675	0	0	0
T6	22858	0	0	0
T11	9442	0	0	0
T12	23348	0	0	0
T14	5271	1	0	0
T15	0	2	0	0
T16	3497	0	0	0
T17	1715	0	0	0
T18	0	1	0	0
T27	5056	0	0	0
T28	43692	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T43	114295	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T75	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	550	0	0
T5	17675	0	0	0
T6	22858	0	0	0
T11	9442	0	0	0
T12	23348	0	0	0
T14	5271	1	0	0
T15	0	2	0	0
T16	3497	0	0	0
T17	1715	0	0	0
T18	0	1	0	0
T27	5056	0	0	0
T28	43692	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T43	114295	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T75	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	537	0	0
T5	17675	0	0	0
T6	22858	0	0	0
T11	9442	0	0	0
T12	23348	0	0	0
T14	5271	1	0	0
T15	0	2	0	0
T16	3497	0	0	0
T17	1715	0	0	0
T18	0	1	0	0
T27	5056	0	0	0
T28	43692	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T43	114295	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T75	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	526	0	0
T5	17675	0	0	0
T6	22858	0	0	0
T11	9442	0	0	0
T12	23348	0	0	0
T14	5271	1	0	0
T15	0	2	0	0
T16	3497	0	0	0
T17	1715	0	0	0
T18	0	1	0	0
T27	5056	0	0	0
T28	43692	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T43	114295	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T75	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	882	0	0
T1	6924	1	0	0
T2	9405	0	0	0
T3	9526	0	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	0	0	0
T11	9442	0	0	0
T12	23348	0	0	0
T14	5271	0	0	0
T16	3497	0	0	0
T26	0	1	0	0
T30	0	1	0	0
T31	0	2	0	0
T37	0	3	0	0
T46	0	2	0	0
T47	0	1	0	0
T57	0	1	0	0
T86	0	1	0	0
T96	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	90440	0	0
T1	6924	195	0	0
T2	9405	0	0	0
T3	9526	0	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	0	0	0
T11	9442	0	0	0
T12	23348	0	0	0
T14	5271	0	0	0
T16	3497	0	0	0
T26	0	273	0	0
T31	0	160	0	0
T37	0	515	0	0
T46	0	368	0	0
T47	0	41	0	0
T57	0	820	0	0
T86	0	43	0	0
T96	0	804	0	0
T97	0	151	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	803	0	0
T1	6924	1	0	0
T2	9405	0	0	0
T3	9526	0	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	0	0	0
T11	9442	0	0	0
T12	23348	0	0	0
T14	5271	0	0	0
T16	3497	0	0	0
T26	0	1	0	0
T31	0	2	0	0
T37	0	3	0	0
T46	0	2	0	0
T59	0	1	0	0
T86	0	1	0	0
T88	0	1	0	0
T96	0	4	0	0
T97	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	57	0	0
T8	69898	0	0	0
T9	20610	0	0	0
T22	9298	0	0	0
T30	80971	1	0	0
T31	25441	0	0	0
T34	25781	0	0	0
T45	27207	0	0	0
T47	0	1	0	0
T52	95605	0	0	0
T57	0	1	0	0
T64	0	3	0	0
T88	0	1	0	0
T94	199960	0	0	0
T95	98803	0	0	0
T103	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	4	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	958	0	0
T5	17675	177	0	0
T6	22858	142	0	0
T7	38029	0	0	0
T9	0	165	0	0
T15	81061	0	0	0
T17	1715	0	0	0
T27	5056	0	0	0
T28	43692	0	0	0
T43	114295	0	0	0
T44	40961	0	0	0
T49	0	296	0	0
T50	0	178	0	0
T51	36483	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	778	0	0
T5	17675	147	0	0
T6	22858	112	0	0
T7	38029	0	0	0
T9	0	135	0	0
T15	81061	0	0	0
T17	1715	0	0	0
T27	5056	0	0	0
T28	43692	0	0	0
T43	114295	0	0	0
T44	40961	0	0	0
T49	0	236	0	0
T50	0	148	0	0
T51	36483	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554392683	554319245	0	0
T1	6924	6861	0	0
T2	9405	9319	0	0
T3	9526	9447	0	0
T4	15605	15468	0	0
T5	100	0	0	0
T10	22726	22675	0	0
T11	9442	9369	0	0
T12	23348	23253	0	0
T14	5271	5178	0	0
T16	3497	3404	0	0
T27	0	4958	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	554357095	0	0
T1	6924	6861	0	0
T2	9405	9319	0	0
T3	9526	9447	0	0
T4	15605	15468	0	0
T5	17675	4729	0	0
T10	22726	22675	0	0
T11	9442	9369	0	0
T12	23348	23253	0	0
T14	5271	5178	0	0
T16	3497	3404	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T2 T15 T89 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T2 T15 T89 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T2 T15 T89 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T16 T13 
159        1/1                    state_d = TimeoutSt;
           Tests:       T2 T16 T13 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T2 T16 T13 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T2 T16 T13 
172        1/1                    state_d    = Phase0St;
           Tests:       T16 T13 T74 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T16 T13 T74 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T16 T13 T74 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T16 T13 T74 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T2 T16 T13 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T16 T13 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T2 T13 T31 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T13 T31 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T16 T15 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T2 T16 T15 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T2 T16 T15 
190        1/1                  esc_state_o = Phase0;
           Tests:       T2 T16 T15 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T2 T16 T15 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T2 T16 T15 
194        1/1                    state_d = IdleSt;
           Tests:       T144 T145 T146 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T144 T145 T146 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T144 T145 T146 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T16 T15 
198        1/1                    state_d = Phase1St;
           Tests:       T2 T16 T15 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T16 T15 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T16 T15 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T16 T15 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T2 T16 T15 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T2 T16 T15 
207        1/1                  esc_state_o = Phase1;
           Tests:       T2 T16 T15 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T2 T16 T15 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T2 T16 T15 
211        1/1                    state_d = IdleSt;
           Tests:       T147 T148 T149 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T147 T148 T149 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T147 T148 T149 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T16 T15 
215        1/1                    state_d = Phase2St;
           Tests:       T2 T16 T15 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T16 T15 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T16 T15 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T16 T15 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T2 T16 T15 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T2 T16 T15 
224        1/1                  esc_state_o = Phase2;
           Tests:       T2 T16 T15 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T2 T16 T15 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T2 T16 T15 
229        1/1                    state_d = IdleSt;
           Tests:       T48 T150 T144 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T48 T150 T144 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T48 T150 T144 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T16 T15 
233        1/1                    state_d = Phase3St;
           Tests:       T2 T16 T15 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T16 T15 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T16 T15 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T2 T16 T15 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T2 T16 T15 
241        1/1                  esc_state_o = Phase3;
           Tests:       T2 T16 T15 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T2 T16 T15 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T2 T16 T15 
245        1/1                    state_d = IdleSt;
           Tests:       T151 T152 T153 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T151 T152 T153 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T151 T152 T153 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T16 T15 
249        1/1                    state_d = TerminalSt;
           Tests:       T2 T16 T15 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T16 T15 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T2 T16 T15 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T2 T16 T15 
259        1/1                  esc_state_o = Terminal;
           Tests:       T2 T16 T15 
260        1/1                  if (clr_i) begin
           Tests:       T2 T16 T15 
261        1/1                    state_d = IdleSt;
           Tests:       T16 T31 T53 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T5 T6 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T5 T6 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T5 T6 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T5 T6 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T9
1	0	Covered	T2,T16,T15
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T16,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T16,T15

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T15,T89

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T11
1	0	1	Covered	T89,T94,T78
1	1	0	Covered	T13,T45,T73
1	1	1	Covered	T2,T16,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T16,T13
0	1	Covered	T16,T13,T53
1	0	Covered	T74,T53,T58

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T16,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T74,T53,T58

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T16,T13
1	0	Covered	T42
1	1	Covered	T16,T13,T74

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T16,T15
1	Covered	T89,T30,T94

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T13,T89,T30
1	Covered	T2,T16,T15

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T16,T15
1	Covered	T26,T20,T136

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T16,T15
1	Covered	T13,T31,T53

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T5,T6,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T2,T89,T94

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T16,T15,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T16,T15,T89

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T16,T15,T13

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T6,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T16,T15
Phase1St	198	Covered	T2,T16,T15
Phase2St	215	Covered	T2,T16,T15
Phase3St	233	Covered	T2,T16,T15
TerminalSt	249	Covered	T2,T16,T15
TimeoutSt	159	Covered	T2,T16,T13

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T6,T9
IdleSt->Phase0St	152	Covered	T2,T15,T89
IdleSt->TimeoutSt	159	Covered	T2,T16,T13
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T66,T154,T144
Phase0St->Phase1St	198	Covered	T2,T16,T15
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T37,T147,T128
Phase1St->Phase2St	215	Covered	T2,T16,T15
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T48,T150,T144
Phase2St->Phase3St	233	Covered	T2,T16,T15
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T151,T152,T153
Phase3St->TerminalSt	249	Covered	T2,T16,T15
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T16,T31,T53
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T13,T31
TimeoutSt->Phase0St	172	Covered	T16,T13,T74

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T15,T89
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T16,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T16,T13,T74
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T16,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T13,T31
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T144,T145,T146
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T16,T15
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T16,T15
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T147,T148,T149
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T16,T15
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T16,T15
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T48,T150,T144
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T16,T15
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T16,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T151,T152,T153
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T16,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T16,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T16,T31,T53
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T16,T15
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	554507586	185	0	0
CheckAccumTrig0_A	554507586	507	0	0
CheckAccumTrig1_A	554507586	16	0	0
CheckClr_A	554507586	243	0	0
CheckEn_A	554394044	241028878	0	0
CheckPhase0_A	554507586	568	0	0
CheckPhase1_A	554507586	559	0	0
CheckPhase2_A	554507586	547	0	0
CheckPhase3_A	554507586	537	0	0
CheckTimeout0_A	554507586	846	0	0
CheckTimeoutSt1_A	554507586	95338	0	0
CheckTimeoutSt2_A	554507586	770	0	0
CheckTimeoutStTrig_A	554507586	58	0	0
ErrorStAllEscAsserted_A	554507586	1011	0	0
ErrorStIsTerminal_A	554507586	831	0	0
EscStateOut_A	554392683	554319245	0	0
u_state_regs_A	554507586	554357095	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	185	0	0
T5	17675	30	0	0
T6	22858	28	0	0
T7	38029	0	0	0
T9	0	24	0	0
T15	81061	0	0	0
T17	1715	0	0	0
T27	5056	0	0	0
T28	43692	0	0	0
T43	114295	0	0	0
T44	40961	0	0	0
T49	0	65	0	0
T50	0	38	0	0
T51	36483	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	507	0	0
T2	9405	1	0	0
T3	9526	0	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	0	0	0
T11	9442	0	0	0
T12	23348	0	0	0
T14	5271	0	0	0
T15	0	1	0	0
T16	3497	0	0	0
T27	5056	0	0	0
T30	0	1	0	0
T31	0	3	0	0
T46	0	1	0	0
T55	0	1	0	0
T78	0	1	0	0
T84	0	2	0	0
T89	0	1	0	0
T94	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	16	0	0
T18	432216	0	0	0
T35	0	1	0	0
T39	37277	0	0	0
T40	46010	0	0	0
T41	17014	0	0	0
T49	38640	0	0	0
T53	0	1	0	0
T74	15413	1	0	0
T75	2871	0	0	0
T76	54675	0	0	0
T77	111285	0	0	0
T78	3301	0	0	0
T87	0	1	0	0
T149	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	243	0	0
T5	17675	0	0	0
T6	22858	0	0	0
T7	38029	0	0	0
T15	81061	0	0	0
T16	3497	1	0	0
T17	1715	0	0	0
T26	0	1	0	0
T27	5056	0	0	0
T28	43692	0	0	0
T31	0	2	0	0
T37	0	3	0	0
T43	114295	0	0	0
T48	0	2	0	0
T51	36483	0	0	0
T53	0	1	0	0
T57	0	1	0	0
T84	0	1	0	0
T87	0	1	0	0
T126	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554394044	241028878	0	0
T1	6924	3854	0	0
T2	9405	2706	0	0
T3	9526	9446	0	0
T4	15605	4243	0	0
T5	602	501	0	0
T10	22726	22674	0	0
T11	9442	4919	0	0
T12	23348	23252	0	0
T14	5271	3259	0	0
T16	3497	1080	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	568	0	0
T2	9405	1	0	0
T3	9526	0	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	0	0	0
T11	9442	0	0	0
T12	23348	0	0	0
T13	0	1	0	0
T14	5271	0	0	0
T15	0	1	0	0
T16	3497	1	0	0
T27	5056	0	0	0
T30	0	1	0	0
T31	0	3	0	0
T74	0	1	0	0
T78	0	1	0	0
T89	0	1	0	0
T94	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	559	0	0
T2	9405	1	0	0
T3	9526	0	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	0	0	0
T11	9442	0	0	0
T12	23348	0	0	0
T13	0	1	0	0
T14	5271	0	0	0
T15	0	1	0	0
T16	3497	1	0	0
T27	5056	0	0	0
T30	0	1	0	0
T31	0	3	0	0
T74	0	1	0	0
T78	0	1	0	0
T89	0	1	0	0
T94	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	547	0	0
T2	9405	1	0	0
T3	9526	0	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	0	0	0
T11	9442	0	0	0
T12	23348	0	0	0
T13	0	1	0	0
T14	5271	0	0	0
T15	0	1	0	0
T16	3497	1	0	0
T27	5056	0	0	0
T30	0	1	0	0
T31	0	3	0	0
T74	0	1	0	0
T78	0	1	0	0
T89	0	1	0	0
T94	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	537	0	0
T2	9405	1	0	0
T3	9526	0	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	0	0	0
T11	9442	0	0	0
T12	23348	0	0	0
T13	0	1	0	0
T14	5271	0	0	0
T15	0	1	0	0
T16	3497	1	0	0
T27	5056	0	0	0
T30	0	1	0	0
T31	0	3	0	0
T74	0	1	0	0
T78	0	1	0	0
T89	0	1	0	0
T94	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	846	0	0
T2	9405	1	0	0
T3	9526	0	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	0	0	0
T11	9442	0	0	0
T12	23348	0	0	0
T13	0	2	0	0
T14	5271	0	0	0
T16	3497	1	0	0
T27	5056	0	0	0
T31	0	5	0	0
T37	0	6	0	0
T40	0	2	0	0
T53	0	3	0	0
T58	0	1	0	0
T74	0	1	0	0
T105	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	95338	0	0
T2	9405	66	0	0
T3	9526	0	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	0	0	0
T11	9442	0	0	0
T12	23348	0	0	0
T13	0	294	0	0
T14	5271	0	0	0
T16	3497	84	0	0
T27	5056	0	0	0
T31	0	433	0	0
T37	0	1329	0	0
T40	0	376	0	0
T53	0	557	0	0
T58	0	196	0	0
T74	0	4	0	0
T105	0	726	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	770	0	0
T2	9405	1	0	0
T3	9526	0	0	0
T4	15605	0	0	0
T5	17675	0	0	0
T10	22726	0	0	0
T11	9442	0	0	0
T12	23348	0	0	0
T13	0	1	0	0
T14	5271	0	0	0
T16	3497	0	0	0
T27	5056	0	0	0
T31	0	5	0	0
T37	0	5	0	0
T40	0	2	0	0
T47	0	1	0	0
T53	0	1	0	0
T58	0	1	0	0
T105	0	6	0	0
T126	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	58	0	0
T5	17675	0	0	0
T6	22858	0	0	0
T7	38029	0	0	0
T13	0	1	0	0
T15	81061	0	0	0
T16	3497	1	0	0
T17	1715	0	0	0
T27	5056	0	0	0
T28	43692	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T43	114295	0	0	0
T51	36483	0	0	0
T53	0	1	0	0
T61	0	1	0	0
T74	0	1	0	0
T93	0	1	0	0
T102	0	1	0	0
T143	0	3	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	1011	0	0
T5	17675	185	0	0
T6	22858	178	0	0
T7	38029	0	0	0
T9	0	164	0	0
T15	81061	0	0	0
T17	1715	0	0	0
T27	5056	0	0	0
T28	43692	0	0	0
T43	114295	0	0	0
T44	40961	0	0	0
T49	0	317	0	0
T50	0	167	0	0
T51	36483	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	831	0	0
T5	17675	155	0	0
T6	22858	148	0	0
T7	38029	0	0	0
T9	0	134	0	0
T15	81061	0	0	0
T17	1715	0	0	0
T27	5056	0	0	0
T28	43692	0	0	0
T43	114295	0	0	0
T44	40961	0	0	0
T49	0	257	0	0
T50	0	137	0	0
T51	36483	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554392683	554319245	0	0
T1	6924	6861	0	0
T2	9405	9319	0	0
T3	9526	9447	0	0
T4	15605	15468	0	0
T5	100	0	0	0
T10	22726	22675	0	0
T11	9442	9369	0	0
T12	23348	23253	0	0
T14	5271	5178	0	0
T16	3497	3404	0	0
T27	0	4958	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554507586	554357095	0	0
T1	6924	6861	0	0
T2	9405	9319	0	0
T3	9526	9447	0	0
T4	15605	15468	0	0
T5	17675	4729	0	0
T10	22726	22675	0	0
T11	9442	9369	0	0
T12	23348	23253	0	0
T14	5271	5178	0	0
T16	3497	3404	0	0