Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52485502	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24868767

1

T1

82

T2

134

T3

433

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	12332078	1			T1	13		T2	73		T3	156
values[0x0]	32429437	1			T1	162		T2	204		T3	662
values[0x1]	32592754	1			T1	147		T2	176		T3	603

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45659431	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

31694838

1

T1

108

T2

179

T3

548

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	231239	1			T2	1		T3	4		T9	12
valid_sources[0x01]	314734	1			T2	4		T3	2		T9	4
valid_sources[0x02]	241644	1			T2	22		T3	7		T9	34
valid_sources[0x03]	234339	1			T3	5		T9	20		T11	1
valid_sources[0x04]	226635	1			T3	8		T9	40		T16	5
valid_sources[0x05]	236161	1			T2	4		T3	7		T9	2
valid_sources[0x06]	235930	1			T2	11		T3	5		T9	12
valid_sources[0x07]	683266	1			T3	4		T9	25		T16	4
valid_sources[0x08]	234071	1			T3	1		T9	50		T16	4
valid_sources[0x09]	222451	1			T3	7		T9	37		T11	3
valid_sources[0x0a]	222390	1			T3	7		T9	5		T16	2
valid_sources[0x0b]	226643	1			T2	12		T3	11		T9	5
valid_sources[0x0c]	226388	1			T3	5		T9	22		T11	5
valid_sources[0x0d]	1066538	1			T3	6		T9	37		T11	2
valid_sources[0x0e]	227864	1			T2	6		T3	3		T9	10
valid_sources[0x0f]	228057	1			T3	4		T11	3		T16	1
valid_sources[0x10]	234890	1			T3	5		T9	5		T11	1
valid_sources[0x11]	236192	1			T2	1		T3	6		T9	31
valid_sources[0x12]	229789	1			T2	7		T3	4		T9	31
valid_sources[0x13]	719217	1			T3	7		T9	22		T11	2
valid_sources[0x14]	223708	1			T2	1		T3	9		T9	39
valid_sources[0x15]	226813	1			T3	2		T11	6		T16	1
valid_sources[0x16]	225502	1			T3	3		T9	40		T16	6
valid_sources[0x17]	239194	1			T3	8		T11	2		T16	2
valid_sources[0x18]	227957	1			T3	6		T9	24		T11	5
valid_sources[0x19]	228858	1			T2	5		T3	3		T9	69
valid_sources[0x1a]	229822	1			T3	2		T9	109		T11	3
valid_sources[0x1b]	229626	1			T3	7		T9	39		T16	5
valid_sources[0x1c]	226474	1			T2	7		T3	3		T9	23
valid_sources[0x1d]	445292	1			T2	6		T3	9		T9	5
valid_sources[0x1e]	231244	1			T3	6		T9	33		T11	1
valid_sources[0x1f]	228065	1			T3	5		T11	3		T16	7
valid_sources[0x20]	525690	1			T3	4		T9	31		T11	2
valid_sources[0x21]	224831	1			T3	7		T9	25		T11	3
valid_sources[0x22]	742300	1			T2	3		T3	2		T9	10
valid_sources[0x23]	224324	1			T3	4		T9	15		T16	4
valid_sources[0x24]	227844	1			T3	8		T9	19		T11	1
valid_sources[0x25]	224951	1			T3	3		T9	20		T11	1
valid_sources[0x26]	230318	1			T2	1		T3	3		T9	22
valid_sources[0x27]	622300	1			T3	2		T9	47		T11	5
valid_sources[0x28]	229955	1			T3	3		T9	35		T11	2
valid_sources[0x29]	227803	1			T3	4		T9	14		T16	2
valid_sources[0x2a]	237740	1			T3	6		T9	19		T11	4
valid_sources[0x2b]	228720	1			T3	9		T9	12		T16	1
valid_sources[0x2c]	231745	1			T3	5		T9	3		T16	5
valid_sources[0x2d]	231672	1			T2	3		T3	2		T9	14
valid_sources[0x2e]	668687	1			T3	5		T11	4		T16	5
valid_sources[0x2f]	227351	1			T3	7		T9	23		T11	2
valid_sources[0x30]	225503	1			T3	6		T9	9		T11	3
valid_sources[0x31]	228381	1			T2	2		T3	7		T9	15
valid_sources[0x32]	222506	1			T3	9		T9	14		T11	2
valid_sources[0x33]	235692	1			T2	4		T3	3		T9	11
valid_sources[0x34]	227624	1			T2	9		T3	4		T9	11
valid_sources[0x35]	566773	1			T3	3		T11	2		T16	5
valid_sources[0x36]	227195	1			T3	7		T11	1		T16	6
valid_sources[0x37]	242960	1			T3	3		T11	2		T16	5
valid_sources[0x38]	224496	1			T3	4		T9	33		T16	6
valid_sources[0x39]	225875	1			T2	14		T3	9		T9	17
valid_sources[0x3a]	233720	1			T3	2		T9	22		T11	1
valid_sources[0x3b]	669046	1			T3	7		T9	5		T11	2
valid_sources[0x3c]	229425	1			T3	8		T9	48		T11	3
valid_sources[0x3d]	225168	1			T3	5		T9	13		T11	1
valid_sources[0x3e]	611975	1			T2	1		T3	6		T9	29
valid_sources[0x3f]	230249	1			T3	5		T9	2		T16	4
valid_sources[0x40]	233186	1			T3	10		T16	8		T7	3
valid_sources[0x41]	225206	1			T3	6		T9	57		T16	2
valid_sources[0x42]	238876	1			T3	2		T9	16		T16	3
valid_sources[0x43]	234493	1			T3	3		T11	1		T16	7
valid_sources[0x44]	229024	1			T2	12		T3	5		T9	34
valid_sources[0x45]	227837	1			T3	2		T9	6		T16	2
valid_sources[0x46]	367913	1			T2	4		T3	4		T9	35
valid_sources[0x47]	229336	1			T1	322		T2	15		T3	3
valid_sources[0x48]	223787	1			T2	3		T3	4		T9	15
valid_sources[0x49]	225858	1			T3	5		T9	17		T11	4
valid_sources[0x4a]	1133848	1			T2	7		T3	4		T9	28
valid_sources[0x4b]	239698	1			T2	3		T3	4		T9	28
valid_sources[0x4c]	234089	1			T3	4		T9	9		T11	3
valid_sources[0x4d]	237872	1			T2	2		T3	5		T9	12
valid_sources[0x4e]	247067	1			T3	5		T9	14		T16	8
valid_sources[0x4f]	225524	1			T3	8		T9	1		T11	2
valid_sources[0x50]	225942	1			T3	9		T9	38		T11	1
valid_sources[0x51]	235750	1			T2	1		T3	4		T9	23
valid_sources[0x52]	227745	1			T3	2		T9	8		T11	1
valid_sources[0x53]	230848	1			T2	2		T3	7		T9	10
valid_sources[0x54]	616992	1			T3	6		T9	12		T16	6
valid_sources[0x55]	229922	1			T2	8		T3	6		T9	40
valid_sources[0x56]	1057182	1			T3	5		T11	4		T16	2
valid_sources[0x57]	523655	1			T3	7		T9	3		T11	5
valid_sources[0x58]	228923	1			T3	3		T9	6		T16	7
valid_sources[0x59]	251043	1			T3	5		T16	4		T7	1
valid_sources[0x5a]	228170	1			T3	12		T9	8		T11	2
valid_sources[0x5b]	229476	1			T3	4		T9	32		T11	3
valid_sources[0x5c]	228529	1			T3	3		T9	47		T11	2
valid_sources[0x5d]	260280	1			T2	3		T3	3		T9	4
valid_sources[0x5e]	229080	1			T2	2		T3	6		T9	36
valid_sources[0x5f]	225947	1			T3	4		T11	2		T16	5
valid_sources[0x60]	227632	1			T2	5		T3	3		T9	32
valid_sources[0x61]	226447	1			T2	14		T3	12		T9	3
valid_sources[0x62]	226287	1			T3	6		T9	16		T16	4
valid_sources[0x63]	228331	1			T3	7		T9	28		T16	4
valid_sources[0x64]	226040	1			T3	6		T9	2		T11	4
valid_sources[0x65]	569508	1			T3	2		T9	4		T16	7
valid_sources[0x66]	230854	1			T3	6		T9	4		T11	3
valid_sources[0x67]	227109	1			T3	9		T9	34		T11	1
valid_sources[0x68]	225271	1			T3	3		T9	17		T11	2
valid_sources[0x69]	230044	1			T3	5		T9	18		T11	2
valid_sources[0x6a]	230655	1			T3	9		T9	20		T11	1
valid_sources[0x6b]	225477	1			T3	5		T9	11		T11	1
valid_sources[0x6c]	227327	1			T2	3		T3	4		T9	25
valid_sources[0x6d]	231897	1			T2	6		T3	7		T9	9
valid_sources[0x6e]	235064	1			T3	6		T9	59		T11	3
valid_sources[0x6f]	229258	1			T3	6		T11	4		T16	5
valid_sources[0x70]	627814	1			T3	13		T9	36		T16	2
valid_sources[0x71]	226888	1			T3	6		T9	34		T16	4
valid_sources[0x72]	686629	1			T2	16		T3	2		T11	1
valid_sources[0x73]	431193	1			T3	7		T9	27		T11	2
valid_sources[0x74]	225703	1			T3	3		T9	23		T11	1
valid_sources[0x75]	227980	1			T3	6		T9	3		T11	7
valid_sources[0x76]	707289	1			T2	1		T3	4		T11	1
valid_sources[0x77]	236960	1			T3	5		T11	3		T16	2
valid_sources[0x78]	226513	1			T3	7		T9	15		T16	5
valid_sources[0x79]	229609	1			T3	7		T11	3		T12	20
valid_sources[0x7a]	224858	1			T3	7		T9	1		T11	1
valid_sources[0x7b]	235557	1			T2	23		T3	6		T9	7
valid_sources[0x7c]	226490	1			T3	4		T9	31		T16	3
valid_sources[0x7d]	607413	1			T3	9		T9	5		T11	11
valid_sources[0x7e]	227587	1			T3	8		T9	27		T11	1
valid_sources[0x7f]	227746	1			T3	6		T9	40		T11	4
valid_sources[0x80]	228193	1			T3	11		T9	19		T11	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5919588

1

T1

3

T2

30

T3

79

values[0x0]

all_enables

biggest_size

12098866

1

T1

47

T2

79

T3

233

values[0x1]

all_enables

biggest_size

6850313

1

T1

32

T2

25

T3

121