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Module Instance : tb.dut.gen_classes[0].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_state_flop


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_classes[1].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_state_flop


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_classes[2].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_state_flop


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_classes[3].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_state_flop


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

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Module Instances:
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic
Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00

17 always_ff @(posedge clk_i or negedge rst_ni) begin 18 1/1 if (!rst_ni) begin Tests: T1 T2 T3  19 1/1 q_o <= ResetValue; Tests: T1 T2 T3  20 end else begin 21 1/1 q_o <= d_i; Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00


18 if (!rst_ni) begin -1- 19 q_o <= ResetValue; ==> 20 end else begin 21 q_o <= d_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00

17 always_ff @(posedge clk_i or negedge rst_ni) begin 18 1/1 if (!rst_ni) begin Tests: T1 T2 T3  19 1/1 q_o <= ResetValue; Tests: T1 T2 T3  20 end else begin 21 1/1 q_o <= d_i; Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00


18 if (!rst_ni) begin -1- 19 q_o <= ResetValue; ==> 20 end else begin 21 q_o <= d_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00

17 always_ff @(posedge clk_i or negedge rst_ni) begin 18 1/1 if (!rst_ni) begin Tests: T1 T2 T3  19 1/1 q_o <= ResetValue; Tests: T1 T2 T3  20 end else begin 21 1/1 q_o <= d_i; Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00


18 if (!rst_ni) begin -1- 19 q_o <= ResetValue; ==> 20 end else begin 21 q_o <= d_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00

17 always_ff @(posedge clk_i or negedge rst_ni) begin 18 1/1 if (!rst_ni) begin Tests: T1 T2 T3  19 1/1 q_o <= ResetValue; Tests: T1 T2 T3  20 end else begin 21 1/1 q_o <= d_i; Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer.u_state_regs.u_state_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00


18 if (!rst_ni) begin -1- 19 q_o <= ResetValue; ==> 20 end else begin 21 q_o <= d_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

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