Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T3,T9

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T11,T43
1	1	Covered	T1,T3,T9

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T9

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	11663	0	0
DisabledNoTrigBkwd_A	2147483647	741498	0	0
DisabledNoTrigFwd_A	2147483647	1148344136	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11663	0	0
T1	3533	305	0	0
T2	14629	0	0	0
T3	16155	0	0	0
T4	21986	0	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T9	17004	0	0	0
T10	14866	0	0	0
T11	1644	876	0	0
T16	2999	0	0	0
T17	166157	0	0	0
T20	36933	0	0	0
T28	16424	0	0	0
T40	46107	0	0	0
T43	1472	663	0	0
T46	4174	632	0	0
T47	16389	0	0	0
T48	17204	0	0	0
T50	0	557	0	0
T73	0	270	0	0
T78	30687	0	0	0
T83	8957	0	0	0
T135	0	278	0	0
T143	0	843	0	0
T228	0	424	0	0
T229	0	790	0	0
T230	0	249	0	0
T231	0	602	0	0
T232	0	115	0	0
T233	0	420	0	0
T234	0	1274	0	0
T235	0	647	0	0
T236	0	665	0	0
T237	0	1313	0	0
T238	0	334	0	0
T239	0	406	0	0
T240	18869	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	741498	0	0
T1	3533	2	0	0
T2	14629	0	0	0
T3	32310	5	0	0
T4	43972	0	0	0
T5	59788	0	0	0
T7	70280	0	0	0
T9	34008	35	0	0
T10	59464	16	0	0
T11	3288	24	0	0
T12	167580	36	0	0
T13	108076	30	0	0
T14	200092	0	0	0
T15	189786	57	0	0
T16	11996	4	0	0
T20	0	3	0	0
T42	139822	2	0	0
T43	2944	40	0	0
T44	0	91	0	0
T45	0	3	0	0
T46	0	2	0	0
T47	0	10	0	0
T48	0	3	0	0
T49	0	1	0	0
T50	0	9	0	0
T51	0	43	0	0
T52	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1148344136	0	0
T1	14132	12355	0	0
T2	58516	25768	0	0
T3	64620	41038	0	0
T4	87944	36360	0	0
T5	59788	9392	0	0
T7	70280	19268	0	0
T9	68016	52145	0	0
T10	59464	29500	0	0
T11	6576	2416	0	0
T16	11996	8031	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T10
1	1	Covered	T1,T3,T9

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T11,T73
1	1	Covered	T1,T3,T9

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T9,T11

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	567670942	2387	0	0
DisabledNoTrigBkwd_A	567670942	183467	0	0
DisabledNoTrigFwd_A	567670942	274977696	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	2387	0	0
T1	3533	305	0	0
T2	14629	0	0	0
T3	16155	0	0	0
T4	21986	0	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T9	17004	0	0	0
T10	14866	0	0	0
T11	1644	876	0	0
T16	2999	0	0	0
T73	0	270	0	0
T231	0	602	0	0
T238	0	334	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	183467	0	0
T1	3533	2	0	0
T2	14629	0	0	0
T3	16155	0	0	0
T4	21986	0	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T9	17004	35	0	0
T10	14866	1	0	0
T11	1644	24	0	0
T12	0	12	0	0
T13	0	15	0	0
T15	0	57	0	0
T16	2999	4	0	0
T42	0	2	0	0
T44	0	91	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	274977696	0	0
T1	3533	3062	0	0
T2	14629	3750	0	0
T3	16155	10891	0	0
T4	21986	9090	0	0
T5	14947	2317	0	0
T7	17570	4817	0	0
T9	17004	1295	0	0
T10	14866	9724	0	0
T11	1644	598	0	0
T16	2999	591	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T2 T3 T9 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T10
1	0	Covered	T2,T3,T10
1	1	Covered	T10,T5,T16

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T46,T50,T229
1	1	Covered	T10,T5,T16

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T10,T16,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T5,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	567670942	4118	0	0
DisabledNoTrigBkwd_A	567670942	170180	0	0
DisabledNoTrigFwd_A	567670942	320885519	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	4118	0	0
T17	166157	0	0	0
T20	36933	0	0	0
T28	16424	0	0	0
T40	46107	0	0	0
T46	4174	632	0	0
T47	16389	0	0	0
T48	17204	0	0	0
T50	0	557	0	0
T78	30687	0	0	0
T83	8957	0	0	0
T229	0	790	0	0
T233	0	420	0	0
T237	0	1313	0	0
T239	0	406	0	0
T240	18869	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	170180	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T10	14866	8	0	0
T12	55860	17	0	0
T13	54038	15	0	0
T14	100046	0	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T20	0	3	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T46	0	2	0	0
T47	0	6	0	0
T49	0	1	0	0
T50	0	9	0	0
T51	0	43	0	0
T52	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	320885519	0	0
T1	3533	3083	0	0
T2	14629	14450	0	0
T3	16155	16086	0	0
T4	21986	9090	0	0
T5	14947	2338	0	0
T7	17570	4817	0	0
T9	17004	16950	0	0
T10	14866	8583	0	0
T11	1644	602	0	0
T16	2999	1600	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T2 T3 T9 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T16,T12
1	1	Covered	T3,T10,T12

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T43,T143,T234
1	1	Covered	T3,T10,T12

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T10,T43,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T10,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	567670942	3427	0	0
DisabledNoTrigBkwd_A	567670942	183957	0	0
DisabledNoTrigFwd_A	567670942	265660391	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	3427	0	0
T6	19555	0	0	0
T8	38549	0	0	0
T26	99478	0	0	0
T27	49569	0	0	0
T34	80556	0	0	0
T43	1472	663	0	0
T44	97495	0	0	0
T45	61914	0	0	0
T67	14492	0	0	0
T77	91294	0	0	0
T143	0	843	0	0
T234	0	1274	0	0
T235	0	647	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	183957	0	0
T3	16155	5	0	0
T4	21986	0	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T9	17004	0	0	0
T10	14866	7	0	0
T11	1644	0	0	0
T12	55860	7	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T17	0	3	0	0
T37	0	15	0	0
T43	0	40	0	0
T45	0	3	0	0
T47	0	4	0	0
T48	0	3	0	0
T121	0	9	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	265660391	0	0
T1	3533	3098	0	0
T2	14629	3776	0	0
T3	16155	3168	0	0
T4	21986	9090	0	0
T5	14947	2358	0	0
T7	17570	4817	0	0
T9	17004	16950	0	0
T10	14866	5364	0	0
T11	1644	606	0	0
T16	2999	2920	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T2 T3 T9 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T16
1	1	Covered	T3,T10,T12

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T135,T228,T230
1	1	Covered	T3,T10,T12

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T12,T45

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	567670942	1731	0	0
DisabledNoTrigBkwd_A	567670942	203894	0	0
DisabledNoTrigFwd_A	567670942	286820530	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	1731	0	0
T21	136998	0	0	0
T22	96094	0	0	0
T37	59706	0	0	0
T82	50978	0	0	0
T84	108396	0	0	0
T121	63101	0	0	0
T135	1114	278	0	0
T151	199943	0	0	0
T227	20227	0	0	0
T228	0	424	0	0
T230	0	249	0	0
T232	0	115	0	0
T236	0	665	0	0
T241	108471	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	203894	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T10	14866	5	0	0
T12	55860	3	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T20	0	36	0	0
T37	0	2	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T45	0	25	0	0
T47	0	427	0	0
T49	0	4	0	0
T51	0	58	0	0
T121	0	19	0	0
T135	0	9	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	286820530	0	0
T1	3533	3112	0	0
T2	14629	3792	0	0
T3	16155	10893	0	0
T4	21986	9090	0	0
T5	14947	2379	0	0
T7	17570	4817	0	0
T9	17004	16950	0	0
T10	14866	5829	0	0
T11	1644	610	0	0
T16	2999	2920	0	0