Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T1 T3 T9 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T1 T3 T9 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T1 T3 T9 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T12 T14 
159        1/1                    state_d = TimeoutSt;
           Tests:       T10 T12 T14 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T10 T12 T14 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T10 T12 T14 
172        1/1                    state_d    = Phase0St;
           Tests:       T12 T14 T26 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T12 T14 T26 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T12 T14 T26 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T12 T14 T26 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T10 T12 T14 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T12 T14 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T10 T14 T27 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T14 T27 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T9 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T1 T3 T9 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T1 T3 T9 
190        1/1                  esc_state_o = Phase0;
           Tests:       T1 T3 T9 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T1 T3 T9 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
194        1/1                    state_d = IdleSt;
           Tests:       T28 T29 T30 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T28 T29 T30 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T28 T29 T30 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T9 
198        1/1                    state_d = Phase1St;
           Tests:       T1 T3 T9 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T3 T9 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T9 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T1 T3 T9 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T1 T3 T9 
207        1/1                  esc_state_o = Phase1;
           Tests:       T1 T3 T9 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T1 T3 T9 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
211        1/1                    state_d = IdleSt;
           Tests:       T9 T12 T31 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T9 T12 T31 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T9 T12 T31 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T9 
215        1/1                    state_d = Phase2St;
           Tests:       T1 T3 T9 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T3 T9 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T9 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T1 T3 T9 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T1 T3 T9 
224        1/1                  esc_state_o = Phase2;
           Tests:       T1 T3 T9 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T1 T3 T9 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
229        1/1                    state_d = IdleSt;
           Tests:       T31 T32 T33 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T31 T32 T33 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T31 T32 T33 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T9 
233        1/1                    state_d = Phase3St;
           Tests:       T1 T3 T9 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T9 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T1 T3 T9 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T1 T3 T9 
241        1/1                  esc_state_o = Phase3;
           Tests:       T1 T3 T9 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T1 T3 T9 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
245        1/1                    state_d = IdleSt;
           Tests:       T10 T12 T34 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T12 T34 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T10 T12 T34 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T9 
249        1/1                    state_d = TerminalSt;
           Tests:       T1 T3 T9 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T1 T3 T9 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
259        1/1                  esc_state_o = Terminal;
           Tests:       T1 T3 T9 
260        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
261        1/1                    state_d = IdleSt;
           Tests:       T9 T10 T15 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T7 T8 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T7 T8 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T7 T8 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T7 T8 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T9

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T10,T15
1	0	1	Covered	T1,T11,T10
1	1	0	Covered	T10,T16,T12
1	1	1	Covered	T10,T12,T14

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T14
0	1	Covered	T12,T14,T26
1	0	Covered	T12,T35,T36

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T12,T14
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T12,T35,T36

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T14
1	0	Covered	T37,T38,T39
1	1	Covered	T12,T14,T26

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T9,T10
1	Covered	T1,T11,T10

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T9,T10,T13

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T10,T15,T12

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T9,T11
1	Covered	T3,T10,T15

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T9,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T11,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T3,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T9,T11

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T7,T8
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T9
Phase1St	198	Covered	T1,T3,T9
Phase2St	215	Covered	T1,T3,T9
Phase3St	233	Covered	T1,T3,T9
TerminalSt	249	Covered	T1,T3,T9
TimeoutSt	159	Covered	T10,T12,T14

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T4,T7,T8
IdleSt->Phase0St	152	Covered	T1,T3,T9
IdleSt->TimeoutSt	159	Covered	T10,T12,T14
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T28,T35,T31
Phase0St->Phase1St	198	Covered	T1,T3,T9
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T9,T12,T31
Phase1St->Phase2St	215	Covered	T1,T3,T9
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T31,T32,T33
Phase2St->Phase3St	233	Covered	T1,T3,T9
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T10,T12,T34
Phase3St->TerminalSt	249	Covered	T1,T3,T9
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T9,T10,T15
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T10,T14,T27
TimeoutSt->Phase0St	172	Covered	T12,T14,T26

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T9
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T14
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T26
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T14
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T10,T14,T27
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T29,T30
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T9
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T9,T10
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T9,T12,T31
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T9
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T9,T10
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T32,T33
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T9
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T9,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T10,T12,T34
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T9
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T9,T10
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T10,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T9
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T8
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	900	0	0
CheckAccumTrig0_A	2147483647	2346	0	0
CheckAccumTrig1_A	2147483647	104	0	0
CheckClr_A	2147483647	1056	0	0
CheckEn_A	2147483647	859029419	0	0
CheckPhase0_A	2147483647	2603	0	0
CheckPhase1_A	2147483647	2556	0	0
CheckPhase2_A	2147483647	2503	0	0
CheckPhase3_A	2147483647	2439	0	0
CheckTimeout0_A	2147483647	3133	0	0
CheckTimeoutSt1_A	2147483647	344210	0	0
CheckTimeoutSt2_A	2147483647	2791	0	0
CheckTimeoutStTrig_A	2147483647	218	0	0
ErrorStAllEscAsserted_A	2147483647	5138	0	0
ErrorStIsTerminal_A	2147483647	4178	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	900	0	0
T4	87944	128	0	0
T5	59788	0	0	0
T7	70280	111	0	0
T8	0	184	0	0
T10	59464	0	0	0
T12	223440	0	0	0
T13	216152	0	0	0
T14	400184	0	0	0
T15	253048	0	0	0
T16	11996	0	0	0
T40	0	234	0	0
T41	0	243	0	0
T42	279644	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2346	0	0
T1	3533	1	0	0
T2	14629	0	0	0
T3	32310	1	0	0
T4	43972	0	0	0
T5	59788	0	0	0
T7	70280	0	0	0
T9	34008	4	0	0
T10	59464	5	0	0
T11	3288	1	0	0
T12	167580	6	0	0
T13	108076	2	0	0
T14	200092	0	0	0
T15	189786	4	0	0
T16	11996	1	0	0
T20	0	1	0	0
T42	139822	1	0	0
T43	2944	1	0	0
T44	0	4	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	4	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	104	0	0
T6	19555	0	0	0
T12	55860	2	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T27	49569	0	0	0
T29	0	2	0	0
T31	824886	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	80556	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T44	97495	0	0	0
T53	0	1	0	0
T54	24475	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	3	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	14492	0	0	0
T68	66144	0	0	0
T69	12752	0	0	0
T70	35631	0	0	0
T71	143516	0	0	0
T72	355260	0	0	0
T73	5130	0	0	0
T74	206556	0	0	0
T75	25072	0	0	0
T76	129606	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1056	0	0
T4	21986	0	0	0
T5	29894	0	0	0
T6	39110	0	0	0
T7	35140	0	0	0
T9	17004	3	0	0
T10	29732	2	0	0
T11	1644	0	0	0
T12	223440	6	0	0
T13	216152	0	0	0
T14	300138	0	0	0
T15	126524	3	0	0
T16	5998	0	0	0
T20	0	1	0	0
T26	0	1	0	0
T27	99138	0	0	0
T28	0	2	0	0
T31	0	1	0	0
T34	161112	2	0	0
T36	0	3	0	0
T42	209733	0	0	0
T43	4416	0	0	0
T44	194990	3	0	0
T45	0	2	0	0
T47	0	2	0	0
T52	0	5	0	0
T54	0	1	0	0
T67	28984	0	0	0
T74	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	4	0	0
T80	0	1	0	0
T81	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	859029419	0	0
T1	14132	12355	0	0
T2	58516	25763	0	0
T3	64620	41035	0	0
T4	1044	668	0	0
T5	59788	9388	0	0
T7	2328	2052	0	0
T9	68016	52142	0	0
T10	59464	24148	0	0
T11	6576	2416	0	0
T16	11996	8028	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2603	0	0
T1	3533	1	0	0
T2	14629	0	0	0
T3	32310	1	0	0
T4	43972	0	0	0
T5	59788	0	0	0
T7	70280	0	0	0
T9	34008	4	0	0
T10	59464	5	0	0
T11	3288	1	0	0
T12	167580	9	0	0
T13	108076	2	0	0
T14	200092	1	0	0
T15	189786	4	0	0
T16	11996	1	0	0
T20	0	1	0	0
T26	0	2	0	0
T42	139822	1	0	0
T43	2944	1	0	0
T44	0	4	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	4	0	0
T49	0	1	0	0
T78	0	1	0	0
T82	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2556	0	0
T1	3533	1	0	0
T2	14629	0	0	0
T3	32310	1	0	0
T4	43972	0	0	0
T5	59788	0	0	0
T7	70280	0	0	0
T9	34008	3	0	0
T10	59464	5	0	0
T11	3288	1	0	0
T12	167580	8	0	0
T13	108076	2	0	0
T14	200092	1	0	0
T15	189786	4	0	0
T16	11996	1	0	0
T20	0	1	0	0
T26	0	2	0	0
T42	139822	1	0	0
T43	2944	1	0	0
T44	0	4	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	4	0	0
T49	0	1	0	0
T78	0	1	0	0
T82	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2503	0	0
T1	3533	1	0	0
T2	14629	0	0	0
T3	32310	1	0	0
T4	43972	0	0	0
T5	59788	0	0	0
T7	70280	0	0	0
T9	34008	3	0	0
T10	59464	5	0	0
T11	3288	1	0	0
T12	167580	8	0	0
T13	108076	2	0	0
T14	200092	1	0	0
T15	189786	4	0	0
T16	11996	1	0	0
T20	0	1	0	0
T26	0	2	0	0
T42	139822	1	0	0
T43	2944	1	0	0
T44	0	4	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	4	0	0
T49	0	1	0	0
T78	0	1	0	0
T82	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2439	0	0
T1	3533	1	0	0
T2	14629	0	0	0
T3	32310	1	0	0
T4	43972	0	0	0
T5	59788	0	0	0
T7	70280	0	0	0
T9	34008	3	0	0
T10	59464	4	0	0
T11	3288	1	0	0
T12	167580	7	0	0
T13	108076	2	0	0
T14	200092	1	0	0
T15	189786	4	0	0
T16	11996	1	0	0
T20	0	1	0	0
T26	0	2	0	0
T42	139822	1	0	0
T43	2944	1	0	0
T44	0	4	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	4	0	0
T49	0	1	0	0
T78	0	1	0	0
T82	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3133	0	0
T5	14947	0	0	0
T6	19555	0	0	0
T7	17570	0	0	0
T8	38549	0	0	0
T10	14866	1	0	0
T12	111720	4	0	0
T13	108076	0	0	0
T14	200092	3	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T20	0	10	0	0
T26	99478	9	0	0
T27	99138	9	0	0
T34	161112	0	0	0
T37	0	5	0	0
T42	139822	0	0	0
T43	2944	0	0	0
T44	194990	0	0	0
T45	61914	0	0	0
T46	4174	0	0	0
T47	0	5	0	0
T49	0	3	0	0
T52	0	1	0	0
T67	28984	1	0	0
T77	91294	0	0	0
T78	0	6	0	0
T81	0	1	0	0
T82	0	8	0	0
T83	8957	3	0	0
T84	0	18	0	0
T85	0	14	0	0
T86	0	14	0	0
T87	0	6	0	0
T88	0	1	0	0
T89	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	344210	0	0
T5	14947	0	0	0
T6	19555	0	0	0
T7	17570	0	0	0
T8	38549	0	0	0
T10	14866	45	0	0
T12	111720	251	0	0
T13	108076	0	0	0
T14	200092	356	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T20	0	868	0	0
T26	99478	1950	0	0
T27	99138	1644	0	0
T34	161112	0	0	0
T37	0	1559	0	0
T42	139822	0	0	0
T43	2944	0	0	0
T44	194990	0	0	0
T45	61914	0	0	0
T46	4174	0	0	0
T47	0	1352	0	0
T49	0	1443	0	0
T52	0	1	0	0
T67	28984	97	0	0
T77	91294	0	0	0
T78	0	333	0	0
T81	0	130	0	0
T82	0	1340	0	0
T83	8957	298	0	0
T84	0	1531	0	0
T85	0	1358	0	0
T86	0	1294	0	0
T87	0	1083	0	0
T88	0	495	0	0
T89	0	217	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2791	0	0
T5	14947	0	0	0
T6	19555	0	0	0
T7	17570	0	0	0
T8	115647	0	0	0
T10	14866	1	0	0
T12	55860	0	0	0
T13	54038	0	0	0
T14	200092	2	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T20	0	10	0	0
T26	298434	7	0	0
T27	148707	9	0	0
T34	241668	0	0	0
T37	0	2	0	0
T42	69911	0	0	0
T43	2944	0	0	0
T44	292485	0	0	0
T45	185742	0	0	0
T46	8348	0	0	0
T47	0	5	0	0
T49	0	3	0	0
T67	43476	1	0	0
T70	0	6	0	0
T72	0	1	0	0
T77	182588	0	0	0
T78	0	5	0	0
T81	0	1	0	0
T82	0	7	0	0
T83	17914	3	0	0
T84	0	31	0	0
T85	0	19	0	0
T86	0	18	0	0
T87	0	5	0	0
T89	0	1	0	0
T90	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	218	0	0
T6	19555	0	0	0
T12	55860	1	0	0
T13	54038	0	0	0
T14	100046	1	0	0
T26	99478	2	0	0
T27	49569	0	0	0
T29	0	1	0	0
T31	412443	3	0	0
T34	80556	0	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T44	97495	0	0	0
T58	0	1	0	0
T67	14492	0	0	0
T71	71758	0	0	0
T72	177630	2	0	0
T73	2565	0	0	0
T74	103278	0	0	0
T75	12536	0	0	0
T76	129606	0	0	0
T78	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	2	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0
T98	0	2	0	0
T99	134069	0	0	0
T100	16424	0	0	0
T101	349144	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5138	0	0
T4	87944	641	0	0
T5	59788	0	0	0
T7	70280	635	0	0
T8	0	1282	0	0
T10	59464	0	0	0
T12	223440	0	0	0
T13	216152	0	0	0
T14	400184	0	0	0
T15	253048	0	0	0
T16	11996	0	0	0
T40	0	1310	0	0
T41	0	1270	0	0
T42	279644	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4178	0	0
T4	87944	521	0	0
T5	59788	0	0	0
T7	70280	515	0	0
T8	0	1042	0	0
T10	59464	0	0	0
T12	223440	0	0	0
T13	216152	0	0	0
T14	400184	0	0	0
T15	253048	0	0	0
T16	11996	0	0	0
T40	0	1070	0	0
T41	0	1030	0	0
T42	279644	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14132	13820	0	0
T2	58516	57800	0	0
T3	64620	64344	0	0
T4	372	0	0	0
T5	59788	59004	0	0
T7	396	124	0	0
T9	68016	67800	0	0
T10	59464	59180	0	0
T11	6576	6192	0	0
T15	0	252768	0	0
T16	11996	11680	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14132	13820	0	0
T2	58516	57800	0	0
T3	64620	64344	0	0
T4	87944	36360	0	0
T5	59788	59004	0	0
T7	70280	19268	0	0
T9	68016	67800	0	0
T10	59464	59180	0	0
T11	6576	6192	0	0
T16	11996	11680	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T1 T9 T11 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T1 T9 T11 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T1 T9 T11 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T12 T14 
159        1/1                    state_d = TimeoutSt;
           Tests:       T10 T12 T14 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T10 T12 T14 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T10 T12 T14 
172        1/1                    state_d    = Phase0St;
           Tests:       T12 T35 T36 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T12 T35 T36 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T12 T35 T36 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T12 T35 T36 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T10 T12 T14 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T12 T14 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T10 T14 T67 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T14 T67 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T9 T11 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T1 T9 T11 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T1 T9 T11 
190        1/1                  esc_state_o = Phase0;
           Tests:       T1 T9 T11 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T1 T9 T11 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T1 T9 T11 
194        1/1                    state_d = IdleSt;
           Tests:       T28 T29 T102 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T28 T29 T102 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T28 T29 T102 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T9 T11 
198        1/1                    state_d = Phase1St;
           Tests:       T1 T9 T11 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T9 T11 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T9 T11 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T9 T11 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T1 T9 T11 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T1 T9 T11 
207        1/1                  esc_state_o = Phase1;
           Tests:       T1 T9 T11 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T1 T9 T11 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T1 T9 T11 
211        1/1                    state_d = IdleSt;
           Tests:       T9 T31 T29 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T9 T31 T29 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T9 T31 T29 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T9 T11 
215        1/1                    state_d = Phase2St;
           Tests:       T1 T9 T11 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T9 T11 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T9 T11 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T9 T11 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T1 T9 T11 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T1 T9 T11 
224        1/1                  esc_state_o = Phase2;
           Tests:       T1 T9 T11 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T1 T9 T11 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T1 T9 T11 
229        1/1                    state_d = IdleSt;
           Tests:       T31 T103 T104 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T31 T103 T104 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T31 T103 T104 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T9 T11 
233        1/1                    state_d = Phase3St;
           Tests:       T1 T9 T11 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T9 T11 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T9 T11 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T1 T9 T11 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T1 T9 T11 
241        1/1                  esc_state_o = Phase3;
           Tests:       T1 T9 T11 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T1 T9 T11 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T1 T9 T11 
245        1/1                    state_d = IdleSt;
           Tests:       T12 T34 T19 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T34 T19 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T12 T34 T19 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T9 T11 
249        1/1                    state_d = TerminalSt;
           Tests:       T1 T9 T11 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T9 T11 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T1 T9 T11 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T9 T11 
259        1/1                  esc_state_o = Terminal;
           Tests:       T1 T9 T11 
260        1/1                  if (clr_i) begin
           Tests:       T1 T9 T11 
261        1/1                    state_d = IdleSt;
           Tests:       T9 T15 T12 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T7 T8 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T7 T8 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T7 T8 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T7 T8 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T9,T11
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T9,T11

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T9,T11

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T10,T15
1	0	1	Covered	T1,T11,T15
1	1	0	Covered	T14,T27,T26
1	1	1	Covered	T10,T12,T14

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T14
0	1	Covered	T31,T91,T92
1	0	Covered	T12,T35,T36

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T10,T12,T14
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T12,T35,T36

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T14
1	0	Not Covered
1	1	Covered	T31,T91,T92

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T9,T10,T15
1	Covered	T1,T11,T16

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T11,T10
1	Covered	T9,T13,T42

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T9,T11
1	Covered	T10,T15,T12

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T9,T11
1	Covered	T15,T12,T34

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T9,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T11,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T9,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T9,T11

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T7,T8
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T9,T11
Phase1St	198	Covered	T1,T9,T11
Phase2St	215	Covered	T1,T9,T11
Phase3St	233	Covered	T1,T9,T11
TerminalSt	249	Covered	T1,T9,T11
TimeoutSt	159	Covered	T10,T12,T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T7,T8
IdleSt->Phase0St	152	Covered	T1,T9,T11
IdleSt->TimeoutSt	159	Covered	T10,T12,T14
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T28,T35,T29
Phase0St->Phase1St	198	Covered	T1,T9,T11
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T9,T31,T29
Phase1St->Phase2St	215	Covered	T1,T9,T11
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T31,T103,T104
Phase2St->Phase3St	233	Covered	T1,T9,T11
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T12,T34,T19
Phase3St->TerminalSt	249	Covered	T1,T9,T11
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T9,T15,T12
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T10,T14,T67
TimeoutSt->Phase0St	172	Covered	T12,T35,T36

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T11
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T14
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T12,T35,T36
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T14
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T10,T14,T67
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T29,T102
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T9,T11
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T9,T10,T16
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T9,T31,T29
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T9,T11
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T9,T10,T16
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T103,T104
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T9,T11
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T9,T10,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T12,T34,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T9,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T9,T10,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T15,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T9,T11
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T8
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	567670942	233	0	0
CheckAccumTrig0_A	567670942	817	0	0
CheckAccumTrig1_A	567670942	48	0	0
CheckClr_A	567670942	385	0	0
CheckEn_A	567510543	200990571	0	0
CheckPhase0_A	567670942	904	0	0
CheckPhase1_A	567670942	883	0	0
CheckPhase2_A	567670942	859	0	0
CheckPhase3_A	567670942	831	0	0
CheckTimeout0_A	567670942	1148	0	0
CheckTimeoutSt1_A	567670942	111718	0	0
CheckTimeoutSt2_A	567670942	1029	0	0
CheckTimeoutStTrig_A	567670942	64	0	0
ErrorStAllEscAsserted_A	567670942	1313	0	0
ErrorStIsTerminal_A	567670942	1073	0	0
EscStateOut_A	567509227	567437396	0	0
u_state_regs_A	567670942	567497677	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	233	0	0
T4	21986	38	0	0
T5	14947	0	0	0
T7	17570	20	0	0
T8	0	62	0	0
T10	14866	0	0	0
T12	55860	0	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T40	0	67	0	0
T41	0	46	0	0
T42	69911	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	817	0	0
T1	3533	1	0	0
T2	14629	0	0	0
T3	16155	0	0	0
T4	21986	0	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T9	17004	4	0	0
T10	14866	1	0	0
T11	1644	1	0	0
T12	0	4	0	0
T13	0	1	0	0
T15	0	4	0	0
T16	2999	1	0	0
T42	0	1	0	0
T44	0	4	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	48	0	0
T6	19555	0	0	0
T12	55860	2	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T27	49569	0	0	0
T29	0	2	0	0
T32	0	1	0	0
T34	80556	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T44	97495	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T67	14492	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	385	0	0
T4	21986	0	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T9	17004	3	0	0
T10	14866	0	0	0
T11	1644	0	0	0
T12	55860	5	0	0
T13	54038	0	0	0
T15	63262	3	0	0
T16	2999	0	0	0
T28	0	2	0	0
T34	0	2	0	0
T44	0	3	0	0
T52	0	1	0	0
T77	0	1	0	0
T79	0	4	0	0
T80	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567510543	200990571	0	0
T1	3533	3062	0	0
T2	14629	3749	0	0
T3	16155	10890	0	0
T4	261	167	0	0
T5	14947	2316	0	0
T7	582	513	0	0
T9	17004	1295	0	0
T10	14866	9724	0	0
T11	1644	598	0	0
T16	2999	591	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	904	0	0
T1	3533	1	0	0
T2	14629	0	0	0
T3	16155	0	0	0
T4	21986	0	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T9	17004	4	0	0
T10	14866	1	0	0
T11	1644	1	0	0
T12	0	6	0	0
T13	0	1	0	0
T15	0	4	0	0
T16	2999	1	0	0
T42	0	1	0	0
T44	0	4	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	883	0	0
T1	3533	1	0	0
T2	14629	0	0	0
T3	16155	0	0	0
T4	21986	0	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T9	17004	3	0	0
T10	14866	1	0	0
T11	1644	1	0	0
T12	0	6	0	0
T13	0	1	0	0
T15	0	4	0	0
T16	2999	1	0	0
T42	0	1	0	0
T44	0	4	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	859	0	0
T1	3533	1	0	0
T2	14629	0	0	0
T3	16155	0	0	0
T4	21986	0	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T9	17004	3	0	0
T10	14866	1	0	0
T11	1644	1	0	0
T12	0	6	0	0
T13	0	1	0	0
T15	0	4	0	0
T16	2999	1	0	0
T42	0	1	0	0
T44	0	4	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	831	0	0
T1	3533	1	0	0
T2	14629	0	0	0
T3	16155	0	0	0
T4	21986	0	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T9	17004	3	0	0
T10	14866	1	0	0
T11	1644	1	0	0
T12	0	5	0	0
T13	0	1	0	0
T15	0	4	0	0
T16	2999	1	0	0
T42	0	1	0	0
T44	0	4	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	1148	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T10	14866	1	0	0
T12	55860	2	0	0
T13	54038	0	0	0
T14	100046	1	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T20	0	1	0	0
T26	0	1	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T47	0	2	0	0
T67	0	1	0	0
T78	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	111718	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T10	14866	45	0	0
T12	55860	8	0	0
T13	54038	0	0	0
T14	100046	159	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T20	0	55	0	0
T26	0	282	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T47	0	904	0	0
T67	0	97	0	0
T78	0	117	0	0
T82	0	162	0	0
T83	0	172	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	1029	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T10	14866	1	0	0
T12	55860	0	0	0
T13	54038	0	0	0
T14	100046	1	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T20	0	1	0	0
T26	0	1	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T47	0	2	0	0
T67	0	1	0	0
T78	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T84	0	14	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	64	0	0
T31	412443	2	0	0
T58	0	1	0	0
T71	71758	0	0	0
T72	177630	0	0	0
T73	2565	0	0	0
T74	103278	0	0	0
T75	12536	0	0	0
T76	129606	0	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0
T98	0	2	0	0
T99	134069	0	0	0
T100	16424	0	0	0
T101	349144	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	1313	0	0
T4	21986	180	0	0
T5	14947	0	0	0
T7	17570	145	0	0
T8	0	338	0	0
T10	14866	0	0	0
T12	55860	0	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T40	0	344	0	0
T41	0	306	0	0
T42	69911	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	1073	0	0
T4	21986	150	0	0
T5	14947	0	0	0
T7	17570	115	0	0
T8	0	278	0	0
T10	14866	0	0	0
T12	55860	0	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T40	0	284	0	0
T41	0	246	0	0
T42	69911	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567509227	567437396	0	0
T1	3533	3455	0	0
T2	14629	14450	0	0
T3	16155	16086	0	0
T4	93	0	0	0
T5	14947	14751	0	0
T7	99	31	0	0
T9	17004	16950	0	0
T10	14866	14795	0	0
T11	1644	1548	0	0
T15	0	63192	0	0
T16	2999	2920	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	567497677	0	0
T1	3533	3455	0	0
T2	14629	14450	0	0
T3	16155	16086	0	0
T4	21986	9090	0	0
T5	14947	14751	0	0
T7	17570	4817	0	0
T9	17004	16950	0	0
T10	14866	14795	0	0
T11	1644	1548	0	0
T16	2999	2920	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T10 T5 T12 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T10 T5 T12 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T10 T5 T12 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T14 T27 
159        1/1                    state_d = TimeoutSt;
           Tests:       T12 T14 T27 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T12 T14 T27 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T12 T14 T27 
172        1/1                    state_d    = Phase0St;
           Tests:       T12 T14 T78 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T12 T14 T78 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T12 T14 T78 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T12 T14 T78 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T12 T14 T27 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T14 T27 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T27 T83 T47 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T27 T83 T47 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T12 T13 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T10 T12 T13 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T10 T12 T13 
190        1/1                  esc_state_o = Phase0;
           Tests:       T10 T12 T13 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T10 T12 T13 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T10 T12 T13 
194        1/1                    state_d = IdleSt;
           Tests:       T105 T106 T107 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T105 T106 T107 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T105 T106 T107 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T12 T13 
198        1/1                    state_d = Phase1St;
           Tests:       T10 T12 T13 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T12 T13 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T12 T13 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T12 T13 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T10 T12 T13 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T10 T12 T13 
207        1/1                  esc_state_o = Phase1;
           Tests:       T10 T12 T13 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T10 T12 T13 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T10 T12 T13 
211        1/1                    state_d = IdleSt;
           Tests:       T12 T106 T108 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T106 T108 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T12 T106 T108 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T12 T13 
215        1/1                    state_d = Phase2St;
           Tests:       T10 T12 T13 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T12 T13 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T12 T13 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T12 T13 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T10 T12 T13 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T10 T12 T13 
224        1/1                  esc_state_o = Phase2;
           Tests:       T10 T12 T13 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T10 T12 T13 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T10 T12 T13 
229        1/1                    state_d = IdleSt;
           Tests:       T32 T109 T110 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T109 T110 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T32 T109 T110 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T12 T13 
233        1/1                    state_d = Phase3St;
           Tests:       T10 T12 T13 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T12 T13 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T12 T13 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T10 T12 T13 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T10 T12 T13 
241        1/1                  esc_state_o = Phase3;
           Tests:       T10 T12 T13 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T10 T12 T13 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T10 T12 T13 
245        1/1                    state_d = IdleSt;
           Tests:       T96 T111 T104 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T96 T111 T104 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T96 T111 T104 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T12 T13 
249        1/1                    state_d = TerminalSt;
           Tests:       T10 T12 T13 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T12 T13 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T10 T12 T13 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T10 T12 T13 
259        1/1                  esc_state_o = Terminal;
           Tests:       T10 T12 T13 
260        1/1                  if (clr_i) begin
           Tests:       T10 T12 T13 
261        1/1                    state_d = IdleSt;
           Tests:       T47 T78 T20 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T7 T8 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T7 T8 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T7 T8 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T7 T8 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T10,T5,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T5,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T11,T10
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T10,T5,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T14,T27
1	0	1	Covered	T10,T16,T46
1	1	0	Covered	T16,T14,T26
1	1	1	Covered	T12,T14,T27

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T27
0	1	Covered	T12,T14,T78
1	0	Covered	T54,T56,T57

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T12,T14,T27
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T54,T56,T57

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T27
1	0	Not Covered
1	1	Covered	T12,T14,T78

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T12,T13
1	Covered	T46,T50,T112

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T12,T13
1	Covered	T14,T20,T82

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T10,T14,T46
1	Covered	T12,T13,T47

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T10,T47,T51

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T10,T12,T46

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T46,T47,T78

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T10,T13,T14

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T7,T8
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T10,T12,T13
Phase1St	198	Covered	T10,T12,T13
Phase2St	215	Covered	T10,T12,T13
Phase3St	233	Covered	T10,T12,T13
TerminalSt	249	Covered	T10,T12,T13
TimeoutSt	159	Covered	T12,T14,T27

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T7,T8
IdleSt->Phase0St	152	Covered	T10,T12,T13
IdleSt->TimeoutSt	159	Covered	T12,T14,T27
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T31,T72,T58
Phase0St->Phase1St	198	Covered	T10,T12,T13
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T12,T106,T108
Phase1St->Phase2St	215	Covered	T10,T12,T13
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T32,T109,T110
Phase2St->Phase3St	233	Covered	T10,T12,T13
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T96,T111,T104
Phase3St->TerminalSt	249	Covered	T10,T12,T13
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T47,T78,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T27,T83,T47
TimeoutSt->Phase0St	172	Covered	T12,T14,T78

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T5,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T27
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T78
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T27
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T27,T83,T47
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T105,T106,T107
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T10,T12,T13
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T10,T12,T13
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T12,T106,T108
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T10,T12,T13
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T10,T12,T13
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T32,T109,T110
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T10,T12,T13
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T10,T12,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T96,T111,T104
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T10,T12,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T10,T12,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T47,T78,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T10,T12,T13
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T8
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	567670942	222	0	0
CheckAccumTrig0_A	567670942	493	0	0
CheckAccumTrig1_A	567670942	14	0	0
CheckClr_A	567670942	209	0	0
CheckEn_A	567510543	245229440	0	0
CheckPhase0_A	567670942	534	0	0
CheckPhase1_A	567670942	527	0	0
CheckPhase2_A	567670942	512	0	0
CheckPhase3_A	567670942	500	0	0
CheckTimeout0_A	567670942	444	0	0
CheckTimeoutSt1_A	567670942	62610	0	0
CheckTimeoutSt2_A	567670942	385	0	0
CheckTimeoutStTrig_A	567670942	43	0	0
ErrorStAllEscAsserted_A	567670942	1316	0	0
ErrorStIsTerminal_A	567670942	1076	0	0
EscStateOut_A	567509227	567437396	0	0
u_state_regs_A	567670942	567497677	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	222	0	0
T4	21986	29	0	0
T5	14947	0	0	0
T7	17570	28	0	0
T8	0	49	0	0
T10	14866	0	0	0
T12	55860	0	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T40	0	56	0	0
T41	0	60	0	0
T42	69911	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	493	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T10	14866	1	0	0
T12	55860	1	0	0
T13	54038	1	0	0
T14	100046	0	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T20	0	1	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T46	0	1	0	0
T47	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	14	0	0
T31	412443	0	0	0
T32	0	1	0	0
T54	24475	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T62	0	3	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T68	66144	0	0	0
T69	12752	0	0	0
T70	35631	0	0	0
T71	71758	0	0	0
T72	177630	0	0	0
T73	2565	0	0	0
T74	103278	0	0	0
T75	12536	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	209	0	0
T6	19555	0	0	0
T12	55860	1	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T20	0	1	0	0
T27	49569	0	0	0
T31	0	1	0	0
T34	80556	0	0	0
T36	0	3	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T44	97495	0	0	0
T47	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T67	14492	0	0	0
T74	0	1	0	0
T78	0	1	0	0
T81	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567510543	245229440	0	0
T1	3533	3083	0	0
T2	14629	14448	0	0
T3	16155	16085	0	0
T4	261	167	0	0
T5	14947	2337	0	0
T7	582	513	0	0
T9	17004	16949	0	0
T10	14866	3231	0	0
T11	1644	602	0	0
T16	2999	1599	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	534	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T10	14866	1	0	0
T12	55860	2	0	0
T13	54038	1	0	0
T14	100046	1	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T20	0	1	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T46	0	1	0	0
T47	0	2	0	0
T49	0	1	0	0
T78	0	1	0	0
T82	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	527	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T10	14866	1	0	0
T12	55860	1	0	0
T13	54038	1	0	0
T14	100046	1	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T20	0	1	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T46	0	1	0	0
T47	0	2	0	0
T49	0	1	0	0
T78	0	1	0	0
T82	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	512	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T10	14866	1	0	0
T12	55860	1	0	0
T13	54038	1	0	0
T14	100046	1	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T20	0	1	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T46	0	1	0	0
T47	0	2	0	0
T49	0	1	0	0
T78	0	1	0	0
T82	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	500	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T10	14866	1	0	0
T12	55860	1	0	0
T13	54038	1	0	0
T14	100046	1	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T20	0	1	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T46	0	1	0	0
T47	0	2	0	0
T49	0	1	0	0
T78	0	1	0	0
T82	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	444	0	0
T6	19555	0	0	0
T12	55860	1	0	0
T13	54038	0	0	0
T14	100046	1	0	0
T20	0	9	0	0
T27	49569	3	0	0
T34	80556	0	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T44	97495	0	0	0
T47	0	2	0	0
T49	0	2	0	0
T67	14492	0	0	0
T78	0	2	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	16	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	62610	0	0
T6	19555	0	0	0
T12	55860	162	0	0
T13	54038	0	0	0
T14	100046	25	0	0
T20	0	813	0	0
T27	49569	554	0	0
T34	80556	0	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T44	97495	0	0	0
T47	0	441	0	0
T49	0	968	0	0
T67	14492	0	0	0
T78	0	46	0	0
T82	0	124	0	0
T83	0	126	0	0
T84	0	1368	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	385	0	0
T8	38549	0	0	0
T20	0	9	0	0
T26	99478	0	0	0
T27	49569	3	0	0
T34	80556	0	0	0
T44	97495	0	0	0
T45	61914	0	0	0
T46	4174	0	0	0
T47	0	2	0	0
T49	0	2	0	0
T67	14492	0	0	0
T77	91294	0	0	0
T78	0	1	0	0
T83	8957	1	0	0
T84	0	15	0	0
T85	0	5	0	0
T86	0	1	0	0
T90	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	43	0	0
T6	19555	0	0	0
T12	55860	1	0	0
T13	54038	0	0	0
T14	100046	1	0	0
T27	49569	0	0	0
T29	0	1	0	0
T31	0	1	0	0
T34	80556	0	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T44	97495	0	0	0
T67	14492	0	0	0
T72	0	1	0	0
T78	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T86	0	1	0	0
T88	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	1316	0	0
T4	21986	163	0	0
T5	14947	0	0	0
T7	17570	163	0	0
T8	0	332	0	0
T10	14866	0	0	0
T12	55860	0	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T40	0	318	0	0
T41	0	340	0	0
T42	69911	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	1076	0	0
T4	21986	133	0	0
T5	14947	0	0	0
T7	17570	133	0	0
T8	0	272	0	0
T10	14866	0	0	0
T12	55860	0	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T40	0	258	0	0
T41	0	280	0	0
T42	69911	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567509227	567437396	0	0
T1	3533	3455	0	0
T2	14629	14450	0	0
T3	16155	16086	0	0
T4	93	0	0	0
T5	14947	14751	0	0
T7	99	31	0	0
T9	17004	16950	0	0
T10	14866	14795	0	0
T11	1644	1548	0	0
T15	0	63192	0	0
T16	2999	2920	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	567497677	0	0
T1	3533	3455	0	0
T2	14629	14450	0	0
T3	16155	16086	0	0
T4	21986	9090	0	0
T5	14947	14751	0	0
T7	17570	4817	0	0
T9	17004	16950	0	0
T10	14866	14795	0	0
T11	1644	1548	0	0
T16	2999	2920	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T3 T10 T12 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T3 T10 T12 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T3 T10 T12 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T27 T26 T47 
159        1/1                    state_d = TimeoutSt;
           Tests:       T27 T26 T47 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T27 T26 T47 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T27 T26 T47 
172        1/1                    state_d    = Phase0St;
           Tests:       T26 T87 T88 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T26 T87 T88 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T26 T87 T88 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T26 T87 T88 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T27 T26 T47 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T27 T26 T47 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T27 T47 T82 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T27 T47 T82 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T3 T10 T12 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T3 T10 T12 
190        1/1                  esc_state_o = Phase0;
           Tests:       T3 T10 T12 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T3 T10 T12 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
194        1/1                    state_d = IdleSt;
           Tests:       T30 T113 T114 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T30 T113 T114 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T30 T113 T114 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
198        1/1                    state_d = Phase1St;
           Tests:       T3 T10 T12 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T10 T12 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T3 T10 T12 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T3 T10 T12 
207        1/1                  esc_state_o = Phase1;
           Tests:       T3 T10 T12 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T3 T10 T12 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
211        1/1                    state_d = IdleSt;
           Tests:       T115 T116 T117 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T115 T116 T117 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T115 T116 T117 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
215        1/1                    state_d = Phase2St;
           Tests:       T3 T10 T12 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T10 T12 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T3 T10 T12 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T3 T10 T12 
224        1/1                  esc_state_o = Phase2;
           Tests:       T3 T10 T12 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T3 T10 T12 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
229        1/1                    state_d = IdleSt;
           Tests:       T33 T106 T118 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T33 T106 T118 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T33 T106 T118 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
233        1/1                    state_d = Phase3St;
           Tests:       T3 T10 T12 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T3 T10 T12 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T3 T10 T12 
241        1/1                  esc_state_o = Phase3;
           Tests:       T3 T10 T12 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T3 T10 T12 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
245        1/1                    state_d = IdleSt;
           Tests:       T10 T119 T96 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T119 T96 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T10 T119 T96 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
249        1/1                    state_d = TerminalSt;
           Tests:       T3 T10 T12 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T3 T10 T12 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
259        1/1                  esc_state_o = Terminal;
           Tests:       T3 T10 T12 
260        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
261        1/1                    state_d = IdleSt;
           Tests:       T10 T26 T45 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T7 T8 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T7 T8 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T7 T8 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T7 T8 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T3,T10,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T10,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T12,T14
1	0	1	Covered	T10,T43,T48
1	1	0	Covered	T14,T26,T45
1	1	1	Covered	T27,T26,T47

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T27,T26,T47
0	1	Covered	T26,T87,T88
1	0	Covered	T31,T55,T120

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T27,T26,T47
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T31,T55,T120

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T26,T47
1	0	Not Covered
1	1	Covered	T26,T87,T88

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T12
1	Covered	T10,T43,T47

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T12
1	Covered	T10,T45,T37

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T12
1	Covered	T10,T26,T17

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T10,T43,T26
1	Covered	T3,T12,T26

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T12,T43,T45

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T10,T43,T26

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T3,T10,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T10,T12,T43

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T7,T8
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T10,T12
Phase1St	198	Covered	T3,T10,T12
Phase2St	215	Covered	T3,T10,T12
Phase3St	233	Covered	T3,T10,T12
TerminalSt	249	Covered	T3,T10,T12
TimeoutSt	159	Covered	T27,T26,T47

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T7,T8
IdleSt->Phase0St	152	Covered	T3,T10,T12
IdleSt->TimeoutSt	159	Covered	T27,T26,T47
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T29,T30,T97
Phase0St->Phase1St	198	Covered	T3,T10,T12
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T72,T115,T116
Phase1St->Phase2St	215	Covered	T3,T10,T12
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T33,T106,T118
Phase2St->Phase3St	233	Covered	T3,T10,T12
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T10,T119,T96
Phase3St->TerminalSt	249	Covered	T3,T10,T12
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T10,T26,T45
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T27,T47,T82
TimeoutSt->Phase0St	172	Covered	T26,T87,T88

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T27,T26,T47
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T26,T87,T88
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T27,T26,T47
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T27,T47,T82
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T113,T114
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T10,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T10,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T115,T116,T117
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T10,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T10,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T33,T106,T118
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T10,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T10,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T10,T119,T96
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T10,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T10,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T26,T45
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T10,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T8
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	567670942	220	0	0
CheckAccumTrig0_A	567670942	501	0	0
CheckAccumTrig1_A	567670942	26	0	0
CheckClr_A	567670942	216	0	0
CheckEn_A	567510543	209108836	0	0
CheckPhase0_A	567670942	548	0	0
CheckPhase1_A	567670942	541	0	0
CheckPhase2_A	567670942	534	0	0
CheckPhase3_A	567670942	520	0	0
CheckTimeout0_A	567670942	689	0	0
CheckTimeoutSt1_A	567670942	71751	0	0
CheckTimeoutSt2_A	567670942	620	0	0
CheckTimeoutStTrig_A	567670942	38	0	0
ErrorStAllEscAsserted_A	567670942	1282	0	0
ErrorStIsTerminal_A	567670942	1042	0	0
EscStateOut_A	567509227	567437396	0	0
u_state_regs_A	567670942	567497677	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	220	0	0
T4	21986	26	0	0
T5	14947	0	0	0
T7	17570	37	0	0
T8	0	36	0	0
T10	14866	0	0	0
T12	55860	0	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T40	0	55	0	0
T41	0	66	0	0
T42	69911	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	501	0	0
T3	16155	1	0	0
T4	21986	0	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T9	17004	0	0	0
T10	14866	3	0	0
T11	1644	0	0	0
T12	55860	1	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T17	0	1	0	0
T37	0	2	0	0
T43	0	1	0	0
T45	0	2	0	0
T47	0	2	0	0
T48	0	1	0	0
T121	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	26	0	0
T31	412443	1	0	0
T33	0	1	0	0
T55	0	1	0	0
T71	71758	0	0	0
T72	177630	0	0	0
T73	2565	0	0	0
T74	103278	0	0	0
T75	12536	0	0	0
T76	129606	0	0	0
T99	134069	0	0	0
T100	16424	0	0	0
T101	349144	0	0	0
T105	0	1	0	0
T113	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	216	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T10	14866	2	0	0
T12	55860	0	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T26	0	1	0	0
T37	0	1	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T45	0	2	0	0
T47	0	1	0	0
T52	0	3	0	0
T87	0	1	0	0
T90	0	1	0	0
T112	0	1	0	0
T127	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567510543	209108836	0	0
T1	3533	3098	0	0
T2	14629	3775	0	0
T3	16155	3168	0	0
T4	261	167	0	0
T5	14947	2357	0	0
T7	582	513	0	0
T9	17004	16949	0	0
T10	14866	5364	0	0
T11	1644	606	0	0
T16	2999	2919	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	548	0	0
T3	16155	1	0	0
T4	21986	0	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T9	17004	0	0	0
T10	14866	3	0	0
T11	1644	0	0	0
T12	55860	1	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T17	0	1	0	0
T26	0	2	0	0
T43	0	1	0	0
T45	0	2	0	0
T47	0	2	0	0
T48	0	1	0	0
T121	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	541	0	0
T3	16155	1	0	0
T4	21986	0	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T9	17004	0	0	0
T10	14866	3	0	0
T11	1644	0	0	0
T12	55860	1	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T17	0	1	0	0
T26	0	2	0	0
T43	0	1	0	0
T45	0	2	0	0
T47	0	2	0	0
T48	0	1	0	0
T121	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	534	0	0
T3	16155	1	0	0
T4	21986	0	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T9	17004	0	0	0
T10	14866	3	0	0
T11	1644	0	0	0
T12	55860	1	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T17	0	1	0	0
T26	0	2	0	0
T43	0	1	0	0
T45	0	2	0	0
T47	0	2	0	0
T48	0	1	0	0
T121	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	520	0	0
T3	16155	1	0	0
T4	21986	0	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T9	17004	0	0	0
T10	14866	2	0	0
T11	1644	0	0	0
T12	55860	1	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T17	0	1	0	0
T26	0	2	0	0
T43	0	1	0	0
T45	0	2	0	0
T47	0	2	0	0
T48	0	1	0	0
T121	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	689	0	0
T8	38549	0	0	0
T26	99478	2	0	0
T27	49569	6	0	0
T34	80556	0	0	0
T44	97495	0	0	0
T45	61914	0	0	0
T46	4174	0	0	0
T47	0	1	0	0
T67	14492	0	0	0
T77	91294	0	0	0
T81	0	1	0	0
T82	0	2	0	0
T83	8957	0	0	0
T85	0	7	0	0
T86	0	14	0	0
T87	0	6	0	0
T88	0	1	0	0
T89	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	71751	0	0
T8	38549	0	0	0
T26	99478	337	0	0
T27	49569	1090	0	0
T34	80556	0	0	0
T44	97495	0	0	0
T45	61914	0	0	0
T46	4174	0	0	0
T47	0	7	0	0
T67	14492	0	0	0
T77	91294	0	0	0
T81	0	130	0	0
T82	0	347	0	0
T83	8957	0	0	0
T85	0	612	0	0
T86	0	1294	0	0
T87	0	1083	0	0
T88	0	495	0	0
T89	0	217	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	620	0	0
T8	38549	0	0	0
T26	99478	0	0	0
T27	49569	6	0	0
T34	80556	0	0	0
T44	97495	0	0	0
T45	61914	0	0	0
T46	4174	0	0	0
T47	0	1	0	0
T67	14492	0	0	0
T70	0	6	0	0
T72	0	1	0	0
T77	91294	0	0	0
T81	0	1	0	0
T82	0	2	0	0
T83	8957	0	0	0
T85	0	7	0	0
T86	0	14	0	0
T87	0	5	0	0
T89	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	38	0	0
T8	38549	0	0	0
T20	36933	0	0	0
T26	99478	2	0	0
T28	16424	0	0	0
T33	0	2	0	0
T45	61914	0	0	0
T46	4174	0	0	0
T47	16389	0	0	0
T68	0	1	0	0
T69	0	1	0	0
T72	0	1	0	0
T77	91294	0	0	0
T78	30687	0	0	0
T83	8957	0	0	0
T87	0	1	0	0
T88	0	1	0	0
T102	0	1	0	0
T120	0	2	0	0
T128	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	1282	0	0
T4	21986	141	0	0
T5	14947	0	0	0
T7	17570	161	0	0
T8	0	329	0	0
T10	14866	0	0	0
T12	55860	0	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T40	0	330	0	0
T41	0	321	0	0
T42	69911	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	1042	0	0
T4	21986	111	0	0
T5	14947	0	0	0
T7	17570	131	0	0
T8	0	269	0	0
T10	14866	0	0	0
T12	55860	0	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T40	0	270	0	0
T41	0	261	0	0
T42	69911	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567509227	567437396	0	0
T1	3533	3455	0	0
T2	14629	14450	0	0
T3	16155	16086	0	0
T4	93	0	0	0
T5	14947	14751	0	0
T7	99	31	0	0
T9	17004	16950	0	0
T10	14866	14795	0	0
T11	1644	1548	0	0
T15	0	63192	0	0
T16	2999	2920	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	567497677	0	0
T1	3533	3455	0	0
T2	14629	14450	0	0
T3	16155	16086	0	0
T4	21986	9090	0	0
T5	14947	14751	0	0
T7	17570	4817	0	0
T9	17004	16950	0	0
T10	14866	14795	0	0
T11	1644	1548	0	0
T16	2999	2920	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T10 T12 T45 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T10 T12 T45 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T10 T12 T45 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T14 T26 
159        1/1                    state_d = TimeoutSt;
           Tests:       T12 T14 T26 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T12 T14 T26 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T12 T14 T26 
172        1/1                    state_d    = Phase0St;
           Tests:       T12 T37 T52 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T12 T37 T52 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T12 T37 T52 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T12 T37 T52 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T12 T14 T26 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T14 T26 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T14 T26 T78 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T14 T26 T78 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T12 T45 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T10 T12 T45 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T10 T12 T45 
190        1/1                  esc_state_o = Phase0;
           Tests:       T10 T12 T45 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T10 T12 T45 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T10 T12 T45 
194        1/1                    state_d = IdleSt;
           Tests:       T129 T130 T117 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T129 T130 T117 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T129 T130 T117 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T12 T45 
198        1/1                    state_d = Phase1St;
           Tests:       T10 T12 T45 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T12 T45 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T12 T45 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T12 T45 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T10 T12 T45 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T10 T12 T45 
207        1/1                  esc_state_o = Phase1;
           Tests:       T10 T12 T45 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T10 T12 T45 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T10 T12 T45 
211        1/1                    state_d = IdleSt;
           Tests:       T131 T132 T133 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T131 T132 T133 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T131 T132 T133 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T12 T45 
215        1/1                    state_d = Phase2St;
           Tests:       T10 T12 T45 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T12 T45 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T12 T45 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T12 T45 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T10 T12 T45 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T10 T12 T45 
224        1/1                  esc_state_o = Phase2;
           Tests:       T10 T12 T45 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T10 T12 T45 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T10 T12 T45 
229        1/1                    state_d = IdleSt;
           Tests:       T113 T134 T118 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T113 T134 T118 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T113 T134 T118 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T12 T45 
233        1/1                    state_d = Phase3St;
           Tests:       T10 T12 T45 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T12 T45 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T12 T45 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T10 T12 T45 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T10 T12 T45 
241        1/1                  esc_state_o = Phase3;
           Tests:       T10 T12 T45 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T10 T12 T45 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T10 T12 T45 
245        1/1                    state_d = IdleSt;
           Tests:       T12 T58 T105 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T58 T105 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T12 T58 T105 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T12 T45 
249        1/1                    state_d = TerminalSt;
           Tests:       T10 T12 T45 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T12 T45 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T10 T12 T45 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T10 T12 T45 
259        1/1                  esc_state_o = Terminal;
           Tests:       T10 T12 T45 
260        1/1                  if (clr_i) begin
           Tests:       T10 T12 T45 
261        1/1                    state_d = IdleSt;
           Tests:       T12 T37 T52 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T7 T8 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T7 T8 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T7 T8 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T7 T8 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T10,T12,T14
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T12,T14

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T10,T12,T45

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T12,T42
1	0	1	Covered	T3,T45,T135
1	1	0	Covered	T10,T12,T14
1	1	1	Covered	T12,T14,T26

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T26
0	1	Covered	T12,T37,T136
1	0	Covered	T52,T88,T137

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T12,T14,T26
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T52,T88,T137

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T26
1	0	Covered	T37,T38,T39
1	1	Covered	T12,T37,T136

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T12,T45
1	Covered	T12,T135,T37

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T12,T45
1	Covered	T47,T121,T37

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T10,T12,T45
1	Covered	T12,T20,T52

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12,T47,T20
1	Covered	T10,T12,T45

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T10,T12,T45

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T10,T12,T45

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T12,T45,T135

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T10,T45,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T7,T8
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T10,T12,T45
Phase1St	198	Covered	T10,T12,T45
Phase2St	215	Covered	T10,T12,T45
Phase3St	233	Covered	T10,T12,T45
TerminalSt	249	Covered	T10,T12,T45
TimeoutSt	159	Covered	T12,T14,T26

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T7,T8
IdleSt->Phase0St	152	Covered	T10,T12,T45
IdleSt->TimeoutSt	159	Covered	T12,T14,T26
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T29,T58,T97
Phase0St->Phase1St	198	Covered	T10,T12,T45
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T92,T131,T132
Phase1St->Phase2St	215	Covered	T10,T12,T45
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T113,T134,T118
Phase2St->Phase3St	233	Covered	T10,T12,T45
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T12,T58,T105
Phase3St->TerminalSt	249	Covered	T10,T12,T45
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T12,T37,T52
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T14,T26,T78
TimeoutSt->Phase0St	172	Covered	T12,T37,T52

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T45
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T26
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T12,T37,T52
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T26
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T14,T26,T78
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T129,T130,T117
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T10,T12,T45
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T10,T12,T45
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T131,T132,T133
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T10,T12,T45
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T10,T12,T45
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T113,T134,T118
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T10,T12,T45
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T10,T12,T45
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T12,T58,T105
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T10,T12,T45
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T10,T12,T45
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T12,T37,T52
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T10,T12,T45
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T8
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	567670942	225	0	0
CheckAccumTrig0_A	567670942	535	0	0
CheckAccumTrig1_A	567670942	16	0	0
CheckClr_A	567670942	246	0	0
CheckEn_A	567510543	203700572	0	0
CheckPhase0_A	567670942	617	0	0
CheckPhase1_A	567670942	605	0	0
CheckPhase2_A	567670942	598	0	0
CheckPhase3_A	567670942	588	0	0
CheckTimeout0_A	567670942	852	0	0
CheckTimeoutSt1_A	567670942	98131	0	0
CheckTimeoutSt2_A	567670942	757	0	0
CheckTimeoutStTrig_A	567670942	73	0	0
ErrorStAllEscAsserted_A	567670942	1227	0	0
ErrorStIsTerminal_A	567670942	987	0	0
EscStateOut_A	567509227	567437396	0	0
u_state_regs_A	567670942	567497677	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	225	0	0
T4	21986	35	0	0
T5	14947	0	0	0
T7	17570	26	0	0
T8	0	37	0	0
T10	14866	0	0	0
T12	55860	0	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T40	0	56	0	0
T41	0	71	0	0
T42	69911	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	535	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T10	14866	1	0	0
T12	55860	3	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T20	0	1	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T52	0	9	0	0
T121	0	1	0	0
T135	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	16	0	0
T18	603227	0	0	0
T23	55218	0	0	0
T24	22571	0	0	0
T35	48190	0	0	0
T52	97700	1	0	0
T79	20703	0	0	0
T80	37451	0	0	0
T88	0	1	0	0
T90	35439	0	0	0
T113	0	1	0	0
T120	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	4368	0	0	0
T144	18175	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	246	0	0
T6	19555	0	0	0
T12	55860	4	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T27	49569	0	0	0
T34	80556	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T44	97495	0	0	0
T52	0	9	0	0
T67	14492	0	0	0
T81	0	5	0	0
T88	0	1	0	0
T127	0	2	0	0
T137	0	2	0	0
T145	0	1	0	0
T146	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567510543	203700572	0	0
T1	3533	3112	0	0
T2	14629	3791	0	0
T3	16155	10892	0	0
T4	261	167	0	0
T5	14947	2378	0	0
T7	582	513	0	0
T9	17004	16949	0	0
T10	14866	5829	0	0
T11	1644	610	0	0
T16	2999	2919	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	617	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T10	14866	1	0	0
T12	55860	4	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T20	0	1	0	0
T37	0	3	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T121	0	1	0	0
T135	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	605	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T10	14866	1	0	0
T12	55860	4	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T20	0	1	0	0
T37	0	3	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T121	0	1	0	0
T135	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	598	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T10	14866	1	0	0
T12	55860	4	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T20	0	1	0	0
T37	0	3	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T121	0	1	0	0
T135	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	588	0	0
T5	14947	0	0	0
T7	17570	0	0	0
T10	14866	1	0	0
T12	55860	3	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T20	0	1	0	0
T37	0	3	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T121	0	1	0	0
T135	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	852	0	0
T6	19555	0	0	0
T12	55860	1	0	0
T13	54038	0	0	0
T14	100046	1	0	0
T26	0	6	0	0
T27	49569	0	0	0
T34	80556	0	0	0
T37	0	5	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T44	97495	0	0	0
T49	0	1	0	0
T52	0	1	0	0
T67	14492	0	0	0
T78	0	3	0	0
T82	0	4	0	0
T84	0	2	0	0
T85	0	7	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	98131	0	0
T6	19555	0	0	0
T12	55860	81	0	0
T13	54038	0	0	0
T14	100046	172	0	0
T26	0	1331	0	0
T27	49569	0	0	0
T34	80556	0	0	0
T37	0	1559	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T44	97495	0	0	0
T49	0	475	0	0
T52	0	1	0	0
T67	14492	0	0	0
T78	0	170	0	0
T82	0	707	0	0
T84	0	163	0	0
T85	0	746	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	757	0	0
T6	19555	0	0	0
T8	38549	0	0	0
T14	100046	1	0	0
T26	99478	6	0	0
T27	49569	0	0	0
T34	80556	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T43	1472	0	0	0
T44	97495	0	0	0
T45	61914	0	0	0
T49	0	1	0	0
T67	14492	0	0	0
T78	0	3	0	0
T82	0	4	0	0
T84	0	2	0	0
T85	0	7	0	0
T86	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	73	0	0
T6	19555	0	0	0
T12	55860	1	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T27	49569	0	0	0
T34	80556	0	0	0
T36	0	3	0	0
T37	0	3	0	0
T42	69911	0	0	0
T43	1472	0	0	0
T44	97495	0	0	0
T58	0	2	0	0
T67	14492	0	0	0
T72	0	1	0	0
T91	0	1	0	0
T127	0	1	0	0
T136	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	1227	0	0
T4	21986	157	0	0
T5	14947	0	0	0
T7	17570	166	0	0
T8	0	283	0	0
T10	14866	0	0	0
T12	55860	0	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T40	0	318	0	0
T41	0	303	0	0
T42	69911	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	987	0	0
T4	21986	127	0	0
T5	14947	0	0	0
T7	17570	136	0	0
T8	0	223	0	0
T10	14866	0	0	0
T12	55860	0	0	0
T13	54038	0	0	0
T14	100046	0	0	0
T15	63262	0	0	0
T16	2999	0	0	0
T40	0	258	0	0
T41	0	243	0	0
T42	69911	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567509227	567437396	0	0
T1	3533	3455	0	0
T2	14629	14450	0	0
T3	16155	16086	0	0
T4	93	0	0	0
T5	14947	14751	0	0
T7	99	31	0	0
T9	17004	16950	0	0
T10	14866	14795	0	0
T11	1644	1548	0	0
T15	0	63192	0	0
T16	2999	2920	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567670942	567497677	0	0
T1	3533	3455	0	0
T2	14629	14450	0	0
T3	16155	16086	0	0
T4	21986	9090	0	0
T5	14947	14751	0	0
T7	17570	4817	0	0
T9	17004	16950	0	0
T10	14866	14795	0	0
T11	1644	1548	0	0
T16	2999	2920	0	0