Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49638696	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

23500793

1

T1

162

T2

330

T3

104

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	11447906	1			T1	67		T2	139		T3	43
values[0x0]	30785283	1			T1	214		T2	425		T3	172
values[0x1]	30906300	1			T1	234		T2	445		T3	163

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43223263	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

29916226

1

T1

187

T2

407

T3

142

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	232191	1			T4	1		T10	20		T11	25
valid_sources[0x01]	229176	1			T2	3		T10	24		T5	1
valid_sources[0x02]	236056	1			T2	1		T4	1		T10	25
valid_sources[0x03]	230722	1			T2	8		T12	2		T4	1
valid_sources[0x04]	236354	1			T2	8		T12	2		T4	5
valid_sources[0x05]	229443	1			T2	7		T12	1		T4	2
valid_sources[0x06]	279284	1			T2	7		T12	2		T10	18
valid_sources[0x07]	231493	1			T2	1		T10	22		T11	29
valid_sources[0x08]	229803	1			T2	3		T12	3		T4	3
valid_sources[0x09]	231837	1			T2	5		T12	3		T10	18
valid_sources[0x0a]	230517	1			T2	3		T12	1		T4	3
valid_sources[0x0b]	230416	1			T2	7		T10	26		T5	8
valid_sources[0x0c]	229999	1			T2	1		T10	20		T5	6
valid_sources[0x0d]	233263	1			T2	1		T12	1		T10	14
valid_sources[0x0e]	243036	1			T2	2		T12	2		T4	3
valid_sources[0x0f]	237009	1			T2	3		T12	1		T4	5
valid_sources[0x10]	239998	1			T2	7		T10	22		T11	38
valid_sources[0x11]	231752	1			T2	4		T12	1		T4	1
valid_sources[0x12]	231948	1			T2	4		T12	2		T4	2
valid_sources[0x13]	231651	1			T2	3		T4	1		T10	28
valid_sources[0x14]	252539	1			T2	6		T12	3		T4	1
valid_sources[0x15]	235064	1			T2	3		T12	2		T4	3
valid_sources[0x16]	231865	1			T2	4		T12	2		T4	2
valid_sources[0x17]	230926	1			T2	4		T12	1		T4	1
valid_sources[0x18]	549032	1			T2	4		T12	1		T10	12
valid_sources[0x19]	241112	1			T2	6		T4	2		T10	18
valid_sources[0x1a]	236365	1			T2	4		T12	3		T4	1
valid_sources[0x1b]	228230	1			T2	1		T12	1		T4	1
valid_sources[0x1c]	441781	1			T2	7		T4	2		T10	20
valid_sources[0x1d]	230948	1			T2	1		T4	2		T10	26
valid_sources[0x1e]	234759	1			T2	3		T12	1		T4	3
valid_sources[0x1f]	232127	1			T2	2		T12	1		T4	2
valid_sources[0x20]	492665	1			T2	1		T4	4		T10	11
valid_sources[0x21]	232548	1			T2	3		T12	1		T4	3
valid_sources[0x22]	226317	1			T2	5		T4	1		T10	20
valid_sources[0x23]	244774	1			T2	10		T12	2		T4	6
valid_sources[0x24]	528758	1			T2	3		T12	1		T4	6
valid_sources[0x25]	229175	1			T2	4		T12	1		T4	3
valid_sources[0x26]	229313	1			T2	4		T12	1		T10	21
valid_sources[0x27]	231311	1			T2	5		T12	3		T4	6
valid_sources[0x28]	228529	1			T2	2		T12	4		T10	30
valid_sources[0x29]	631203	1			T2	2		T12	1		T4	4
valid_sources[0x2a]	233842	1			T2	3		T4	2		T10	11
valid_sources[0x2b]	238173	1			T2	7		T4	1		T10	18
valid_sources[0x2c]	231538	1			T2	5		T4	3		T10	23
valid_sources[0x2d]	235656	1			T2	7		T12	2		T4	1
valid_sources[0x2e]	234327	1			T2	1		T12	1		T4	1
valid_sources[0x2f]	234870	1			T2	3		T12	1		T4	1
valid_sources[0x30]	242886	1			T2	1		T4	1		T10	15
valid_sources[0x31]	230368	1			T12	4		T10	18		T11	29
valid_sources[0x32]	235383	1			T2	8		T4	3		T10	25
valid_sources[0x33]	229263	1			T2	3		T12	2		T10	33
valid_sources[0x34]	236488	1			T2	10		T12	1		T4	3
valid_sources[0x35]	581617	1			T1	515		T2	7		T12	1
valid_sources[0x36]	229654	1			T2	1		T12	2		T10	19
valid_sources[0x37]	233734	1			T2	3		T12	4		T4	3
valid_sources[0x38]	705132	1			T2	5		T4	3		T10	10
valid_sources[0x39]	472606	1			T2	3		T12	2		T4	3
valid_sources[0x3a]	229164	1			T2	6		T12	2		T4	1
valid_sources[0x3b]	230838	1			T2	3		T10	20		T11	23
valid_sources[0x3c]	232865	1			T2	5		T12	2		T4	3
valid_sources[0x3d]	704753	1			T2	6		T4	2		T10	21
valid_sources[0x3e]	231033	1			T2	5		T12	3		T10	17
valid_sources[0x3f]	231713	1			T2	3		T12	1		T10	18
valid_sources[0x40]	235953	1			T2	2		T12	1		T10	24
valid_sources[0x41]	238794	1			T2	2		T12	2		T10	16
valid_sources[0x42]	439736	1			T2	5		T12	1		T10	10
valid_sources[0x43]	241270	1			T2	3		T12	1		T4	4
valid_sources[0x44]	230254	1			T2	4		T4	4		T10	16
valid_sources[0x45]	233279	1			T2	5		T12	1		T4	4
valid_sources[0x46]	238067	1			T2	2		T10	22		T5	2
valid_sources[0x47]	228313	1			T2	8		T12	2		T4	7
valid_sources[0x48]	255816	1			T2	3		T12	1		T4	3
valid_sources[0x49]	232567	1			T2	8		T10	19		T5	2
valid_sources[0x4a]	239647	1			T2	7		T4	1		T10	20
valid_sources[0x4b]	238459	1			T2	4		T12	1		T4	2
valid_sources[0x4c]	229272	1			T2	4		T12	2		T4	1
valid_sources[0x4d]	489521	1			T12	1		T4	4		T10	18
valid_sources[0x4e]	228327	1			T2	3		T12	2		T4	3
valid_sources[0x4f]	229761	1			T2	2		T4	3		T10	12
valid_sources[0x50]	234598	1			T2	7		T12	2		T4	5
valid_sources[0x51]	534605	1			T2	2		T12	4		T4	4
valid_sources[0x52]	228228	1			T2	4		T12	1		T4	1
valid_sources[0x53]	228316	1			T2	5		T12	1		T4	3
valid_sources[0x54]	230188	1			T2	2		T12	1		T4	6
valid_sources[0x55]	229221	1			T2	4		T4	1		T10	23
valid_sources[0x56]	230018	1			T2	12		T12	3		T10	14
valid_sources[0x57]	229572	1			T2	4		T12	3		T10	17
valid_sources[0x58]	714976	1			T2	6		T12	1		T4	5
valid_sources[0x59]	670871	1			T2	6		T12	1		T4	1
valid_sources[0x5a]	235066	1			T2	6		T12	1		T4	5
valid_sources[0x5b]	231872	1			T2	2		T4	2		T10	19
valid_sources[0x5c]	236161	1			T2	2		T12	1		T4	2
valid_sources[0x5d]	620707	1			T2	4		T4	1		T10	17
valid_sources[0x5e]	236590	1			T2	3		T12	1		T4	2
valid_sources[0x5f]	231253	1			T2	1		T10	17		T11	33
valid_sources[0x60]	240602	1			T2	10		T12	2		T4	2
valid_sources[0x61]	231024	1			T2	2		T12	1		T10	18
valid_sources[0x62]	256241	1			T2	9		T12	1		T4	5
valid_sources[0x63]	228790	1			T2	2		T12	1		T4	7
valid_sources[0x64]	425612	1			T2	2		T4	1		T10	20
valid_sources[0x65]	233232	1			T2	6		T12	3		T10	25
valid_sources[0x66]	231653	1			T2	4		T12	2		T4	2
valid_sources[0x67]	445706	1			T2	3		T12	2		T10	15
valid_sources[0x68]	431939	1			T2	2		T12	1		T4	3
valid_sources[0x69]	639968	1			T2	4		T4	5		T10	25
valid_sources[0x6a]	231595	1			T2	5		T12	2		T4	3
valid_sources[0x6b]	563900	1			T2	2		T12	1		T4	1
valid_sources[0x6c]	230873	1			T2	5		T4	3		T10	16
valid_sources[0x6d]	233896	1			T2	7		T12	2		T4	1
valid_sources[0x6e]	231732	1			T2	6		T12	1		T10	18
valid_sources[0x6f]	555763	1			T2	3		T12	3		T4	1
valid_sources[0x70]	230057	1			T12	4		T10	14		T11	44
valid_sources[0x71]	238308	1			T2	2		T12	1		T4	6
valid_sources[0x72]	231996	1			T2	5		T10	20		T11	22
valid_sources[0x73]	532450	1			T2	3		T12	2		T10	15
valid_sources[0x74]	232101	1			T2	2		T4	1		T10	18
valid_sources[0x75]	235764	1			T2	4		T12	1		T4	3
valid_sources[0x76]	463750	1			T2	5		T12	2		T4	3
valid_sources[0x77]	230409	1			T2	7		T12	2		T4	2
valid_sources[0x78]	241776	1			T2	1		T12	2		T4	1
valid_sources[0x79]	232534	1			T2	4		T12	1		T4	1
valid_sources[0x7a]	231041	1			T2	7		T12	2		T4	7
valid_sources[0x7b]	673426	1			T2	4		T4	1		T10	16
valid_sources[0x7c]	238489	1			T2	9		T12	1		T4	2
valid_sources[0x7d]	229341	1			T2	8		T4	2		T10	20
valid_sources[0x7e]	244159	1			T2	8		T12	1		T4	4
valid_sources[0x7f]	593927	1			T2	1		T12	2		T10	21
valid_sources[0x80]	229609	1			T2	1		T12	1		T10	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5512123

1

T1

38

T2

67

T3

26

values[0x0]

all_enables

biggest_size

11487531

1

T1

66

T2

172

T3

48

values[0x1]

all_enables

biggest_size

6501139

1

T1

58

T2

91

T3

30