Module Definition
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Module : prim_esc_sender
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_sender.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_esc_sev[0].u_esc_sender 100.00 100.00
tb.dut.gen_esc_sev[1].u_esc_sender 100.00 100.00
tb.dut.gen_esc_sev[2].u_esc_sender 100.00 100.00
tb.dut.gen_esc_sev[3].u_esc_sender 100.00 100.00


Module Instance : tb.dut.gen_esc_sev[0].u_esc_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.96 100.00 99.87 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_esc_sev[1].u_esc_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.96 100.00 99.87 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_esc_sev[2].u_esc_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.96 100.00 99.87 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_esc_sev[3].u_esc_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.96 100.00 99.87 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_esc_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T5,T7 Yes T4,T5,T7 INPUT
ping_ok_o Yes Yes T4,T5,T7 Yes T4,T5,T7 OUTPUT
integ_fail_o Yes Yes T3,T12,T6 Yes T3,T12,T6 OUTPUT
esc_req_i Yes Yes T2,T3,T12 Yes T2,T3,T12 INPUT
esc_rx_i.resp_n Yes Yes T2,T4,T5 Yes T2,T4,T5 INPUT
esc_rx_i.resp_p Yes Yes T2,T4,T5 Yes T2,T4,T5 INPUT
esc_tx_o.esc_n Yes Yes T2,T3,T12 Yes T2,T3,T12 OUTPUT
esc_tx_o.esc_p Yes Yes T2,T3,T12 Yes T2,T3,T12 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_esc_sev[0].u_esc_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T5,T7 Yes T4,T5,T7 INPUT
ping_ok_o Yes Yes T4,T5,T7 Yes T4,T5,T7 OUTPUT
integ_fail_o Yes Yes T3,T12,T6 Yes T3,T12,T6 OUTPUT
esc_req_i Yes Yes T2,T3,T12 Yes T2,T3,T12 INPUT
esc_rx_i.resp_n Yes Yes T2,T4,T5 Yes T2,T4,T5 INPUT
esc_rx_i.resp_p Yes Yes T2,T4,T5 Yes T2,T4,T5 INPUT
esc_tx_o.esc_n Yes Yes T2,T3,T12 Yes T2,T3,T12 OUTPUT
esc_tx_o.esc_p Yes Yes T2,T3,T12 Yes T2,T3,T12 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_esc_sev[1].u_esc_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T5,T7 Yes T4,T5,T7 INPUT
ping_ok_o Yes Yes T4,T5,T7 Yes T4,T5,T7 OUTPUT
integ_fail_o Yes Yes T3,T12,T6 Yes T3,T12,T6 OUTPUT
esc_req_i Yes Yes T3,T12,T28 Yes T3,T12,T28 INPUT
esc_rx_i.resp_n Yes Yes T4,T5,T28 Yes T4,T5,T28 INPUT
esc_rx_i.resp_p Yes Yes T4,T5,T28 Yes T4,T5,T28 INPUT
esc_tx_o.esc_n Yes Yes T3,T12,T4 Yes T3,T12,T4 OUTPUT
esc_tx_o.esc_p Yes Yes T3,T12,T4 Yes T3,T12,T4 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_esc_sev[2].u_esc_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T5,T7 Yes T4,T5,T7 INPUT
ping_ok_o Yes Yes T4,T5,T7 Yes T4,T5,T7 OUTPUT
integ_fail_o Yes Yes T3,T12,T6 Yes T3,T12,T6 OUTPUT
esc_req_i Yes Yes T3,T12,T6 Yes T3,T12,T6 INPUT
esc_rx_i.resp_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
esc_rx_i.resp_p Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
esc_tx_o.esc_n Yes Yes T3,T12,T4 Yes T3,T12,T4 OUTPUT
esc_tx_o.esc_p Yes Yes T3,T12,T4 Yes T3,T12,T4 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_esc_sev[3].u_esc_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T4,T5,T7 Yes T4,T5,T7 INPUT
ping_ok_o Yes Yes T4,T5,T7 Yes T4,T5,T7 OUTPUT
integ_fail_o Yes Yes T3,T12,T6 Yes T3,T12,T6 OUTPUT
esc_req_i Yes Yes T3,T12,T28 Yes T3,T12,T28 INPUT
esc_rx_i.resp_n Yes Yes T4,T5,T28 Yes T4,T5,T28 INPUT
esc_rx_i.resp_p Yes Yes T4,T5,T28 Yes T4,T5,T28 INPUT
esc_tx_o.esc_n Yes Yes T3,T12,T4 Yes T3,T12,T4 OUTPUT
esc_tx_o.esc_p Yes Yes T3,T12,T4 Yes T3,T12,T4 OUTPUT

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