Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T6
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T12,T15
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T12

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	16022	0	0
DisabledNoTrigBkwd_A	2147483647	679231	0	0
DisabledNoTrigFwd_A	2147483647	1170020944	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16022	0	0
T3	3651	1065	0	0
T4	25732	0	0	0
T5	35530	0	0	0
T6	34428	0	0	0
T8	82584	0	0	0
T9	39079	0	0	0
T10	36056	0	0	0
T11	45464	0	0	0
T12	5194	304	0	0
T14	1742	961	0	0
T15	0	388	0	0
T16	43811	0	0	0
T28	70662	0	0	0
T29	92116	0	0	0
T32	108382	0	0	0
T36	88560	0	0	0
T47	107886	0	0	0
T49	78949	0	0	0
T55	0	307	0	0
T61	20565	0	0	0
T62	31133	0	0	0
T63	6516	0	0	0
T64	8439	0	0	0
T85	0	1089	0	0
T156	0	707	0	0
T170	0	297	0	0
T245	0	327	0	0
T246	0	757	0	0
T247	0	948	0	0
T248	0	1183	0	0
T249	0	644	0	0
T250	0	642	0	0
T251	0	1568	0	0
T252	0	1276	0	0
T253	0	792	0	0
T254	0	861	0	0
T255	0	914	0	0
T256	0	992	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	679231	0	0
T2	4616	3	0	0
T3	7302	20	0	0
T4	25732	0	0	0
T5	35530	0	0	0
T6	34428	0	0	0
T8	82584	0	0	0
T9	39079	0	0	0
T10	36056	0	0	0
T11	45464	0	0	0
T12	5194	3	0	0
T14	1742	28	0	0
T16	0	36	0	0
T17	0	57	0	0
T18	0	21	0	0
T28	70662	5	0	0
T29	46058	20	0	0
T32	108382	2	0	0
T36	88560	0	0	0
T44	0	3	0	0
T46	0	37	0	0
T47	107886	44	0	0
T49	78949	0	0	0
T50	0	10	0	0
T54	0	44	0	0
T55	0	9	0	0
T56	0	21	0	0
T57	0	15	0	0
T58	0	45	0	0
T59	0	3	0	0
T60	0	49	0	0
T61	20565	0	0	0
T62	31133	0	0	0
T63	6516	0	0	0
T64	8439	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1170020944	0	0
T1	6244	4264	0	0
T2	18464	14205	0	0
T3	14604	8944	0	0
T4	51464	8739	0	0
T5	71060	8207	0	0
T6	68856	18252	0	0
T10	72112	20253	0	0
T11	90928	43035	0	0
T12	10388	8571	0	0
T28	141324	107690	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T12 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T1,T6,T11
1	1	Covered	T2,T12,T10

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T246,T249
1	1	Covered	T2,T12,T10

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T12,T28

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	538552980	2619	0	0
DisabledNoTrigBkwd_A	538552980	198912	0	0
DisabledNoTrigFwd_A	538552980	240471078	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	2619	0	0
T4	12866	0	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	0	0	0
T11	22732	0	0	0
T12	2597	304	0	0
T16	43811	0	0	0
T28	35331	0	0	0
T29	46058	0	0	0
T246	0	757	0	0
T249	0	644	0	0
T255	0	914	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	198912	0	0
T2	4616	3	0	0
T3	3651	0	0	0
T4	12866	0	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	0	0	0
T11	22732	0	0	0
T12	2597	3	0	0
T16	0	36	0	0
T17	0	21	0	0
T18	0	1	0	0
T28	35331	5	0	0
T29	0	20	0	0
T44	0	3	0	0
T50	0	2	0	0
T54	0	44	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	240471078	0	0
T1	1561	1508	0	0
T2	4616	582	0	0
T3	3651	2221	0	0
T4	12866	2164	0	0
T5	17765	2034	0	0
T6	17214	4563	0	0
T10	18028	759	0	0
T11	22732	4154	0	0
T12	2597	2128	0	0
T28	35331	5531	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T4 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T4
1	0	Covered	T1,T10,T11
1	1	Covered	T4,T5,T11

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T55,T251
1	1	Covered	T4,T5,T11

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	538552980	4112	0	0
DisabledNoTrigBkwd_A	538552980	152622	0	0
DisabledNoTrigFwd_A	538552980	306810257	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	4112	0	0
T9	39079	0	0	0
T14	1742	961	0	0
T32	108382	0	0	0
T36	88560	0	0	0
T47	107886	0	0	0
T49	78949	0	0	0
T55	0	307	0	0
T61	20565	0	0	0
T62	31133	0	0	0
T63	6516	0	0	0
T64	8439	0	0	0
T251	0	1568	0	0
T252	0	1276	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	152622	0	0
T9	39079	0	0	0
T14	1742	28	0	0
T32	108382	2	0	0
T36	88560	0	0	0
T46	0	27	0	0
T47	107886	16	0	0
T49	78949	0	0	0
T55	0	9	0	0
T56	0	12	0	0
T57	0	15	0	0
T58	0	45	0	0
T59	0	3	0	0
T60	0	49	0	0
T61	20565	0	0	0
T62	31133	0	0	0
T63	6516	0	0	0
T64	8439	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	306810257	0	0
T1	1561	1508	0	0
T2	4616	4541	0	0
T3	3651	2227	0	0
T4	12866	2182	0	0
T5	17765	2041	0	0
T6	17214	4563	0	0
T10	18028	17956	0	0
T11	22732	4158	0	0
T12	2597	2137	0	0
T28	35331	31695	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T12
1	0	Covered	T11,T16,T13
1	1	Covered	T1,T3,T10

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T247
1	1	Covered	T1,T3,T10

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T15,T17

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	538552980	5087	0	0
DisabledNoTrigBkwd_A	538552980	167668	0	0
DisabledNoTrigFwd_A	538552980	314202493	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	5087	0	0
T3	3651	1065	0	0
T4	12866	0	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	0	0	0
T11	22732	0	0	0
T12	2597	0	0	0
T15	0	388	0	0
T28	35331	0	0	0
T29	46058	0	0	0
T247	0	948	0	0
T248	0	1183	0	0
T250	0	642	0	0
T254	0	861	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	167668	0	0
T3	3651	20	0	0
T4	12866	0	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	0	0	0
T11	22732	0	0	0
T12	2597	0	0	0
T15	0	9	0	0
T17	0	36	0	0
T18	0	20	0	0
T28	35331	0	0	0
T29	46058	0	0	0
T46	0	10	0	0
T47	0	28	0	0
T50	0	8	0	0
T56	0	9	0	0
T95	0	10	0	0
T96	0	133	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	314202493	0	0
T1	1561	622	0	0
T2	4616	4541	0	0
T3	3651	2240	0	0
T4	12866	2190	0	0
T5	17765	2057	0	0
T6	17214	4563	0	0
T10	18028	767	0	0
T11	22732	15648	0	0
T12	2597	2142	0	0
T28	35331	35232	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T4 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T12
1	0	Covered	T11,T16,T13
1	1	Covered	T1,T10,T11

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T245,T170,T85
1	1	Covered	T1,T10,T11

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	538552980	4204	0	0
DisabledNoTrigBkwd_A	538552980	160029	0	0
DisabledNoTrigFwd_A	538552980	308537116	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	4204	0	0
T24	47038	0	0	0
T25	24817	0	0	0
T57	134413	0	0	0
T85	0	1089	0	0
T98	6900	0	0	0
T106	39982	0	0	0
T107	51573	0	0	0
T156	0	707	0	0
T169	50708	0	0	0
T170	3546	297	0	0
T245	1100	327	0	0
T253	0	792	0	0
T256	0	992	0	0
T257	6090	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	160029	0	0
T7	63575	0	0	0
T13	45743	0	0	0
T15	1110	0	0	0
T16	43811	35	0	0
T17	62926	3	0	0
T18	19012	162	0	0
T30	57586	0	0	0
T31	0	27	0	0
T44	89273	0	0	0
T46	0	23	0	0
T47	0	20	0	0
T50	44513	8	0	0
T95	0	20	0	0
T96	0	19	0	0
T105	7867	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	308537116	0	0
T1	1561	626	0	0
T2	4616	4541	0	0
T3	3651	2256	0	0
T4	12866	2203	0	0
T5	17765	2075	0	0
T6	17214	4563	0	0
T10	18028	771	0	0
T11	22732	19075	0	0
T12	2597	2164	0	0
T28	35331	35232	0	0