Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T2 T3 T12 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T2 T3 T12 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T2 T3 T12 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T10 T11 
159        1/1                    state_d = TimeoutSt;
           Tests:       T2 T10 T11 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T2 T10 T11 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T2 T10 T11 
172        1/1                    state_d    = Phase0St;
           Tests:       T11 T18 T32 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T11 T18 T32 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T11 T18 T32 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T11 T18 T32 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T2 T10 T11 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T10 T11 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T2 T10 T11 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T10 T11 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T3 T12 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T2 T3 T12 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T2 T3 T12 
190        1/1                  esc_state_o = Phase0;
           Tests:       T2 T3 T12 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T2 T3 T12 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T2 T3 T12 
194        1/1                    state_d = IdleSt;
           Tests:       T33 T34 T35 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T33 T34 T35 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T33 T34 T35 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T3 T12 
198        1/1                    state_d = Phase1St;
           Tests:       T2 T3 T12 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T3 T12 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T3 T12 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T3 T12 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T2 T3 T12 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T2 T3 T12 
207        1/1                  esc_state_o = Phase1;
           Tests:       T2 T3 T12 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T2 T3 T12 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T2 T3 T12 
211        1/1                    state_d = IdleSt;
           Tests:       T36 T37 T38 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T36 T37 T38 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T36 T37 T38 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T3 T12 
215        1/1                    state_d = Phase2St;
           Tests:       T2 T3 T12 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T3 T12 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T3 T12 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T3 T12 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T2 T3 T12 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T2 T3 T12 
224        1/1                  esc_state_o = Phase2;
           Tests:       T2 T3 T12 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T2 T3 T12 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T2 T3 T12 
229        1/1                    state_d = IdleSt;
           Tests:       T2 T39 T40 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T39 T40 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T2 T39 T40 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T3 T12 
233        1/1                    state_d = Phase3St;
           Tests:       T3 T12 T28 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T12 T28 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T12 T28 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T3 T12 T28 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T3 T12 T28 
241        1/1                  esc_state_o = Phase3;
           Tests:       T3 T12 T28 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T3 T12 T28 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T3 T12 T28 
245        1/1                    state_d = IdleSt;
           Tests:       T41 T42 T43 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T41 T42 T43 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T41 T42 T43 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T12 T28 
249        1/1                    state_d = TerminalSt;
           Tests:       T3 T12 T28 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T12 T28 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T3 T12 T28 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T3 T12 T28 
259        1/1                  esc_state_o = Terminal;
           Tests:       T3 T12 T28 
260        1/1                  if (clr_i) begin
           Tests:       T3 T12 T28 
261        1/1                    state_d = IdleSt;
           Tests:       T29 T18 T44 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T6 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T6 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T6 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T6 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Covered	T2,T3,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T28
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T45
1	1	1	Covered	T2,T3,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T3,T12,T15
1	1	0	Covered	T10,T11,T16
1	1	1	Covered	T2,T10,T11

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T11
0	1	Covered	T11,T32,T46
1	0	Covered	T18,T47,T48

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T10,T11
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T18,T47,T48

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T11
1	0	Not Covered
1	1	Covered	T11,T32,T46

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T28,T29
1	Covered	T3,T12,T11

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T16,T17,T49

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T50,T44,T32

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T11
1	Covered	T28,T29,T18

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T6,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T2,T3,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T3,T12,T28

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T3,T12,T29

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T3,T12,T28

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T6,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T12
Phase1St	198	Covered	T2,T3,T12
Phase2St	215	Covered	T2,T3,T12
Phase3St	233	Covered	T3,T12,T28
TerminalSt	249	Covered	T3,T12,T28
TimeoutSt	159	Covered	T2,T10,T11

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T6,T8,T9
IdleSt->Phase0St	152	Covered	T2,T3,T12
IdleSt->TimeoutSt	159	Covered	T2,T10,T11
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T33,T51,T40
Phase0St->Phase1St	198	Covered	T2,T3,T12
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T36,T37,T43
Phase1St->Phase2St	215	Covered	T2,T3,T12
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T2,T39,T40
Phase2St->Phase3St	233	Covered	T3,T12,T28
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T41,T42,T43
Phase3St->TerminalSt	249	Covered	T3,T12,T28
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T29,T18,T44
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T2,T10,T11
TimeoutSt->Phase0St	172	Covered	T11,T18,T32

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T11
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T11,T18,T32
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T11
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T11
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T33,T34,T35
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T28,T11
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T36,T37,T38
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T28,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T39,T40
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T12,T28
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T28,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T41,T42,T43
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T12,T28
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T28,T11,T29
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T29,T18,T44
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T12,T28
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	942	0	0
CheckAccumTrig0_A	2147483647	2141	0	0
CheckAccumTrig1_A	2147483647	123	0	0
CheckClr_A	2147483647	1003	0	0
CheckEn_A	2147483647	894789423	0	0
CheckPhase0_A	2147483647	2386	0	0
CheckPhase1_A	2147483647	2328	0	0
CheckPhase2_A	2147483647	2281	0	0
CheckPhase3_A	2147483647	2236	0	0
CheckTimeout0_A	2147483647	1980	0	0
CheckTimeoutSt1_A	2147483647	238662	0	0
CheckTimeoutSt2_A	2147483647	1672	0	0
CheckTimeoutStTrig_A	2147483647	176	0	0
ErrorStAllEscAsserted_A	2147483647	5169	0	0
ErrorStIsTerminal_A	2147483647	4209	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	942	0	0
T6	68856	93	0	0
T8	165168	250	0	0
T9	0	232	0	0
T11	90928	0	0	0
T13	182972	0	0	0
T15	4440	0	0	0
T16	175244	0	0	0
T17	251704	0	0	0
T18	76048	0	0	0
T29	184232	0	0	0
T30	230344	0	0	0
T52	0	129	0	0
T53	0	238	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2141	0	0
T2	4616	1	0	0
T3	7302	1	0	0
T4	25732	0	0	0
T5	35530	0	0	0
T6	34428	0	0	0
T8	82584	0	0	0
T9	39079	0	0	0
T10	36056	0	0	0
T11	45464	0	0	0
T12	5194	1	0	0
T14	1742	1	0	0
T16	0	1	0	0
T17	0	2	0	0
T18	0	2	0	0
T28	70662	1	0	0
T29	46058	3	0	0
T32	108382	1	0	0
T36	88560	0	0	0
T44	0	3	0	0
T46	0	2	0	0
T47	107886	1	0	0
T49	78949	0	0	0
T50	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	4	0	0
T57	0	6	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	20565	0	0	0
T62	31133	0	0	0
T63	6516	0	0	0
T64	8439	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	123	0	0
T18	19012	1	0	0
T20	375082	0	0	0
T39	18850	0	0	0
T43	0	1	0	0
T47	0	1	0	0
T48	78276	1	0	0
T51	0	1	0	0
T60	15670	0	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	776695	2	0	0
T71	16192	1	0	0
T72	0	2	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	3	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	25451	0	0	0
T82	53283	0	0	0
T83	234656	0	0	0
T84	36429	0	0	0
T85	4697	0	0	0
T86	578135	0	0	0
T87	31493	0	0	0
T88	49533	0	0	0
T89	44365	0	0	0
T90	618927	0	0	0
T91	182551	0	0	0
T92	141326	0	0	0
T93	42441	0	0	0
T94	780546	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1003	0	0
T2	4616	1	0	0
T3	3651	0	0	0
T4	12866	0	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	0	0	0
T11	22732	0	0	0
T12	2597	0	0	0
T18	19012	2	0	0
T22	63717	0	0	0
T28	35331	0	0	0
T29	0	2	0	0
T32	216764	1	0	0
T36	88560	2	0	0
T42	0	2	0	0
T44	0	2	0	0
T46	0	4	0	0
T47	107886	0	0	0
T51	0	2	0	0
T52	16729	0	0	0
T55	1012	0	0	0
T56	0	3	0	0
T57	0	4	0	0
T61	20565	0	0	0
T62	31133	0	0	0
T63	6516	0	0	0
T64	8439	0	0	0
T95	0	1	0	0
T96	0	2	0	0
T97	0	4	0	0
T98	0	1	0	0
T99	0	3	0	0
T100	0	3	0	0
T101	0	2	0	0
T102	0	1	0	0
T103	0	5	0	0
T104	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	894789423	0	0
T1	6244	4262	0	0
T2	18464	14202	0	0
T3	14604	8944	0	0
T4	51464	8735	0	0
T5	71060	8203	0	0
T6	1320	1116	0	0
T10	72112	20252	0	0
T11	90928	43033	0	0
T12	10388	8571	0	0
T28	141324	107687	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2386	0	0
T2	4616	1	0	0
T3	7302	1	0	0
T4	25732	0	0	0
T5	35530	0	0	0
T6	34428	0	0	0
T7	63575	0	0	0
T8	123876	0	0	0
T10	36056	0	0	0
T11	68196	1	0	0
T12	5194	1	0	0
T13	91486	0	0	0
T14	0	1	0	0
T15	2220	0	0	0
T16	87622	1	0	0
T17	125852	2	0	0
T18	38024	3	0	0
T28	70662	1	0	0
T29	92116	3	0	0
T30	115172	0	0	0
T32	0	2	0	0
T44	89273	3	0	0
T46	0	2	0	0
T47	0	2	0	0
T50	89026	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	4	0	0
T57	0	5	0	0
T58	0	1	0	0
T59	0	1	0	0
T105	7867	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2328	0	0
T2	4616	1	0	0
T3	7302	1	0	0
T4	25732	0	0	0
T5	35530	0	0	0
T6	34428	0	0	0
T7	63575	0	0	0
T8	123876	0	0	0
T10	36056	0	0	0
T11	68196	1	0	0
T12	5194	1	0	0
T13	91486	0	0	0
T14	0	1	0	0
T15	2220	0	0	0
T16	87622	1	0	0
T17	125852	2	0	0
T18	38024	3	0	0
T28	70662	1	0	0
T29	92116	3	0	0
T30	115172	0	0	0
T32	0	2	0	0
T44	89273	3	0	0
T46	0	2	0	0
T47	0	2	0	0
T50	89026	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	4	0	0
T57	0	5	0	0
T58	0	1	0	0
T59	0	1	0	0
T105	7867	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2281	0	0
T3	3651	1	0	0
T4	25732	0	0	0
T5	35530	0	0	0
T6	34428	0	0	0
T7	63575	0	0	0
T8	123876	0	0	0
T10	36056	0	0	0
T11	68196	1	0	0
T12	5194	1	0	0
T13	91486	0	0	0
T14	0	1	0	0
T15	2220	0	0	0
T16	131433	1	0	0
T17	125852	2	0	0
T18	38024	3	0	0
T28	70662	1	0	0
T29	138174	3	0	0
T30	115172	0	0	0
T32	0	2	0	0
T44	89273	3	0	0
T46	0	2	0	0
T47	0	2	0	0
T49	0	1	0	0
T50	89026	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	4	0	0
T57	0	5	0	0
T58	0	1	0	0
T59	0	1	0	0
T105	7867	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2236	0	0
T3	3651	1	0	0
T4	25732	0	0	0
T5	35530	0	0	0
T6	34428	0	0	0
T7	63575	0	0	0
T8	123876	0	0	0
T10	36056	0	0	0
T11	68196	1	0	0
T12	5194	1	0	0
T13	91486	0	0	0
T14	0	1	0	0
T15	2220	0	0	0
T16	131433	1	0	0
T17	125852	2	0	0
T18	38024	3	0	0
T28	70662	1	0	0
T29	138174	3	0	0
T30	115172	0	0	0
T32	0	2	0	0
T44	89273	3	0	0
T46	0	2	0	0
T47	0	2	0	0
T49	0	1	0	0
T50	89026	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	4	0	0
T57	0	5	0	0
T58	0	1	0	0
T59	0	1	0	0
T105	7867	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1980	0	0
T2	4616	1	0	0
T3	3651	0	0	0
T4	12866	0	0	0
T5	53295	0	0	0
T6	51642	0	0	0
T8	165168	0	0	0
T10	54084	14	0	0
T11	90928	6	0	0
T12	2597	0	0	0
T13	45743	10	0	0
T15	3330	0	0	0
T16	131433	0	0	0
T17	62926	0	0	0
T18	19012	4	0	0
T28	105993	0	0	0
T29	138174	0	0	0
T30	172758	0	0	0
T32	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T46	0	6	0	0
T47	0	1	0	0
T50	44513	0	0	0
T60	0	2	0	0
T61	0	7	0	0
T62	0	1	0	0
T63	0	3	0	0
T81	0	9	0	0
T100	0	3	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	4	0	0
T109	0	1	0	0
T110	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	238662	0	0
T2	4616	41	0	0
T3	3651	0	0	0
T4	12866	0	0	0
T5	53295	0	0	0
T6	51642	0	0	0
T8	165168	0	0	0
T10	54084	995	0	0
T11	90928	614	0	0
T12	2597	0	0	0
T13	45743	1332	0	0
T15	3330	0	0	0
T16	131433	0	0	0
T17	62926	0	0	0
T18	19012	523	0	0
T28	105993	0	0	0
T29	138174	0	0	0
T30	172758	0	0	0
T32	0	425	0	0
T42	0	144	0	0
T44	0	220	0	0
T46	0	765	0	0
T50	44513	0	0	0
T60	0	85	0	0
T61	0	687	0	0
T62	0	127	0	0
T63	0	632	0	0
T81	0	691	0	0
T100	0	1379	0	0
T106	0	48	0	0
T107	0	208	0	0
T108	0	758	0	0
T109	0	943	0	0
T110	0	813	0	0
T111	0	123	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1672	0	0
T2	4616	1	0	0
T3	3651	0	0	0
T4	12866	0	0	0
T5	35530	0	0	0
T6	34428	0	0	0
T7	63575	0	0	0
T8	82584	0	0	0
T10	36056	14	0	0
T11	45464	5	0	0
T12	2597	0	0	0
T13	45743	10	0	0
T14	1742	0	0	0
T17	62926	0	0	0
T18	19012	3	0	0
T28	70662	0	0	0
T29	46058	0	0	0
T42	0	2	0	0
T44	89273	2	0	0
T46	0	3	0	0
T49	78949	0	0	0
T50	44513	0	0	0
T54	42509	0	0	0
T60	0	2	0	0
T61	0	7	0	0
T62	0	1	0	0
T63	0	3	0	0
T81	0	9	0	0
T100	0	1	0	0
T105	7867	0	0	0
T106	0	1	0	0
T108	0	4	0	0
T109	0	1	0	0
T110	0	4	0	0
T111	0	2	0	0
T112	0	7	0	0
T113	0	5	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	176	0	0
T8	41292	0	0	0
T11	22732	1	0	0
T13	45743	0	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T17	62926	0	0	0
T18	19012	0	0	0
T23	105653	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T31	91617	0	0	0
T32	0	1	0	0
T35	0	2	0	0
T40	0	2	0	0
T46	25175	3	0	0
T50	44513	0	0	0
T53	41980	0	0	0
T56	50548	0	0	0
T67	0	2	0	0
T74	0	5	0	0
T75	0	1	0	0
T89	0	1	0	0
T91	0	2	0	0
T94	0	1	0	0
T95	32705	0	0	0
T96	42770	0	0	0
T97	24485	0	0	0
T100	0	2	0	0
T104	0	1	0	0
T107	51573	2	0	0
T110	0	2	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	1	0	0
T116	0	2	0	0
T117	0	1	0	0
T118	0	2	0	0
T119	20216	0	0	0
T120	11625	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5169	0	0
T6	68856	598	0	0
T8	165168	1256	0	0
T9	0	1294	0	0
T11	90928	0	0	0
T13	182972	0	0	0
T15	4440	0	0	0
T16	175244	0	0	0
T17	251704	0	0	0
T18	76048	0	0	0
T29	184232	0	0	0
T30	230344	0	0	0
T52	0	687	0	0
T53	0	1334	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4209	0	0
T6	68856	478	0	0
T8	165168	1016	0	0
T9	0	1054	0	0
T11	90928	0	0	0
T13	182972	0	0	0
T15	4440	0	0	0
T16	175244	0	0	0
T17	251704	0	0	0
T18	76048	0	0	0
T29	184232	0	0	0
T30	230344	0	0	0
T52	0	567	0	0
T53	0	1094	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6244	6032	0	0
T2	18464	18164	0	0
T3	14604	14224	0	0
T4	51464	50692	0	0
T5	71060	70468	0	0
T6	384	184	0	0
T10	72112	71824	0	0
T11	90928	90588	0	0
T12	10388	10096	0	0
T28	141324	140928	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6244	6032	0	0
T2	18464	18164	0	0
T3	14604	14224	0	0
T4	51464	50692	0	0
T5	71060	70468	0	0
T6	68856	18252	0	0
T10	72112	71824	0	0
T11	90928	90588	0	0
T12	10388	10096	0	0
T28	141324	140928	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T4 T5 T7 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T4 T5 T7 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T4 T5 T7 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T11 T13 T32 
159        1/1                    state_d = TimeoutSt;
           Tests:       T11 T13 T32 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T11 T13 T32 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T11 T13 T32 
172        1/1                    state_d    = Phase0St;
           Tests:       T11 T32 T100 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T11 T32 T100 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T11 T32 T100 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T11 T32 T100 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T11 T13 T32 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T11 T13 T32 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T13 T61 T63 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T61 T63 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T11 T14 T32 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T11 T14 T32 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T11 T14 T32 
190        1/1                  esc_state_o = Phase0;
           Tests:       T11 T14 T32 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T11 T14 T32 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T11 T14 T32 
194        1/1                    state_d = IdleSt;
           Tests:       T121 T122 T123 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T121 T122 T123 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T121 T122 T123 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T11 T14 T32 
198        1/1                    state_d = Phase1St;
           Tests:       T11 T14 T32 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T14 T32 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T11 T14 T32 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T11 T14 T32 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T11 T14 T32 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T11 T14 T32 
207        1/1                  esc_state_o = Phase1;
           Tests:       T11 T14 T32 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T11 T14 T32 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T11 T14 T32 
211        1/1                    state_d = IdleSt;
           Tests:       T124 T75 T125 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T124 T75 T125 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T124 T75 T125 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T11 T14 T32 
215        1/1                    state_d = Phase2St;
           Tests:       T11 T14 T32 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T14 T32 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T11 T14 T32 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T11 T14 T32 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T11 T14 T32 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T11 T14 T32 
224        1/1                  esc_state_o = Phase2;
           Tests:       T11 T14 T32 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T11 T14 T32 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T11 T14 T32 
229        1/1                    state_d = IdleSt;
           Tests:       T74 T126 T127 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T74 T126 T127 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T74 T126 T127 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T11 T14 T32 
233        1/1                    state_d = Phase3St;
           Tests:       T11 T14 T32 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T14 T32 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T11 T14 T32 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T11 T14 T32 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T11 T14 T32 
241        1/1                  esc_state_o = Phase3;
           Tests:       T11 T14 T32 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T11 T14 T32 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T11 T14 T32 
245        1/1                    state_d = IdleSt;
           Tests:       T70 T128 T129 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T70 T128 T129 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T70 T128 T129 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T11 T14 T32 
249        1/1                    state_d = TerminalSt;
           Tests:       T11 T14 T32 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T14 T32 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T11 T14 T32 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T11 T14 T32 
259        1/1                  esc_state_o = Terminal;
           Tests:       T11 T14 T32 
260        1/1                  if (clr_i) begin
           Tests:       T11 T14 T32 
261        1/1                    state_d = IdleSt;
           Tests:       T32 T56 T57 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T6 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T6 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T6 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T6 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Covered	T4,T5,T11
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T11

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T12,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T13,T18
1	0	1	Covered	T14,T36,T55
1	1	0	Covered	T10,T17,T18
1	1	1	Covered	T11,T13,T32

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T32
0	1	Covered	T11,T32,T100
1	0	Covered	T70,T71,T72

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T11,T13,T32
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T70,T71,T72

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T32
1	0	Not Covered
1	1	Covered	T11,T32,T100

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T32,T47,T56
1	Covered	T11,T14,T55

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T11,T14,T32
1	Covered	T32,T56,T100

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T11,T14,T32
1	Covered	T32,T47,T42

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T11,T14,T32
1	Covered	T56,T58,T59

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T6,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T11,T14,T32

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T14,T32,T55

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T14,T32,T47

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T14,T32,T55

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T6,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T11,T14,T32
Phase1St	198	Covered	T11,T14,T32
Phase2St	215	Covered	T11,T14,T32
Phase3St	233	Covered	T11,T14,T32
TerminalSt	249	Covered	T11,T14,T32
TimeoutSt	159	Covered	T11,T13,T32

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T6,T8,T9
IdleSt->Phase0St	152	Covered	T14,T32,T47
IdleSt->TimeoutSt	159	Covered	T11,T13,T32
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T51,T74,T121
Phase0St->Phase1St	198	Covered	T11,T14,T32
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T124,T75,T118
Phase1St->Phase2St	215	Covered	T11,T14,T32
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T74,T126,T127
Phase2St->Phase3St	233	Covered	T11,T14,T32
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T43,T70,T128
Phase3St->TerminalSt	249	Covered	T11,T14,T32
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T32,T56,T57
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T13,T61,T63
TimeoutSt->Phase0St	172	Covered	T11,T32,T100

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T13,T32
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T11,T32,T100
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T11,T13,T32
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T13,T61,T63
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T121,T122,T123
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T11,T14,T32
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T11,T32,T47
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T124,T75,T125
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T11,T14,T32
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T11,T32,T47
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T74,T126,T127
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T11,T14,T32
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T11,T32,T47
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T70,T128,T129
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T11,T14,T32
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T11,T32,T47
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T32,T56,T57
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T11,T14,T32
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	538552980	214	0	0
CheckAccumTrig0_A	538552980	441	0	0
CheckAccumTrig1_A	538552980	23	0	0
CheckClr_A	538552980	214	0	0
CheckEn_A	538398130	251358770	0	0
CheckPhase0_A	538552980	498	0	0
CheckPhase1_A	538552980	485	0	0
CheckPhase2_A	538552980	473	0	0
CheckPhase3_A	538552980	463	0	0
CheckTimeout0_A	538552980	445	0	0
CheckTimeoutSt1_A	538552980	58080	0	0
CheckTimeoutSt2_A	538552980	380	0	0
CheckTimeoutStTrig_A	538552980	40	0	0
ErrorStAllEscAsserted_A	538552980	1276	0	0
ErrorStIsTerminal_A	538552980	1036	0	0
EscStateOut_A	538397058	538328675	0	0
u_state_regs_A	538552980	538382136	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	214	0	0
T6	17214	34	0	0
T8	41292	52	0	0
T9	0	50	0	0
T11	22732	0	0	0
T13	45743	0	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T17	62926	0	0	0
T18	19012	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T52	0	22	0	0
T53	0	56	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	441	0	0
T9	39079	0	0	0
T14	1742	1	0	0
T32	108382	1	0	0
T36	88560	0	0	0
T46	0	1	0	0
T47	107886	1	0	0
T49	78949	0	0	0
T55	0	1	0	0
T56	0	3	0	0
T57	0	5	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	20565	0	0	0
T62	31133	0	0	0
T63	6516	0	0	0
T64	8439	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	23	0	0
T70	776695	1	0	0
T71	16192	1	0	0
T72	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	3	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T87	31493	0	0	0
T88	49533	0	0	0
T89	44365	0	0	0
T90	618927	0	0	0
T91	182551	0	0	0
T92	141326	0	0	0
T93	42441	0	0	0
T94	780546	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	214	0	0
T22	63717	0	0	0
T32	108382	1	0	0
T36	88560	0	0	0
T42	0	1	0	0
T47	107886	0	0	0
T51	0	2	0	0
T52	16729	0	0	0
T55	1012	0	0	0
T56	0	2	0	0
T57	0	3	0	0
T61	20565	0	0	0
T62	31133	0	0	0
T63	6516	0	0	0
T64	8439	0	0	0
T100	0	3	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	2	0	0
T104	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538398130	251358770	0	0
T1	1561	1507	0	0
T2	4616	4540	0	0
T3	3651	2227	0	0
T4	12866	2181	0	0
T5	17765	2040	0	0
T6	330	279	0	0
T10	18028	17955	0	0
T11	22732	4158	0	0
T12	2597	2137	0	0
T28	35331	31694	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	498	0	0
T8	41292	0	0	0
T11	22732	1	0	0
T13	45743	0	0	0
T14	0	1	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T17	62926	0	0	0
T18	19012	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T32	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	44513	0	0	0
T55	0	1	0	0
T56	0	3	0	0
T57	0	5	0	0
T58	0	1	0	0
T59	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	485	0	0
T8	41292	0	0	0
T11	22732	1	0	0
T13	45743	0	0	0
T14	0	1	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T17	62926	0	0	0
T18	19012	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T32	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	44513	0	0	0
T55	0	1	0	0
T56	0	3	0	0
T57	0	5	0	0
T58	0	1	0	0
T59	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	473	0	0
T8	41292	0	0	0
T11	22732	1	0	0
T13	45743	0	0	0
T14	0	1	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T17	62926	0	0	0
T18	19012	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T32	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	44513	0	0	0
T55	0	1	0	0
T56	0	3	0	0
T57	0	5	0	0
T58	0	1	0	0
T59	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	463	0	0
T8	41292	0	0	0
T11	22732	1	0	0
T13	45743	0	0	0
T14	0	1	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T17	62926	0	0	0
T18	19012	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T32	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	44513	0	0	0
T55	0	1	0	0
T56	0	3	0	0
T57	0	5	0	0
T58	0	1	0	0
T59	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	445	0	0
T8	41292	0	0	0
T11	22732	1	0	0
T13	45743	5	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T17	62926	0	0	0
T18	19012	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T32	0	1	0	0
T50	44513	0	0	0
T60	0	2	0	0
T61	0	4	0	0
T63	0	1	0	0
T81	0	4	0	0
T100	0	3	0	0
T109	0	1	0	0
T110	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	58080	0	0
T8	41292	0	0	0
T11	22732	114	0	0
T13	45743	691	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T17	62926	0	0	0
T18	19012	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T32	0	425	0	0
T50	44513	0	0	0
T60	0	85	0	0
T61	0	396	0	0
T63	0	201	0	0
T81	0	316	0	0
T100	0	1379	0	0
T109	0	943	0	0
T110	0	735	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	380	0	0
T7	63575	0	0	0
T13	45743	5	0	0
T14	1742	0	0	0
T17	62926	0	0	0
T18	19012	0	0	0
T42	0	1	0	0
T44	89273	0	0	0
T49	78949	0	0	0
T50	44513	0	0	0
T54	42509	0	0	0
T60	0	2	0	0
T61	0	4	0	0
T63	0	1	0	0
T81	0	4	0	0
T100	0	1	0	0
T105	7867	0	0	0
T109	0	1	0	0
T110	0	4	0	0
T112	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	40	0	0
T8	41292	0	0	0
T11	22732	1	0	0
T13	45743	0	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T17	62926	0	0	0
T18	19012	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T32	0	1	0	0
T40	0	1	0	0
T50	44513	0	0	0
T67	0	1	0	0
T74	0	4	0	0
T75	0	1	0	0
T91	0	1	0	0
T100	0	2	0	0
T113	0	1	0	0
T114	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	1276	0	0
T6	17214	177	0	0
T8	41292	316	0	0
T9	0	306	0	0
T11	22732	0	0	0
T13	45743	0	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T17	62926	0	0	0
T18	19012	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T52	0	146	0	0
T53	0	331	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	1036	0	0
T6	17214	147	0	0
T8	41292	256	0	0
T9	0	246	0	0
T11	22732	0	0	0
T13	45743	0	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T17	62926	0	0	0
T18	19012	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T52	0	116	0	0
T53	0	271	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538397058	538328675	0	0
T1	1561	1508	0	0
T2	4616	4541	0	0
T3	3651	3556	0	0
T4	12866	12673	0	0
T5	17765	17617	0	0
T6	96	46	0	0
T10	18028	17956	0	0
T11	22732	22647	0	0
T12	2597	2524	0	0
T28	35331	35232	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	538382136	0	0
T1	1561	1508	0	0
T2	4616	4541	0	0
T3	3651	3556	0	0
T4	12866	12673	0	0
T5	17765	17617	0	0
T6	17214	4563	0	0
T10	18028	17956	0	0
T11	22732	22647	0	0
T12	2597	2524	0	0
T28	35331	35232	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T3 T15 T17 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T3 T15 T17 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T3 T15 T17 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T18 T47 
159        1/1                    state_d = TimeoutSt;
           Tests:       T10 T18 T47 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T10 T18 T47 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T10 T18 T47 
172        1/1                    state_d    = Phase0St;
           Tests:       T18 T47 T107 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T18 T47 T107 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T18 T47 T107 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T18 T47 T107 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T10 T18 T106 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T18 T106 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T10 T18 T106 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T18 T106 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T15 T17 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T3 T15 T17 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T3 T15 T17 
190        1/1                  esc_state_o = Phase0;
           Tests:       T3 T15 T17 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T3 T15 T17 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T3 T15 T17 
194        1/1                    state_d = IdleSt;
           Tests:       T33 T34 T130 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T33 T34 T130 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T33 T34 T130 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T15 T17 
198        1/1                    state_d = Phase1St;
           Tests:       T3 T15 T17 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T15 T17 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T15 T17 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T15 T17 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T3 T15 T17 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T3 T15 T17 
207        1/1                  esc_state_o = Phase1;
           Tests:       T3 T15 T17 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T3 T15 T17 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T3 T15 T17 
211        1/1                    state_d = IdleSt;
           Tests:       T131 T132 T133 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T131 T132 T133 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T131 T132 T133 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T15 T17 
215        1/1                    state_d = Phase2St;
           Tests:       T3 T15 T17 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T15 T17 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T15 T17 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T15 T17 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T3 T15 T17 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T3 T15 T17 
224        1/1                  esc_state_o = Phase2;
           Tests:       T3 T15 T17 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T3 T15 T17 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T3 T15 T17 
229        1/1                    state_d = IdleSt;
           Tests:       T134 T135 T131 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T134 T135 T131 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T134 T135 T131 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T15 T17 
233        1/1                    state_d = Phase3St;
           Tests:       T3 T15 T17 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T15 T17 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T15 T17 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T3 T15 T17 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T3 T15 T17 
241        1/1                  esc_state_o = Phase3;
           Tests:       T3 T15 T17 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T3 T15 T17 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T3 T15 T17 
245        1/1                    state_d = IdleSt;
           Tests:       T136 T124 T137 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T136 T124 T137 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T136 T124 T137 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T15 T17 
249        1/1                    state_d = TerminalSt;
           Tests:       T3 T15 T17 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T15 T17 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T3 T15 T17 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T3 T15 T17 
259        1/1                  esc_state_o = Terminal;
           Tests:       T3 T15 T17 
260        1/1                  if (clr_i) begin
           Tests:       T3 T15 T17 
261        1/1                    state_d = IdleSt;
           Tests:       T18 T95 T57 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T6 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T6 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T6 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T6 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Covered	T3,T10,T15
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T10,T15

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T12
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T15,T17

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T10,T11
1	0	1	Covered	T3,T15,T46
1	1	0	Covered	T11,T13,T17
1	1	1	Covered	T10,T18,T47

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T10,T18,T106
0	1	Covered	T107,T110,T104
1	0	Covered	T18,T47,T43

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T10,T18,T106
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T18,T47,T43

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T18,T47
1	0	Not Covered
1	1	Covered	T107,T110,T104

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T17,T50,T47
1	Covered	T3,T15,T18

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T15,T18
1	Covered	T17,T46,T56

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T15,T17
1	Covered	T50,T47,T95

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T15,T17
1	Covered	T138,T42,T43

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T6,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T3,T15,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T3,T15,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T3,T15,T47

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T3,T15,T18

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T6,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T15,T17
Phase1St	198	Covered	T3,T15,T17
Phase2St	215	Covered	T3,T15,T17
Phase3St	233	Covered	T3,T15,T17
TerminalSt	249	Covered	T3,T15,T17
TimeoutSt	159	Covered	T10,T18,T47

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T6,T8,T9
IdleSt->Phase0St	152	Covered	T3,T15,T17
IdleSt->TimeoutSt	159	Covered	T10,T18,T47
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T33,T40,T34
Phase0St->Phase1St	198	Covered	T3,T15,T17
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T131,T132,T133
Phase1St->Phase2St	215	Covered	T3,T15,T17
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T134,T135,T131
Phase2St->Phase3St	233	Covered	T3,T15,T17
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T136,T124,T137
Phase3St->TerminalSt	249	Covered	T3,T15,T17
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T18,T95,T57
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T10,T18,T106
TimeoutSt->Phase0St	172	Covered	T18,T47,T107

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T15,T17
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T18,T47
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T47,T107
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T10,T18,T106
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T10,T18,T106
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T33,T34,T130
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T15,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T17,T18,T50
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T131,T132,T133
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T15,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T17,T18,T50
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T134,T135,T131
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T15,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T17,T18,T50
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T136,T124,T137
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T15,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T17,T18,T50
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T18,T95,T57
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T15,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	538552980	279	0	0
CheckAccumTrig0_A	538552980	460	0	0
CheckAccumTrig1_A	538552980	26	0	0
CheckClr_A	538552980	205	0	0
CheckEn_A	538398130	219699249	0	0
CheckPhase0_A	538552980	510	0	0
CheckPhase1_A	538552980	500	0	0
CheckPhase2_A	538552980	491	0	0
CheckPhase3_A	538552980	482	0	0
CheckTimeout0_A	538552980	465	0	0
CheckTimeoutSt1_A	538552980	47703	0	0
CheckTimeoutSt2_A	538552980	401	0	0
CheckTimeoutStTrig_A	538552980	36	0	0
ErrorStAllEscAsserted_A	538552980	1303	0	0
ErrorStIsTerminal_A	538552980	1063	0	0
EscStateOut_A	538397058	538328675	0	0
u_state_regs_A	538552980	538382136	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	279	0	0
T6	17214	27	0	0
T8	41292	72	0	0
T9	0	76	0	0
T11	22732	0	0	0
T13	45743	0	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T17	62926	0	0	0
T18	19012	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T52	0	31	0	0
T53	0	73	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	460	0	0
T3	3651	1	0	0
T4	12866	0	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	0	0	0
T11	22732	0	0	0
T12	2597	0	0	0
T15	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T28	35331	0	0	0
T29	46058	0	0	0
T46	0	1	0	0
T50	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T95	0	2	0	0
T96	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	26	0	0
T7	63575	0	0	0
T9	39079	0	0	0
T14	1742	0	0	0
T18	19012	1	0	0
T32	108382	0	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	89273	0	0	0
T47	0	1	0	0
T49	78949	0	0	0
T50	44513	0	0	0
T54	42509	0	0	0
T104	0	1	0	0
T105	7867	0	0	0
T117	0	1	0	0
T135	0	1	0	0
T139	0	2	0	0
T140	0	1	0	0
T141	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	205	0	0
T7	63575	0	0	0
T9	39079	0	0	0
T14	1742	0	0	0
T18	19012	1	0	0
T32	108382	0	0	0
T33	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	89273	0	0	0
T49	78949	0	0	0
T50	44513	0	0	0
T54	42509	0	0	0
T57	0	1	0	0
T67	0	1	0	0
T95	0	1	0	0
T99	0	3	0	0
T101	0	1	0	0
T103	0	3	0	0
T105	7867	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538398130	219699249	0	0
T1	1561	622	0	0
T2	4616	4540	0	0
T3	3651	2240	0	0
T4	12866	2189	0	0
T5	17765	2056	0	0
T6	330	279	0	0
T10	18028	767	0	0
T11	22732	15647	0	0
T12	2597	2142	0	0
T28	35331	35231	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	510	0	0
T3	3651	1	0	0
T4	12866	0	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	0	0	0
T11	22732	0	0	0
T12	2597	0	0	0
T15	0	1	0	0
T17	0	1	0	0
T18	0	2	0	0
T28	35331	0	0	0
T29	46058	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T56	0	1	0	0
T95	0	2	0	0
T96	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	500	0	0
T3	3651	1	0	0
T4	12866	0	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	0	0	0
T11	22732	0	0	0
T12	2597	0	0	0
T15	0	1	0	0
T17	0	1	0	0
T18	0	2	0	0
T28	35331	0	0	0
T29	46058	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T56	0	1	0	0
T95	0	2	0	0
T96	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	491	0	0
T3	3651	1	0	0
T4	12866	0	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	0	0	0
T11	22732	0	0	0
T12	2597	0	0	0
T15	0	1	0	0
T17	0	1	0	0
T18	0	2	0	0
T28	35331	0	0	0
T29	46058	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T56	0	1	0	0
T95	0	2	0	0
T96	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	482	0	0
T3	3651	1	0	0
T4	12866	0	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	0	0	0
T11	22732	0	0	0
T12	2597	0	0	0
T15	0	1	0	0
T17	0	1	0	0
T18	0	2	0	0
T28	35331	0	0	0
T29	46058	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T56	0	1	0	0
T95	0	2	0	0
T96	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	465	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	8	0	0
T11	22732	0	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T18	0	2	0	0
T28	35331	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T42	0	1	0	0
T47	0	1	0	0
T81	0	5	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	4	0	0
T110	0	1	0	0
T111	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	47703	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	544	0	0
T11	22732	0	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T18	0	13	0	0
T28	35331	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T42	0	144	0	0
T81	0	375	0	0
T106	0	48	0	0
T107	0	208	0	0
T108	0	758	0	0
T110	0	78	0	0
T111	0	123	0	0
T113	0	443	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	401	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	8	0	0
T11	22732	0	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T18	0	1	0	0
T28	35331	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T81	0	5	0	0
T106	0	1	0	0
T108	0	4	0	0
T111	0	2	0	0
T113	0	5	0	0
T114	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	36	0	0
T19	535329	0	0	0
T25	24817	0	0	0
T26	22706	0	0	0
T37	16522	0	0	0
T40	0	1	0	0
T58	94602	0	0	0
T59	4918	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T89	0	1	0	0
T99	11463	0	0	0
T104	0	1	0	0
T107	51573	1	0	0
T110	0	1	0	0
T115	0	1	0	0
T116	0	1	0	0
T142	0	1	0	0
T143	97086	0	0	0
T144	6654	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	1303	0	0
T6	17214	140	0	0
T8	41292	317	0	0
T9	0	362	0	0
T11	22732	0	0	0
T13	45743	0	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T17	62926	0	0	0
T18	19012	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T52	0	180	0	0
T53	0	304	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	1063	0	0
T6	17214	110	0	0
T8	41292	257	0	0
T9	0	302	0	0
T11	22732	0	0	0
T13	45743	0	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T17	62926	0	0	0
T18	19012	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T52	0	150	0	0
T53	0	244	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538397058	538328675	0	0
T1	1561	1508	0	0
T2	4616	4541	0	0
T3	3651	3556	0	0
T4	12866	12673	0	0
T5	17765	17617	0	0
T6	96	46	0	0
T10	18028	17956	0	0
T11	22732	22647	0	0
T12	2597	2524	0	0
T28	35331	35232	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	538382136	0	0
T1	1561	1508	0	0
T2	4616	4541	0	0
T3	3651	3556	0	0
T4	12866	12673	0	0
T5	17765	17617	0	0
T6	17214	4563	0	0
T10	18028	17956	0	0
T11	22732	22647	0	0
T12	2597	2524	0	0
T28	35331	35232	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T16 T17 T18 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T16 T17 T18 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T16 T17 T18 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T50 T61 
159        1/1                    state_d = TimeoutSt;
           Tests:       T10 T50 T61 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T10 T50 T61 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T10 T50 T61 
172        1/1                    state_d    = Phase0St;
           Tests:       T47 T107 T99 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T47 T107 T99 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T47 T107 T99 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T47 T107 T99 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T10 T50 T61 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T50 T61 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T10 T50 T61 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T50 T61 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T16 T17 T18 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T16 T17 T18 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T16 T17 T18 
190        1/1                  esc_state_o = Phase0;
           Tests:       T16 T17 T18 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T16 T17 T18 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T16 T17 T18 
194        1/1                    state_d = IdleSt;
           Tests:       T145 T146 T122 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T145 T146 T122 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T145 T146 T122 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T16 T17 T18 
198        1/1                    state_d = Phase1St;
           Tests:       T16 T17 T18 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T16 T17 T18 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T16 T17 T18 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T16 T17 T18 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T16 T17 T18 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T16 T17 T18 
207        1/1                  esc_state_o = Phase1;
           Tests:       T16 T17 T18 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T16 T17 T18 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T16 T17 T18 
211        1/1                    state_d = IdleSt;
           Tests:       T56 T35 T147 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T56 T35 T147 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T56 T35 T147 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T16 T17 T18 
215        1/1                    state_d = Phase2St;
           Tests:       T16 T17 T18 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T16 T17 T18 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T16 T17 T18 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T16 T17 T18 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T16 T17 T18 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T16 T17 T18 
224        1/1                  esc_state_o = Phase2;
           Tests:       T16 T17 T18 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T16 T17 T18 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T16 T17 T18 
229        1/1                    state_d = IdleSt;
           Tests:       T35 T148 T149 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T148 T149 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T35 T148 T149 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T16 T17 T18 
233        1/1                    state_d = Phase3St;
           Tests:       T16 T17 T18 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T16 T17 T18 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T16 T17 T18 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T16 T17 T18 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T16 T17 T18 
241        1/1                  esc_state_o = Phase3;
           Tests:       T16 T17 T18 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T16 T17 T18 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T16 T17 T18 
245        1/1                    state_d = IdleSt;
           Tests:       T150 T124 T145 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T150 T124 T145 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T150 T124 T145 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T16 T17 T18 
249        1/1                    state_d = TerminalSt;
           Tests:       T16 T17 T18 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T16 T17 T18 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T16 T17 T18 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T16 T17 T18 
259        1/1                  esc_state_o = Terminal;
           Tests:       T16 T17 T18 
260        1/1                  if (clr_i) begin
           Tests:       T16 T17 T18 
261        1/1                    state_d = IdleSt;
           Tests:       T17 T18 T105 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T6 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T6 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T6 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T6 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Covered	T10,T16,T17
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T16,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T16,T17

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T12
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T16,T17,T18

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T10,T11
1	0	1	Covered	T18,T105,T31
1	1	0	Covered	T11,T16,T13
1	1	1	Covered	T10,T50,T61

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T10,T50,T61
0	1	Covered	T47,T107,T99
1	0	Covered	T42,T103,T40

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T10,T50,T61
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T42,T103,T40

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T50,T61
1	0	Not Covered
1	1	Covered	T47,T107,T99

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T18,T105,T46
1	Covered	T16,T17,T50

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T46,T107,T151

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T18,T105,T96

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T18,T105,T95

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T6,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T18,T105,T47

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T16,T17,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T16,T17,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T18,T105,T46

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T6,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T16,T17,T18
Phase1St	198	Covered	T16,T17,T18
Phase2St	215	Covered	T16,T17,T18
Phase3St	233	Covered	T16,T17,T18
TerminalSt	249	Covered	T16,T17,T18
TimeoutSt	159	Covered	T10,T50,T61

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T6,T8,T9
IdleSt->Phase0St	152	Covered	T16,T17,T18
IdleSt->TimeoutSt	159	Covered	T10,T50,T61
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T51,T40,T34
Phase0St->Phase1St	198	Covered	T16,T17,T18
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T56,T51,T40
Phase1St->Phase2St	215	Covered	T16,T17,T18
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T35,T148,T149
Phase2St->Phase3St	233	Covered	T16,T17,T18
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T150,T124,T145
Phase3St->TerminalSt	249	Covered	T16,T17,T18
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T17,T18,T105
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T10,T50,T61
TimeoutSt->Phase0St	172	Covered	T47,T107,T99

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T18
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T50,T61
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T47,T107,T99
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T10,T50,T61
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T10,T50,T61
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T145,T146,T122
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T16,T17,T18
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T16,T17,T18
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T56,T35,T147
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T16,T17,T18
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T16,T17,T18
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T35,T148,T149
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T16,T17,T18
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T16,T17,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T150,T124,T145
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T16,T17,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T16,T18,T50
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T17,T18,T105
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T16,T17,T18
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	538552980	213	0	0
CheckAccumTrig0_A	538552980	443	0	0
CheckAccumTrig1_A	538552980	22	0	0
CheckClr_A	538552980	194	0	0
CheckEn_A	538398130	248518880	0	0
CheckPhase0_A	538552980	494	0	0
CheckPhase1_A	538552980	483	0	0
CheckPhase2_A	538552980	475	0	0
CheckPhase3_A	538552980	465	0	0
CheckTimeout0_A	538552980	518	0	0
CheckTimeoutSt1_A	538552980	62419	0	0
CheckTimeoutSt2_A	538552980	453	0	0
CheckTimeoutStTrig_A	538552980	40	0	0
ErrorStAllEscAsserted_A	538552980	1268	0	0
ErrorStIsTerminal_A	538552980	1028	0	0
EscStateOut_A	538397058	538328675	0	0
u_state_regs_A	538552980	538382136	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	213	0	0
T6	17214	12	0	0
T8	41292	62	0	0
T9	0	52	0	0
T11	22732	0	0	0
T13	45743	0	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T17	62926	0	0	0
T18	19012	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T52	0	46	0	0
T53	0	41	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	443	0	0
T7	63575	0	0	0
T13	45743	0	0	0
T15	1110	0	0	0
T16	43811	1	0	0
T17	62926	1	0	0
T18	19012	2	0	0
T30	57586	0	0	0
T31	0	1	0	0
T44	89273	0	0	0
T46	0	1	0	0
T50	44513	1	0	0
T56	0	3	0	0
T95	0	1	0	0
T96	0	1	0	0
T105	7867	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	22	0	0
T40	0	1	0	0
T42	862100	1	0	0
T69	0	1	0	0
T72	0	1	0	0
T75	0	2	0	0
T103	0	2	0	0
T111	35977	0	0	0
T113	29943	0	0	0
T135	0	1	0	0
T145	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	63716	0	0	0
T155	120011	0	0	0
T156	2962	0	0	0
T157	7961	0	0	0
T158	5595	0	0	0
T159	68955	0	0	0
T160	42312	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	194	0	0
T7	63575	0	0	0
T9	39079	0	0	0
T14	1742	0	0	0
T17	62926	1	0	0
T18	19012	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	89273	0	0	0
T49	78949	0	0	0
T50	44513	0	0	0
T54	42509	0	0	0
T56	0	2	0	0
T99	0	1	0	0
T103	0	1	0	0
T105	7867	2	0	0
T107	0	1	0	0
T151	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538398130	248518880	0	0
T1	1561	626	0	0
T2	4616	4540	0	0
T3	3651	2256	0	0
T4	12866	2202	0	0
T5	17765	2074	0	0
T6	330	279	0	0
T10	18028	771	0	0
T11	22732	19074	0	0
T12	2597	2164	0	0
T28	35331	35231	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	494	0	0
T7	63575	0	0	0
T13	45743	0	0	0
T15	1110	0	0	0
T16	43811	1	0	0
T17	62926	1	0	0
T18	19012	2	0	0
T30	57586	0	0	0
T31	0	1	0	0
T44	89273	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	44513	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T105	7867	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	483	0	0
T7	63575	0	0	0
T13	45743	0	0	0
T15	1110	0	0	0
T16	43811	1	0	0
T17	62926	1	0	0
T18	19012	2	0	0
T30	57586	0	0	0
T31	0	1	0	0
T44	89273	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	44513	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T105	7867	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	475	0	0
T7	63575	0	0	0
T13	45743	0	0	0
T15	1110	0	0	0
T16	43811	1	0	0
T17	62926	1	0	0
T18	19012	2	0	0
T30	57586	0	0	0
T31	0	1	0	0
T44	89273	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	44513	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T105	7867	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	465	0	0
T7	63575	0	0	0
T13	45743	0	0	0
T15	1110	0	0	0
T16	43811	1	0	0
T17	62926	1	0	0
T18	19012	2	0	0
T30	57586	0	0	0
T31	0	1	0	0
T44	89273	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	44513	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T105	7867	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	518	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	5	0	0
T11	22732	0	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T27	0	9	0	0
T28	35331	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T47	0	1	0	0
T50	0	1	0	0
T61	0	4	0	0
T63	0	1	0	0
T81	0	5	0	0
T99	0	1	0	0
T100	0	1	0	0
T107	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	62419	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	384	0	0
T11	22732	0	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T27	0	2177	0	0
T28	35331	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T47	0	927	0	0
T50	0	183	0	0
T61	0	327	0	0
T63	0	145	0	0
T81	0	398	0	0
T99	0	164	0	0
T100	0	270	0	0
T107	0	774	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	453	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	5	0	0
T11	22732	0	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T27	0	9	0	0
T28	35331	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T42	0	1	0	0
T50	0	1	0	0
T61	0	4	0	0
T63	0	1	0	0
T81	0	5	0	0
T100	0	1	0	0
T110	0	1	0	0
T112	0	5	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	40	0	0
T22	63717	0	0	0
T31	91617	0	0	0
T46	25175	0	0	0
T47	107886	1	0	0
T52	16729	0	0	0
T55	1012	0	0	0
T75	0	1	0	0
T94	0	1	0	0
T95	32705	0	0	0
T96	42770	0	0	0
T99	0	1	0	0
T107	0	2	0	0
T116	0	2	0	0
T119	20216	0	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	24239	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	1268	0	0
T6	17214	118	0	0
T8	41292	299	0	0
T9	0	313	0	0
T11	22732	0	0	0
T13	45743	0	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T17	62926	0	0	0
T18	19012	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T52	0	196	0	0
T53	0	342	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	1028	0	0
T6	17214	88	0	0
T8	41292	239	0	0
T9	0	253	0	0
T11	22732	0	0	0
T13	45743	0	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T17	62926	0	0	0
T18	19012	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T52	0	166	0	0
T53	0	282	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538397058	538328675	0	0
T1	1561	1508	0	0
T2	4616	4541	0	0
T3	3651	3556	0	0
T4	12866	12673	0	0
T5	17765	17617	0	0
T6	96	46	0	0
T10	18028	17956	0	0
T11	22732	22647	0	0
T12	2597	2524	0	0
T28	35331	35232	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	538382136	0	0
T1	1561	1508	0	0
T2	4616	4541	0	0
T3	3651	3556	0	0
T4	12866	12673	0	0
T5	17765	17617	0	0
T6	17214	4563	0	0
T10	18028	17956	0	0
T11	22732	22647	0	0
T12	2597	2524	0	0
T28	35331	35232	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T2 T12 T28 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T2 T12 T28 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T2 T12 T28 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T10 T11 
159        1/1                    state_d = TimeoutSt;
           Tests:       T2 T10 T11 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T2 T10 T11 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T2 T10 T11 
172        1/1                    state_d    = Phase0St;
           Tests:       T46 T107 T48 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T46 T107 T48 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T46 T107 T48 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T46 T107 T48 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T2 T10 T11 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T10 T11 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T2 T10 T11 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T10 T11 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T12 T28 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T2 T12 T28 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T2 T12 T28 
190        1/1                  esc_state_o = Phase0;
           Tests:       T2 T12 T28 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T2 T12 T28 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T2 T12 T28 
194        1/1                    state_d = IdleSt;
           Tests:       T35 T166 T122 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T166 T122 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T35 T166 T122 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T12 T28 
198        1/1                    state_d = Phase1St;
           Tests:       T2 T12 T28 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T12 T28 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T12 T28 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T12 T28 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T2 T12 T28 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T2 T12 T28 
207        1/1                  esc_state_o = Phase1;
           Tests:       T2 T12 T28 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T2 T12 T28 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T2 T12 T28 
211        1/1                    state_d = IdleSt;
           Tests:       T36 T37 T38 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T36 T37 T38 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T36 T37 T38 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T12 T28 
215        1/1                    state_d = Phase2St;
           Tests:       T2 T12 T28 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T12 T28 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T12 T28 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T12 T28 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T2 T12 T28 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T2 T12 T28 
224        1/1                  esc_state_o = Phase2;
           Tests:       T2 T12 T28 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T2 T12 T28 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T2 T12 T28 
229        1/1                    state_d = IdleSt;
           Tests:       T2 T39 T40 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T39 T40 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T2 T39 T40 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T12 T28 
233        1/1                    state_d = Phase3St;
           Tests:       T12 T28 T29 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T28 T29 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T12 T28 T29 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T12 T28 T29 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T12 T28 T29 
241        1/1                  esc_state_o = Phase3;
           Tests:       T12 T28 T29 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T12 T28 T29 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T12 T28 T29 
245        1/1                    state_d = IdleSt;
           Tests:       T41 T42 T43 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T41 T42 T43 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T41 T42 T43 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T12 T28 T29 
249        1/1                    state_d = TerminalSt;
           Tests:       T12 T28 T29 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T28 T29 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T12 T28 T29 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T12 T28 T29 
259        1/1                  esc_state_o = Terminal;
           Tests:       T12 T28 T29 
260        1/1                  if (clr_i) begin
           Tests:       T12 T28 T29 
261        1/1                    state_d = IdleSt;
           Tests:       T29 T18 T44 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T6 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T6 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T6 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T6 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Covered	T2,T12,T10
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T28
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T12,T10

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T12
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T45
1	1	1	Covered	T2,T12,T28

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T10,T11
1	0	1	Covered	T12,T105,T165
1	1	0	Covered	T17,T18,T50
1	1	1	Covered	T2,T10,T11

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T11
0	1	Covered	T46,T107,T110
1	0	Covered	T48,T65,T66

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T10,T11
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T48,T65,T66

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T11
1	0	Not Covered
1	1	Covered	T46,T107,T110

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T28,T29
1	Covered	T12,T36,T95

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T12,T28
1	Covered	T16,T17,T49

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T12,T28
1	Covered	T50,T44,T46

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12,T16,T17
1	Covered	T28,T29,T18

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T6,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T2,T12,T28

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T12,T28,T29

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T12,T29,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
1	0	Covered	T12,T28,T29

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T6,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T12,T28
Phase1St	198	Covered	T2,T12,T28
Phase2St	215	Covered	T2,T12,T28
Phase3St	233	Covered	T12,T28,T29
TerminalSt	249	Covered	T12,T28,T29
TimeoutSt	159	Covered	T2,T10,T11

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T6,T8,T9
IdleSt->Phase0St	152	Covered	T2,T12,T28
IdleSt->TimeoutSt	159	Covered	T2,T10,T11
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T51,T40,T34
Phase0St->Phase1St	198	Covered	T2,T12,T28
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T36,T37,T43
Phase1St->Phase2St	215	Covered	T2,T12,T28
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T2,T39,T40
Phase2St->Phase3St	233	Covered	T12,T28,T29
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T41,T42,T43
Phase3St->TerminalSt	249	Covered	T12,T28,T29
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T29,T18,T44
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T10,T11
TimeoutSt->Phase0St	172	Covered	T46,T107,T48

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T28
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T11
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T46,T107,T48
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T11
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T11
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T35,T166,T122
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T12,T28
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T28,T29
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T36,T37,T38
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T12,T28
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T28,T29
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T39,T40
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T12,T28,T29
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T28,T29
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T41,T42,T43
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T12,T28,T29
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T28,T29,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T29,T18,T44
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T12,T28,T29
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	538552980	236	0	0
CheckAccumTrig0_A	538552980	797	0	0
CheckAccumTrig1_A	538552980	52	0	0
CheckClr_A	538552980	390	0	0
CheckEn_A	538398130	175212524	0	0
CheckPhase0_A	538552980	884	0	0
CheckPhase1_A	538552980	860	0	0
CheckPhase2_A	538552980	842	0	0
CheckPhase3_A	538552980	826	0	0
CheckTimeout0_A	538552980	552	0	0
CheckTimeoutSt1_A	538552980	70460	0	0
CheckTimeoutSt2_A	538552980	438	0	0
CheckTimeoutStTrig_A	538552980	60	0	0
ErrorStAllEscAsserted_A	538552980	1322	0	0
ErrorStIsTerminal_A	538552980	1082	0	0
EscStateOut_A	538397058	538328675	0	0
u_state_regs_A	538552980	538382136	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	236	0	0
T6	17214	20	0	0
T8	41292	64	0	0
T9	0	54	0	0
T11	22732	0	0	0
T13	45743	0	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T17	62926	0	0	0
T18	19012	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T52	0	30	0	0
T53	0	68	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	797	0	0
T2	4616	1	0	0
T3	3651	0	0	0
T4	12866	0	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	0	0	0
T11	22732	0	0	0
T12	2597	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T28	35331	1	0	0
T29	0	3	0	0
T44	0	3	0	0
T50	0	1	0	0
T54	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	52	0	0
T20	375082	0	0	0
T39	18850	0	0	0
T48	78276	1	0	0
T51	0	1	0	0
T60	15670	0	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T81	25451	0	0	0
T82	53283	0	0	0
T83	234656	0	0	0
T84	36429	0	0	0
T85	4697	0	0	0
T86	578135	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	390	0	0
T2	4616	1	0	0
T3	3651	0	0	0
T4	12866	0	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	0	0	0
T11	22732	0	0	0
T12	2597	0	0	0
T18	0	1	0	0
T28	35331	0	0	0
T29	0	2	0	0
T36	0	2	0	0
T44	0	2	0	0
T46	0	4	0	0
T56	0	1	0	0
T96	0	2	0	0
T97	0	4	0	0
T98	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538398130	175212524	0	0
T1	1561	1507	0	0
T2	4616	582	0	0
T3	3651	2221	0	0
T4	12866	2163	0	0
T5	17765	2033	0	0
T6	330	279	0	0
T10	18028	759	0	0
T11	22732	4154	0	0
T12	2597	2128	0	0
T28	35331	5531	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	884	0	0
T2	4616	1	0	0
T3	3651	0	0	0
T4	12866	0	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	0	0	0
T11	22732	0	0	0
T12	2597	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T28	35331	1	0	0
T29	0	3	0	0
T44	0	3	0	0
T50	0	1	0	0
T54	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	860	0	0
T2	4616	1	0	0
T3	3651	0	0	0
T4	12866	0	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	0	0	0
T11	22732	0	0	0
T12	2597	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T28	35331	1	0	0
T29	0	3	0	0
T44	0	3	0	0
T50	0	1	0	0
T54	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	842	0	0
T4	12866	0	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	0	0	0
T11	22732	0	0	0
T12	2597	1	0	0
T16	43811	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T28	35331	1	0	0
T29	46058	3	0	0
T44	0	3	0	0
T49	0	1	0	0
T50	0	1	0	0
T54	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	826	0	0
T4	12866	0	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	0	0	0
T11	22732	0	0	0
T12	2597	1	0	0
T16	43811	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T28	35331	1	0	0
T29	46058	3	0	0
T44	0	3	0	0
T49	0	1	0	0
T50	0	1	0	0
T54	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	552	0	0
T2	4616	1	0	0
T3	3651	0	0	0
T4	12866	0	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	6	0	0
T11	22732	5	0	0
T12	2597	0	0	0
T13	0	5	0	0
T18	0	2	0	0
T28	35331	0	0	0
T44	0	2	0	0
T46	0	6	0	0
T61	0	3	0	0
T62	0	1	0	0
T63	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	70460	0	0
T2	4616	41	0	0
T3	3651	0	0	0
T4	12866	0	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	451	0	0
T11	22732	500	0	0
T12	2597	0	0	0
T13	0	641	0	0
T18	0	510	0	0
T28	35331	0	0	0
T44	0	220	0	0
T46	0	765	0	0
T61	0	291	0	0
T62	0	127	0	0
T63	0	431	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	438	0	0
T2	4616	1	0	0
T3	3651	0	0	0
T4	12866	0	0	0
T5	17765	0	0	0
T6	17214	0	0	0
T8	41292	0	0	0
T10	18028	6	0	0
T11	22732	5	0	0
T12	2597	0	0	0
T13	0	5	0	0
T18	0	2	0	0
T28	35331	0	0	0
T44	0	2	0	0
T46	0	3	0	0
T61	0	3	0	0
T62	0	1	0	0
T63	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	60	0	0
T23	105653	0	0	0
T31	91617	0	0	0
T35	0	2	0	0
T46	25175	3	0	0
T53	41980	0	0	0
T56	50548	0	0	0
T67	0	1	0	0
T91	0	1	0	0
T94	0	1	0	0
T95	32705	0	0	0
T96	42770	0	0	0
T97	24485	0	0	0
T107	0	1	0	0
T110	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0
T118	0	2	0	0
T119	20216	0	0	0
T120	11625	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	1322	0	0
T6	17214	163	0	0
T8	41292	324	0	0
T9	0	313	0	0
T11	22732	0	0	0
T13	45743	0	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T17	62926	0	0	0
T18	19012	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T52	0	165	0	0
T53	0	357	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	1082	0	0
T6	17214	133	0	0
T8	41292	264	0	0
T9	0	253	0	0
T11	22732	0	0	0
T13	45743	0	0	0
T15	1110	0	0	0
T16	43811	0	0	0
T17	62926	0	0	0
T18	19012	0	0	0
T29	46058	0	0	0
T30	57586	0	0	0
T52	0	135	0	0
T53	0	297	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538397058	538328675	0	0
T1	1561	1508	0	0
T2	4616	4541	0	0
T3	3651	3556	0	0
T4	12866	12673	0	0
T5	17765	17617	0	0
T6	96	46	0	0
T10	18028	17956	0	0
T11	22732	22647	0	0
T12	2597	2524	0	0
T28	35331	35232	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	538552980	538382136	0	0
T1	1561	1508	0	0
T2	4616	4541	0	0
T3	3651	3556	0	0
T4	12866	12673	0	0
T5	17765	17617	0	0
T6	17214	4563	0	0
T10	18028	17956	0	0
T11	22732	22647	0	0
T12	2597	2524	0	0
T28	35331	35232	0	0