| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.24 | 99.99 | 98.69 | 97.06 | 100.00 | 100.00 | 99.38 | 99.56 |
| T779 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3754787157 | Oct 03 06:24:22 AM UTC 24 | Oct 03 06:25:28 AM UTC 24 | 1025646848 ps | ||
| T780 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3589994138 | Oct 03 06:25:18 AM UTC 24 | Oct 03 06:25:30 AM UTC 24 | 84913487 ps | ||
| T781 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.370336522 | Oct 03 06:25:31 AM UTC 24 | Oct 03 06:25:35 AM UTC 24 | 12340308 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3693294581 | Oct 03 06:25:29 AM UTC 24 | Oct 03 06:25:39 AM UTC 24 | 73446004 ps | ||
| T782 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.525561849 | Oct 03 06:25:36 AM UTC 24 | Oct 03 06:25:50 AM UTC 24 | 217961616 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.893935137 | Oct 03 06:20:21 AM UTC 24 | Oct 03 06:25:53 AM UTC 24 | 4718149427 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2511281084 | Oct 03 06:23:40 AM UTC 24 | Oct 03 06:25:54 AM UTC 24 | 5377212855 ps | ||
| T783 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.722571133 | Oct 03 06:25:18 AM UTC 24 | Oct 03 06:25:55 AM UTC 24 | 3286636629 ps | ||
| T784 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.2308687908 | Oct 03 06:25:57 AM UTC 24 | Oct 03 06:26:06 AM UTC 24 | 135709241 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.1886907849 | Oct 03 06:25:29 AM UTC 24 | Oct 03 06:26:06 AM UTC 24 | 311383948 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2313623298 | Oct 03 06:20:49 AM UTC 24 | Oct 03 06:26:07 AM UTC 24 | 8906148489 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.4099194252 | Oct 03 06:17:22 AM UTC 24 | Oct 03 06:26:09 AM UTC 24 | 79619496420 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.340888195 | Oct 03 06:26:07 AM UTC 24 | Oct 03 06:26:11 AM UTC 24 | 12275196 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.789334671 | Oct 03 06:25:50 AM UTC 24 | Oct 03 06:26:12 AM UTC 24 | 362999431 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2665355356 | Oct 03 06:24:53 AM UTC 24 | Oct 03 06:26:13 AM UTC 24 | 2986122078 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.713989995 | Oct 03 06:25:40 AM UTC 24 | Oct 03 06:26:14 AM UTC 24 | 607145172 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.410403928 | Oct 03 06:26:09 AM UTC 24 | Oct 03 06:26:16 AM UTC 24 | 118406766 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.226423647 | Oct 03 06:26:14 AM UTC 24 | Oct 03 06:26:17 AM UTC 24 | 10807633 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.924734030 | Oct 03 06:26:15 AM UTC 24 | Oct 03 06:26:18 AM UTC 24 | 26714243 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.1905724278 | Oct 03 06:26:15 AM UTC 24 | Oct 03 06:26:18 AM UTC 24 | 8765922 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.3362665873 | Oct 03 06:26:17 AM UTC 24 | Oct 03 06:26:20 AM UTC 24 | 9723191 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1135886527 | Oct 03 06:24:28 AM UTC 24 | Oct 03 06:26:20 AM UTC 24 | 975550549 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.973994935 | Oct 03 06:26:19 AM UTC 24 | Oct 03 06:26:21 AM UTC 24 | 6833250 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3234633547 | Oct 03 06:26:11 AM UTC 24 | Oct 03 06:26:21 AM UTC 24 | 79485265 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.4230359681 | Oct 03 06:26:19 AM UTC 24 | Oct 03 06:26:22 AM UTC 24 | 6180203 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2627834821 | Oct 03 06:26:07 AM UTC 24 | Oct 03 06:26:23 AM UTC 24 | 200358970 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.388212264 | Oct 03 06:26:22 AM UTC 24 | Oct 03 06:26:25 AM UTC 24 | 12504483 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.1336831465 | Oct 03 06:26:22 AM UTC 24 | Oct 03 06:26:26 AM UTC 24 | 26272804 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.1849369315 | Oct 03 06:26:24 AM UTC 24 | Oct 03 06:26:26 AM UTC 24 | 14775573 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.2024681561 | Oct 03 06:26:23 AM UTC 24 | Oct 03 06:26:27 AM UTC 24 | 7116867 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.4105560816 | Oct 03 06:26:23 AM UTC 24 | Oct 03 06:26:27 AM UTC 24 | 26171510 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.1125403725 | Oct 03 06:26:24 AM UTC 24 | Oct 03 06:26:27 AM UTC 24 | 16185447 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.2823171172 | Oct 03 06:26:24 AM UTC 24 | Oct 03 06:26:27 AM UTC 24 | 15313985 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.1293907849 | Oct 03 06:26:25 AM UTC 24 | Oct 03 06:26:28 AM UTC 24 | 18312069 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.513652725 | Oct 03 06:26:26 AM UTC 24 | Oct 03 06:26:30 AM UTC 24 | 17536105 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3935202094 | Oct 03 06:17:21 AM UTC 24 | Oct 03 06:26:30 AM UTC 24 | 7405197796 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.293134479 | Oct 03 06:26:28 AM UTC 24 | Oct 03 06:26:31 AM UTC 24 | 9744829 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.718706588 | Oct 03 06:26:28 AM UTC 24 | Oct 03 06:26:31 AM UTC 24 | 9920297 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.4232404331 | Oct 03 06:26:28 AM UTC 24 | Oct 03 06:26:32 AM UTC 24 | 6099253 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.3601163536 | Oct 03 06:26:28 AM UTC 24 | Oct 03 06:26:32 AM UTC 24 | 19552886 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.1538493645 | Oct 03 06:26:28 AM UTC 24 | Oct 03 06:26:32 AM UTC 24 | 9741700 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.3795696415 | Oct 03 06:26:28 AM UTC 24 | Oct 03 06:26:33 AM UTC 24 | 28821897 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.1159388885 | Oct 03 06:26:30 AM UTC 24 | Oct 03 06:26:33 AM UTC 24 | 7516686 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2520290542 | Oct 03 06:26:10 AM UTC 24 | Oct 03 06:26:33 AM UTC 24 | 1024727457 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.3152665155 | Oct 03 06:26:32 AM UTC 24 | Oct 03 06:26:35 AM UTC 24 | 9887111 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.3802861922 | Oct 03 06:26:32 AM UTC 24 | Oct 03 06:26:35 AM UTC 24 | 58317644 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.3992961638 | Oct 03 06:26:32 AM UTC 24 | Oct 03 06:26:35 AM UTC 24 | 15019963 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.2830394432 | Oct 03 06:26:33 AM UTC 24 | Oct 03 06:26:36 AM UTC 24 | 11495186 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.3755878240 | Oct 03 06:26:33 AM UTC 24 | Oct 03 06:26:36 AM UTC 24 | 7261789 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.1185107502 | Oct 03 06:26:33 AM UTC 24 | Oct 03 06:26:37 AM UTC 24 | 8331602 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.3396776465 | Oct 03 06:26:34 AM UTC 24 | Oct 03 06:26:37 AM UTC 24 | 18375757 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.4130880351 | Oct 03 06:26:34 AM UTC 24 | Oct 03 06:26:38 AM UTC 24 | 17058275 ps | ||
| T220 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1691688679 | Oct 03 06:25:02 AM UTC 24 | Oct 03 06:26:44 AM UTC 24 | 2648888268 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3062809239 | Oct 03 06:14:16 AM UTC 24 | Oct 03 06:26:50 AM UTC 24 | 8905789510 ps | ||
| T219 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.529815540 | Oct 03 06:21:28 AM UTC 24 | Oct 03 06:27:26 AM UTC 24 | 16342190036 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.831406052 | Oct 03 06:18:31 AM UTC 24 | Oct 03 06:28:37 AM UTC 24 | 26415973623 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.4040446634 | Oct 03 06:15:38 AM UTC 24 | Oct 03 06:29:07 AM UTC 24 | 8606095164 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3157678775 | Oct 03 06:25:29 AM UTC 24 | Oct 03 06:29:17 AM UTC 24 | 20043205775 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3090658331 | Oct 03 06:25:55 AM UTC 24 | Oct 03 06:29:41 AM UTC 24 | 6471985081 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3780173774 | Oct 03 06:24:09 AM UTC 24 | Oct 03 06:30:09 AM UTC 24 | 5319162729 ps | ||
| T393 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3574319973 | Oct 03 06:18:01 AM UTC 24 | Oct 03 06:30:14 AM UTC 24 | 157068185467 ps | ||
| T221 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3644911295 | Oct 03 06:22:13 AM UTC 24 | Oct 03 06:30:56 AM UTC 24 | 100651910260 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2818030818 | Oct 03 06:20:17 AM UTC 24 | Oct 03 06:30:58 AM UTC 24 | 15057442446 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4081569992 | Oct 03 06:25:26 AM UTC 24 | Oct 03 06:32:06 AM UTC 24 | 8893872602 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.459013713 | Oct 03 06:23:01 AM UTC 24 | Oct 03 06:32:57 AM UTC 24 | 100570734500 ps | ||
| T394 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2228650102 | Oct 03 06:25:00 AM UTC 24 | Oct 03 06:33:27 AM UTC 24 | 24860032945 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2802009879 | Oct 03 06:19:07 AM UTC 24 | Oct 03 06:36:24 AM UTC 24 | 78673994411 ps | ||
| T391 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1597721027 | Oct 03 06:23:40 AM UTC 24 | Oct 03 06:36:48 AM UTC 24 | 15989246200 ps | ||
| T392 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3841195946 | Oct 03 06:23:58 AM UTC 24 | Oct 03 06:38:18 AM UTC 24 | 8833952376 ps | ||
| T390 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.432860053 | Oct 03 06:24:25 AM UTC 24 | Oct 03 06:39:16 AM UTC 24 | 25920229591 ps | ||
| T223 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.711724597 | Oct 03 06:19:49 AM UTC 24 | Oct 03 06:39:22 AM UTC 24 | 93564018959 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3592844628 | Oct 03 06:25:54 AM UTC 24 | Oct 03 06:45:20 AM UTC 24 | 12976746723 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_intr_timeout.4163685805 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3247623222 ps |
| CPU time | 24.41 seconds |
| Started | Oct 03 04:40:32 AM UTC 24 |
| Finished | Oct 03 04:40:57 AM UTC 24 |
| Peak memory | 266644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163685805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.4163685805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/7.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/0.alert_handler_sec_cm.610163568 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1651741023 ps |
| CPU time | 33.28 seconds |
| Started | Oct 03 04:37:11 AM UTC 24 |
| Finished | Oct 03 04:37:46 AM UTC 24 |
| Peak memory | 296828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610163568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_h andler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.610163568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/2.alert_handler_sig_int_fail.3121609140 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 792251352 ps |
| CPU time | 36.95 seconds |
| Started | Oct 03 04:37:34 AM UTC 24 |
| Finished | Oct 03 04:38:13 AM UTC 24 |
| Peak memory | 260464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121609140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3121609140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all_with_rand_reset.1029260669 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 17628065274 ps |
| CPU time | 253.65 seconds |
| Started | Oct 03 04:47:29 AM UTC 24 |
| Finished | Oct 03 04:51:46 AM UTC 24 |
| Peak memory | 279120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1029260669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.a lert_handler_stress_all_with_rand_reset.1029260669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/12.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy_stress.3673006271 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1615002442 ps |
| CPU time | 20.94 seconds |
| Started | Oct 03 04:37:11 AM UTC 24 |
| Finished | Oct 03 04:37:33 AM UTC 24 |
| Peak memory | 260512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673006271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3673006271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1681900993 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 309258753 ps |
| CPU time | 37.54 seconds |
| Started | Oct 03 06:11:11 AM UTC 24 |
| Finished | Oct 03 06:11:50 AM UTC 24 |
| Peak memory | 250528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681900993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1681900993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all.1539974777 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 34484105271 ps |
| CPU time | 459 seconds |
| Started | Oct 03 04:37:52 AM UTC 24 |
| Finished | Oct 03 04:45:37 AM UTC 24 |
| Peak memory | 266772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539974777 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_stress_all.1539974777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all.3488984757 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 216808805151 ps |
| CPU time | 3251.92 seconds |
| Started | Oct 03 05:34:57 AM UTC 24 |
| Finished | Oct 03 06:29:45 AM UTC 24 |
| Peak memory | 302048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488984757 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_stress_all.3488984757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/33.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/10.alert_handler_stress_all_with_rand_reset.591624940 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 8536707819 ps |
| CPU time | 335.95 seconds |
| Started | Oct 03 04:44:32 AM UTC 24 |
| Finished | Oct 03 04:50:13 AM UTC 24 |
| Peak memory | 279120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=591624940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.al ert_handler_stress_all_with_rand_reset.591624940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/10.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/1.alert_handler_sig_int_fail.3820434290 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3371503449 ps |
| CPU time | 88.49 seconds |
| Started | Oct 03 04:37:13 AM UTC 24 |
| Finished | Oct 03 04:38:44 AM UTC 24 |
| Peak memory | 260728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820434290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3820434290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1622648835 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 5082800785 ps |
| CPU time | 437.24 seconds |
| Started | Oct 03 06:10:37 AM UTC 24 |
| Finished | Oct 03 06:18:00 AM UTC 24 |
| Peak memory | 277740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622648835 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors.1622648835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all.458274466 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 38548239061 ps |
| CPU time | 2452.73 seconds |
| Started | Oct 03 05:24:34 AM UTC 24 |
| Finished | Oct 03 06:05:55 AM UTC 24 |
| Peak memory | 300196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458274466 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_stress_all.458274466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/28.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg.1463952814 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 90580810824 ps |
| CPU time | 1232.92 seconds |
| Started | Oct 03 04:43:56 AM UTC 24 |
| Finished | Oct 03 05:04:44 AM UTC 24 |
| Peak memory | 299548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463952814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1463952814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/10.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_classes.182717892 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 1825583768 ps |
| CPU time | 43.45 seconds |
| Started | Oct 03 04:37:09 AM UTC 24 |
| Finished | Oct 03 04:37:55 AM UTC 24 |
| Peak memory | 260692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182717892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.182717892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy.4114989642 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 29873353233 ps |
| CPU time | 791.32 seconds |
| Started | Oct 03 04:39:49 AM UTC 24 |
| Finished | Oct 03 04:53:10 AM UTC 24 |
| Peak memory | 281044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114989642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.4114989642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/6.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.711724597 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 93564018959 ps |
| CPU time | 1158.68 seconds |
| Started | Oct 03 06:19:49 AM UTC 24 |
| Finished | Oct 03 06:39:22 AM UTC 24 |
| Peak memory | 277544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711724597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow _reg_errors_with_csr_rw.711724597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all.1773939132 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 86322288133 ps |
| CPU time | 1650.99 seconds |
| Started | Oct 03 04:39:31 AM UTC 24 |
| Finished | Oct 03 05:07:23 AM UTC 24 |
| Peak memory | 299396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773939132 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_stress_all.1773939132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/5.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3780173774 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 5319162729 ps |
| CPU time | 354.11 seconds |
| Started | Oct 03 06:24:09 AM UTC 24 |
| Finished | Oct 03 06:30:09 AM UTC 24 |
| Peak memory | 283884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780173774 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors.3780173774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/1.alert_handler_ping_timeout.3331718976 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 26089354206 ps |
| CPU time | 502.93 seconds |
| Started | Oct 03 04:37:14 AM UTC 24 |
| Finished | Oct 03 04:45:43 AM UTC 24 |
| Peak memory | 260640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331718976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3331718976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.893935137 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 4718149427 ps |
| CPU time | 328.06 seconds |
| Started | Oct 03 06:20:21 AM UTC 24 |
| Finished | Oct 03 06:25:53 AM UTC 24 |
| Peak memory | 277552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893935137 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors.893935137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/4.alert_handler_ping_timeout.2246037558 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 12024637836 ps |
| CPU time | 747.48 seconds |
| Started | Oct 03 04:38:40 AM UTC 24 |
| Finished | Oct 03 04:51:18 AM UTC 24 |
| Peak memory | 260896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246037558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2246037558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg.3500617823 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 23874100019 ps |
| CPU time | 1592.85 seconds |
| Started | Oct 03 05:00:09 AM UTC 24 |
| Finished | Oct 03 05:27:02 AM UTC 24 |
| Peak memory | 283164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500617823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3500617823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/17.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all_with_rand_reset.1933215931 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1400212262 ps |
| CPU time | 112.64 seconds |
| Started | Oct 03 04:37:57 AM UTC 24 |
| Finished | Oct 03 04:39:52 AM UTC 24 |
| Peak memory | 278988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1933215931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.al ert_handler_stress_all_with_rand_reset.1933215931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_intr_test.3468295776 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 99683387 ps |
| CPU time | 2.13 seconds |
| Started | Oct 03 06:18:51 AM UTC 24 |
| Finished | Oct 03 06:18:54 AM UTC 24 |
| Peak memory | 248424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468295776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3468295776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/6.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.432860053 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 25920229591 ps |
| CPU time | 878.93 seconds |
| Started | Oct 03 06:24:25 AM UTC 24 |
| Finished | Oct 03 06:39:16 AM UTC 24 |
| Peak memory | 277612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432860053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shado w_reg_errors_with_csr_rw.432860053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.4192077176 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 4538666224 ps |
| CPU time | 272.14 seconds |
| Started | Oct 03 06:14:50 AM UTC 24 |
| Finished | Oct 03 06:19:26 AM UTC 24 |
| Peak memory | 250724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192077176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.4192077176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/17.alert_handler_ping_timeout.1534071236 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 17518280159 ps |
| CPU time | 958.46 seconds |
| Started | Oct 03 05:00:07 AM UTC 24 |
| Finished | Oct 03 05:16:18 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534071236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1534071236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.4099194252 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 79619496420 ps |
| CPU time | 520.3 seconds |
| Started | Oct 03 06:17:22 AM UTC 24 |
| Finished | Oct 03 06:26:09 AM UTC 24 |
| Peak memory | 277536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099194252 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors.4099194252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg.2190867865 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 75626748550 ps |
| CPU time | 3081.2 seconds |
| Started | Oct 03 04:49:33 AM UTC 24 |
| Finished | Oct 03 05:41:30 AM UTC 24 |
| Peak memory | 302052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190867865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2190867865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/13.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_classes.3171310455 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1362803308 ps |
| CPU time | 43.8 seconds |
| Started | Oct 03 04:38:29 AM UTC 24 |
| Finished | Oct 03 04:39:15 AM UTC 24 |
| Peak memory | 266680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171310455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.3171310455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/10.alert_handler_ping_timeout.1579410225 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 26684560912 ps |
| CPU time | 878.32 seconds |
| Started | Oct 03 04:43:56 AM UTC 24 |
| Finished | Oct 03 04:58:46 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579410225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1579410225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all_with_rand_reset.683426334 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 2825393965 ps |
| CPU time | 202.34 seconds |
| Started | Oct 03 04:40:24 AM UTC 24 |
| Finished | Oct 03 04:43:50 AM UTC 24 |
| Peak memory | 281176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=683426334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.ale rt_handler_stress_all_with_rand_reset.683426334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/0.alert_handler_ping_timeout.3470701523 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 47982808329 ps |
| CPU time | 575.95 seconds |
| Started | Oct 03 04:37:10 AM UTC 24 |
| Finished | Oct 03 04:46:53 AM UTC 24 |
| Peak memory | 260564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470701523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3470701523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg.3101790085 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 176824549763 ps |
| CPU time | 3036.09 seconds |
| Started | Oct 03 06:02:27 AM UTC 24 |
| Finished | Oct 03 06:53:40 AM UTC 24 |
| Peak memory | 302124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101790085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3101790085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/46.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3644911295 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 100651910260 ps |
| CPU time | 515.6 seconds |
| Started | Oct 03 06:22:13 AM UTC 24 |
| Finished | Oct 03 06:30:56 AM UTC 24 |
| Peak memory | 277804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644911295 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shad ow_reg_errors_with_csr_rw.3644911295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg.2740082654 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 55830234290 ps |
| CPU time | 1382.71 seconds |
| Started | Oct 03 04:57:36 AM UTC 24 |
| Finished | Oct 03 05:20:57 AM UTC 24 |
| Peak memory | 299740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740082654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2740082654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/16.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all.155153338 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 15929396157 ps |
| CPU time | 1024.54 seconds |
| Started | Oct 03 04:38:21 AM UTC 24 |
| Finished | Oct 03 04:55:40 AM UTC 24 |
| Peak memory | 276944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155153338 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_stress_all.155153338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2499224560 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 6445321404 ps |
| CPU time | 226.45 seconds |
| Started | Oct 03 06:19:50 AM UTC 24 |
| Finished | Oct 03 06:23:40 AM UTC 24 |
| Peak memory | 281636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499224560 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors.2499224560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_classes.519266558 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1573820620 ps |
| CPU time | 16.82 seconds |
| Started | Oct 03 04:38:02 AM UTC 24 |
| Finished | Oct 03 04:38:20 AM UTC 24 |
| Peak memory | 260692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519266558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.519266558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/12.alert_handler_ping_timeout.151963519 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 12908541759 ps |
| CPU time | 750.23 seconds |
| Started | Oct 03 04:46:44 AM UTC 24 |
| Finished | Oct 03 04:59:24 AM UTC 24 |
| Peak memory | 260640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151963519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.151963519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/12.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg.2208927490 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 101476170021 ps |
| CPU time | 3340.91 seconds |
| Started | Oct 03 04:39:18 AM UTC 24 |
| Finished | Oct 03 05:35:39 AM UTC 24 |
| Peak memory | 302052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208927490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2208927490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/5.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3312281413 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1758673912 ps |
| CPU time | 133.41 seconds |
| Started | Oct 03 06:11:34 AM UTC 24 |
| Finished | Oct 03 06:13:50 AM UTC 24 |
| Peak memory | 248476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312281413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3312281413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy.4291106552 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 33736891167 ps |
| CPU time | 1570.3 seconds |
| Started | Oct 03 04:43:52 AM UTC 24 |
| Finished | Oct 03 05:10:21 AM UTC 24 |
| Peak memory | 293660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291106552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.4291106552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/10.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3592844628 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 12976746723 ps |
| CPU time | 1151.23 seconds |
| Started | Oct 03 06:25:54 AM UTC 24 |
| Finished | Oct 03 06:45:20 AM UTC 24 |
| Peak memory | 277740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592844628 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shad ow_reg_errors_with_csr_rw.3592844628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2384706864 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 97739390 ps |
| CPU time | 6.23 seconds |
| Started | Oct 03 06:12:55 AM UTC 24 |
| Finished | Oct 03 06:13:03 AM UTC 24 |
| Peak memory | 248484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384706864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2384706864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_intr_test.2809205595 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 33439690 ps |
| CPU time | 1.84 seconds |
| Started | Oct 03 06:21:13 AM UTC 24 |
| Finished | Oct 03 06:21:16 AM UTC 24 |
| Peak memory | 246852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809205595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2809205595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/10.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all_with_rand_reset.2512340486 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 25857555288 ps |
| CPU time | 757.94 seconds |
| Started | Oct 03 05:38:14 AM UTC 24 |
| Finished | Oct 03 05:51:02 AM UTC 24 |
| Peak memory | 293720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2512340486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.a lert_handler_stress_all_with_rand_reset.2512340486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/34.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.831406052 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 26415973623 ps |
| CPU time | 596.96 seconds |
| Started | Oct 03 06:18:31 AM UTC 24 |
| Finished | Oct 03 06:28:37 AM UTC 24 |
| Peak memory | 281716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831406052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow _reg_errors_with_csr_rw.831406052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/20.alert_handler_ping_timeout.3262639716 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 12579974289 ps |
| CPU time | 490.7 seconds |
| Started | Oct 03 05:06:32 AM UTC 24 |
| Finished | Oct 03 05:14:49 AM UTC 24 |
| Peak memory | 260572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262639716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3262639716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/20.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg.3663133146 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 96888843903 ps |
| CPU time | 1042.9 seconds |
| Started | Oct 03 05:32:15 AM UTC 24 |
| Finished | Oct 03 05:49:51 AM UTC 24 |
| Peak memory | 283092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663133146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3663133146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/32.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all.4155666084 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 51723468171 ps |
| CPU time | 1739.73 seconds |
| Started | Oct 03 05:41:48 AM UTC 24 |
| Finished | Oct 03 06:11:09 AM UTC 24 |
| Peak memory | 293596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155666084 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_stress_all.4155666084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/36.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all.995313554 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 79150894690 ps |
| CPU time | 2120.78 seconds |
| Started | Oct 03 04:40:58 AM UTC 24 |
| Finished | Oct 03 05:16:45 AM UTC 24 |
| Peak memory | 316192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995313554 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_stress_all.995313554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/7.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3574319973 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 157068185467 ps |
| CPU time | 722.92 seconds |
| Started | Oct 03 06:18:01 AM UTC 24 |
| Finished | Oct 03 06:30:14 AM UTC 24 |
| Peak memory | 277740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574319973 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shado w_reg_errors_with_csr_rw.3574319973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_alerts.1570794392 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3158003399 ps |
| CPU time | 67.05 seconds |
| Started | Oct 03 04:37:18 AM UTC 24 |
| Finished | Oct 03 04:38:27 AM UTC 24 |
| Peak memory | 266636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570794392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1570794392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_classes.1451633958 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 3997560610 ps |
| CPU time | 42.26 seconds |
| Started | Oct 03 04:45:56 AM UTC 24 |
| Finished | Oct 03 04:46:39 AM UTC 24 |
| Peak memory | 260792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451633958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1451633958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/12.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/24.alert_handler_sig_int_fail.2048670376 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 657071188 ps |
| CPU time | 36.51 seconds |
| Started | Oct 03 05:15:24 AM UTC 24 |
| Finished | Oct 03 05:16:02 AM UTC 24 |
| Peak memory | 260428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048670376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2048670376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/24.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all.3498400596 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 7085812874 ps |
| CPU time | 232.39 seconds |
| Started | Oct 03 05:19:27 AM UTC 24 |
| Finished | Oct 03 05:23:24 AM UTC 24 |
| Peak memory | 262608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498400596 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_stress_all.3498400596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/25.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg.2891310959 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 33215030897 ps |
| CPU time | 1867.13 seconds |
| Started | Oct 03 05:45:01 AM UTC 24 |
| Finished | Oct 03 06:16:30 AM UTC 24 |
| Peak memory | 283092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891310959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2891310959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/38.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/3.alert_handler_alert_accum_saturation.4124810540 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 18180463 ps |
| CPU time | 3.6 seconds |
| Started | Oct 03 04:38:21 AM UTC 24 |
| Finished | Oct 03 04:38:26 AM UTC 24 |
| Peak memory | 260700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124810540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.4124810540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/0.alert_handler_alert_accum_saturation.210301621 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 38446740 ps |
| CPU time | 4.57 seconds |
| Started | Oct 03 04:37:11 AM UTC 24 |
| Finished | Oct 03 04:37:17 AM UTC 24 |
| Peak memory | 260660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210301621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.210301621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/1.alert_handler_alert_accum_saturation.2243566126 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 108286813 ps |
| CPU time | 4.75 seconds |
| Started | Oct 03 04:37:15 AM UTC 24 |
| Finished | Oct 03 04:37:21 AM UTC 24 |
| Peak memory | 260704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243566126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2243566126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/11.alert_handler_alert_accum_saturation.1247799447 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 29648948 ps |
| CPU time | 4.67 seconds |
| Started | Oct 03 04:45:39 AM UTC 24 |
| Finished | Oct 03 04:45:44 AM UTC 24 |
| Peak memory | 260776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247799447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1247799447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/11.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all.115373259 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 36978145191 ps |
| CPU time | 2556.45 seconds |
| Started | Oct 03 04:37:11 AM UTC 24 |
| Finished | Oct 03 05:20:19 AM UTC 24 |
| Peak memory | 302044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115373259 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_stress_all.115373259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_classes.4117984238 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 2575977987 ps |
| CPU time | 105.54 seconds |
| Started | Oct 03 05:01:53 AM UTC 24 |
| Finished | Oct 03 05:03:41 AM UTC 24 |
| Peak memory | 266744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117984238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.4117984238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/18.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all.146251387 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 15606602317 ps |
| CPU time | 1488.02 seconds |
| Started | Oct 03 05:32:34 AM UTC 24 |
| Finished | Oct 03 05:57:40 AM UTC 24 |
| Peak memory | 299468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146251387 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_stress_all.146251387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/32.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all.2581094216 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 137250140584 ps |
| CPU time | 2247.1 seconds |
| Started | Oct 03 05:49:53 AM UTC 24 |
| Finished | Oct 03 06:27:45 AM UTC 24 |
| Peak memory | 302116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581094216 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_stress_all.2581094216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/40.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/49.alert_handler_sig_int_fail.2345840329 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 3113370081 ps |
| CPU time | 79.51 seconds |
| Started | Oct 03 06:08:56 AM UTC 24 |
| Finished | Oct 03 06:10:17 AM UTC 24 |
| Peak memory | 266708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345840329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2345840329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/49.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3889778619 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 8534904894 ps |
| CPU time | 548.53 seconds |
| Started | Oct 03 06:12:24 AM UTC 24 |
| Finished | Oct 03 06:21:40 AM UTC 24 |
| Peak memory | 281836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889778619 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors.3889778619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_intg_err.456681818 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 1048991687 ps |
| CPU time | 90.84 seconds |
| Started | Oct 03 06:19:54 AM UTC 24 |
| Finished | Oct 03 06:21:27 AM UTC 24 |
| Peak memory | 250528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456681818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.456681818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/8.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3841195946 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 8833952376 ps |
| CPU time | 848.07 seconds |
| Started | Oct 03 06:23:58 AM UTC 24 |
| Finished | Oct 03 06:38:18 AM UTC 24 |
| Peak memory | 277536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841195946 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shad ow_reg_errors_with_csr_rw.3841195946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3944660443 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 1841974360 ps |
| CPU time | 41.37 seconds |
| Started | Oct 03 06:14:37 AM UTC 24 |
| Finished | Oct 03 06:15:20 AM UTC 24 |
| Peak memory | 258720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944660443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3944660443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/0.alert_handler_sig_int_fail.2700417198 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1129046348 ps |
| CPU time | 79.3 seconds |
| Started | Oct 03 04:37:10 AM UTC 24 |
| Finished | Oct 03 04:38:31 AM UTC 24 |
| Peak memory | 266680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700417198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2700417198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg.1223701597 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 111355191895 ps |
| CPU time | 1752.45 seconds |
| Started | Oct 03 04:46:47 AM UTC 24 |
| Finished | Oct 03 05:16:21 AM UTC 24 |
| Peak memory | 283092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223701597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1223701597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/12.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all.3209706163 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 83547900091 ps |
| CPU time | 2362.62 seconds |
| Started | Oct 03 04:55:32 AM UTC 24 |
| Finished | Oct 03 05:35:23 AM UTC 24 |
| Peak memory | 302048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209706163 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_stress_all.3209706163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/15.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg_stub_clk.52434037 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 34768353228 ps |
| CPU time | 2611.03 seconds |
| Started | Oct 03 04:58:01 AM UTC 24 |
| Finished | Oct 03 05:42:04 AM UTC 24 |
| Peak memory | 300080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52434037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.52434037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/16.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_alert_accum.438727242 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 1896628453 ps |
| CPU time | 158.58 seconds |
| Started | Oct 03 04:59:26 AM UTC 24 |
| Finished | Oct 03 05:02:08 AM UTC 24 |
| Peak memory | 266868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438727242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.438727242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/17.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/18.alert_handler_sig_int_fail.4053621377 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 2079802488 ps |
| CPU time | 56.13 seconds |
| Started | Oct 03 05:02:10 AM UTC 24 |
| Finished | Oct 03 05:03:07 AM UTC 24 |
| Peak memory | 260428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053621377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.4053621377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/18.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg_stub_clk.3641484388 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 39531613212 ps |
| CPU time | 2452.75 seconds |
| Started | Oct 03 05:05:06 AM UTC 24 |
| Finished | Oct 03 05:46:28 AM UTC 24 |
| Peak memory | 302060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641484388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3641484388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/19.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/21.alert_handler_ping_timeout.1297231171 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 44600419481 ps |
| CPU time | 588.93 seconds |
| Started | Oct 03 05:09:34 AM UTC 24 |
| Finished | Oct 03 05:19:31 AM UTC 24 |
| Peak memory | 260644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297231171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1297231171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all_with_rand_reset.1177121101 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 10261372068 ps |
| CPU time | 336.65 seconds |
| Started | Oct 03 05:13:43 AM UTC 24 |
| Finished | Oct 03 05:19:26 AM UTC 24 |
| Peak memory | 279120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1177121101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.a lert_handler_stress_all_with_rand_reset.1177121101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/23.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg.140883262 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 92297091833 ps |
| CPU time | 1807.47 seconds |
| Started | Oct 03 05:18:26 AM UTC 24 |
| Finished | Oct 03 05:48:58 AM UTC 24 |
| Peak memory | 283348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140883262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.140883262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/25.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/28.alert_handler_sig_int_fail.613967703 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 730294245 ps |
| CPU time | 26.1 seconds |
| Started | Oct 03 05:23:34 AM UTC 24 |
| Finished | Oct 03 05:24:02 AM UTC 24 |
| Peak memory | 266872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613967703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.613967703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/28.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/30.alert_handler_ping_timeout.2326837944 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 12410130324 ps |
| CPU time | 618.07 seconds |
| Started | Oct 03 05:28:24 AM UTC 24 |
| Finished | Oct 03 05:38:51 AM UTC 24 |
| Peak memory | 260568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326837944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2326837944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/30.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all_with_rand_reset.3417350177 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 4284849172 ps |
| CPU time | 610.94 seconds |
| Started | Oct 03 05:30:19 AM UTC 24 |
| Finished | Oct 03 05:40:38 AM UTC 24 |
| Peak memory | 281104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3417350177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.a lert_handler_stress_all_with_rand_reset.3417350177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg.3576671832 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 57891751873 ps |
| CPU time | 1517.57 seconds |
| Started | Oct 03 04:38:40 AM UTC 24 |
| Finished | Oct 03 05:04:17 AM UTC 24 |
| Peak memory | 283164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576671832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3576671832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all.2507705767 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 194021248187 ps |
| CPU time | 3124.43 seconds |
| Started | Oct 03 05:57:38 AM UTC 24 |
| Finished | Oct 03 06:50:20 AM UTC 24 |
| Peak memory | 302188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507705767 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_stress_all.2507705767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/44.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/45.alert_handler_stress_all.3300992340 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 64868256621 ps |
| CPU time | 1838.95 seconds |
| Started | Oct 03 06:00:29 AM UTC 24 |
| Finished | Oct 03 06:31:31 AM UTC 24 |
| Peak memory | 299476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300992340 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_stress_all.3300992340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/45.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg_stub_clk.3279489827 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 98223760178 ps |
| CPU time | 2837.52 seconds |
| Started | Oct 03 06:02:32 AM UTC 24 |
| Finished | Oct 03 06:50:22 AM UTC 24 |
| Peak memory | 302056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279489827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3279489827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/46.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/46.alert_handler_sig_int_fail.2131726108 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 694213592 ps |
| CPU time | 64.11 seconds |
| Started | Oct 03 06:01:37 AM UTC 24 |
| Finished | Oct 03 06:02:43 AM UTC 24 |
| Peak memory | 266572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131726108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2131726108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/46.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all.1286121236 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 41105071336 ps |
| CPU time | 691.68 seconds |
| Started | Oct 03 06:07:56 AM UTC 24 |
| Finished | Oct 03 06:19:36 AM UTC 24 |
| Peak memory | 277020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286121236 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_stress_all.1286121236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/48.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all.647222318 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 91281749198 ps |
| CPU time | 3438.86 seconds |
| Started | Oct 03 04:40:17 AM UTC 24 |
| Finished | Oct 03 05:38:18 AM UTC 24 |
| Peak memory | 318432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647222318 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_stress_all.647222318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/6.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all_with_rand_reset.3421149431 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 2264842955 ps |
| CPU time | 367.43 seconds |
| Started | Oct 03 04:45:40 AM UTC 24 |
| Finished | Oct 03 04:51:53 AM UTC 24 |
| Peak memory | 283484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3421149431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.a lert_handler_stress_all_with_rand_reset.3421149431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/11.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.459013713 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 100570734500 ps |
| CPU time | 588.16 seconds |
| Started | Oct 03 06:23:01 AM UTC 24 |
| Finished | Oct 03 06:32:57 AM UTC 24 |
| Peak memory | 277540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459013713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shado w_reg_errors_with_csr_rw.459013713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2818030818 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 15057442446 ps |
| CPU time | 630.91 seconds |
| Started | Oct 03 06:20:17 AM UTC 24 |
| Finished | Oct 03 06:30:58 AM UTC 24 |
| Peak memory | 279660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818030818 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shado w_reg_errors_with_csr_rw.2818030818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_intr_test.2695613537 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 12328559 ps |
| CPU time | 2.32 seconds |
| Started | Oct 03 06:11:19 AM UTC 24 |
| Finished | Oct 03 06:11:23 AM UTC 24 |
| Peak memory | 248424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695613537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2695613537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_intg_err.4071373778 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 1254074065 ps |
| CPU time | 55.09 seconds |
| Started | Oct 03 06:21:13 AM UTC 24 |
| Finished | Oct 03 06:22:10 AM UTC 24 |
| Peak memory | 248480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071373778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.4071373778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/10.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_intg_err.864802089 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 107369298 ps |
| CPU time | 6.22 seconds |
| Started | Oct 03 06:24:13 AM UTC 24 |
| Finished | Oct 03 06:24:21 AM UTC 24 |
| Peak memory | 248552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864802089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.864802089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/15.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2627834821 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 200358970 ps |
| CPU time | 14.91 seconds |
| Started | Oct 03 06:26:07 AM UTC 24 |
| Finished | Oct 03 06:26:23 AM UTC 24 |
| Peak memory | 248676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627834821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2627834821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/19.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.770606247 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 1798738622 ps |
| CPU time | 99.53 seconds |
| Started | Oct 03 06:20:56 AM UTC 24 |
| Finished | Oct 03 06:22:38 AM UTC 24 |
| Peak memory | 267232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770606247 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_errors.770606247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_intg_err.434217361 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 862071872 ps |
| CPU time | 42.43 seconds |
| Started | Oct 03 06:22:39 AM UTC 24 |
| Finished | Oct 03 06:23:23 AM UTC 24 |
| Peak memory | 260760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434217361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.434217361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/12.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1171890032 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 34604751 ps |
| CPU time | 4.67 seconds |
| Started | Oct 03 06:23:41 AM UTC 24 |
| Finished | Oct 03 06:23:47 AM UTC 24 |
| Peak memory | 248552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171890032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1171890032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/14.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3693294581 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 73446004 ps |
| CPU time | 8.42 seconds |
| Started | Oct 03 06:25:29 AM UTC 24 |
| Finished | Oct 03 06:25:39 AM UTC 24 |
| Peak memory | 248476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693294581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3693294581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/18.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2681021465 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 211330673 ps |
| CPU time | 6.53 seconds |
| Started | Oct 03 06:17:28 AM UTC 24 |
| Finished | Oct 03 06:17:36 AM UTC 24 |
| Peak memory | 248680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681021465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2681021465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/3.alert_handler_sig_int_fail.2823828842 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 262274515 ps |
| CPU time | 42.8 seconds |
| Started | Oct 03 04:38:11 AM UTC 24 |
| Finished | Oct 03 04:38:56 AM UTC 24 |
| Peak memory | 266608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823828842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2823828842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2354387104 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 13211533499 ps |
| CPU time | 120.62 seconds |
| Started | Oct 03 06:23:23 AM UTC 24 |
| Finished | Oct 03 06:25:27 AM UTC 24 |
| Peak memory | 250660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354387104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2354387104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/13.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3743892920 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 446552531 ps |
| CPU time | 59.65 seconds |
| Started | Oct 03 06:16:26 AM UTC 24 |
| Finished | Oct 03 06:17:28 AM UTC 24 |
| Peak memory | 250528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743892920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3743892920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3466481574 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 43855145 ps |
| CPU time | 4.85 seconds |
| Started | Oct 03 06:18:20 AM UTC 24 |
| Finished | Oct 03 06:18:26 AM UTC 24 |
| Peak memory | 248552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466481574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3466481574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/5.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1550734680 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 86334683 ps |
| CPU time | 8.5 seconds |
| Started | Oct 03 06:18:49 AM UTC 24 |
| Finished | Oct 03 06:18:58 AM UTC 24 |
| Peak memory | 250728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550734680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1550734680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/6.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_intg_err.818140587 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 459809577 ps |
| CPU time | 38.32 seconds |
| Started | Oct 03 06:19:27 AM UTC 24 |
| Finished | Oct 03 06:20:07 AM UTC 24 |
| Peak memory | 250524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818140587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.818140587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/7.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1773490349 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 114795622 ps |
| CPU time | 4.44 seconds |
| Started | Oct 03 06:20:31 AM UTC 24 |
| Finished | Oct 03 06:20:37 AM UTC 24 |
| Peak memory | 248484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773490349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1773490349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/9.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg.3435451155 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 63775090944 ps |
| CPU time | 2101.22 seconds |
| Started | Oct 03 05:09:41 AM UTC 24 |
| Finished | Oct 03 05:45:08 AM UTC 24 |
| Peak memory | 285668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435451155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3435451155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/21.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.4268575313 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 821434702 ps |
| CPU time | 165.39 seconds |
| Started | Oct 03 06:11:34 AM UTC 24 |
| Finished | Oct 03 06:14:22 AM UTC 24 |
| Peak memory | 250724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268575313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.4268575313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1128807514 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 320435083 ps |
| CPU time | 8.19 seconds |
| Started | Oct 03 06:11:23 AM UTC 24 |
| Finished | Oct 03 06:11:33 AM UTC 24 |
| Peak memory | 260764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128807514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1128807514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2890777907 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 223126209 ps |
| CPU time | 8.9 seconds |
| Started | Oct 03 06:12:13 AM UTC 24 |
| Finished | Oct 03 06:12:23 AM UTC 24 |
| Peak memory | 250788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890777907 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_mem_ rw_with_rand_reset.2890777907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_rw.186163476 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 125465497 ps |
| CPU time | 8.39 seconds |
| Started | Oct 03 06:11:23 AM UTC 24 |
| Finished | Oct 03 06:11:33 AM UTC 24 |
| Peak memory | 248548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186163476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.186163476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1597886873 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 684609402 ps |
| CPU time | 30.48 seconds |
| Started | Oct 03 06:11:51 AM UTC 24 |
| Finished | Oct 03 06:12:23 AM UTC 24 |
| Peak memory | 250524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597886873 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outstanding.1597886873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.751230437 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 6061577908 ps |
| CPU time | 603.17 seconds |
| Started | Oct 03 06:10:18 AM UTC 24 |
| Finished | Oct 03 06:20:29 AM UTC 24 |
| Peak memory | 281644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751230437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow _reg_errors_with_csr_rw.751230437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_errors.2000943643 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 749853232 ps |
| CPU time | 14.27 seconds |
| Started | Oct 03 06:11:07 AM UTC 24 |
| Finished | Oct 03 06:11:22 AM UTC 24 |
| Peak memory | 265004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000943643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2000943643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_aliasing.4294187915 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 17580016288 ps |
| CPU time | 355.14 seconds |
| Started | Oct 03 06:13:47 AM UTC 24 |
| Finished | Oct 03 06:19:47 AM UTC 24 |
| Peak memory | 250588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294187915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.4294187915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.139222061 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 11932190174 ps |
| CPU time | 342.06 seconds |
| Started | Oct 03 06:13:29 AM UTC 24 |
| Finished | Oct 03 06:19:16 AM UTC 24 |
| Peak memory | 248548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139222061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/al ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.139222061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3456601755 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 109752936 ps |
| CPU time | 9.77 seconds |
| Started | Oct 03 06:13:08 AM UTC 24 |
| Finished | Oct 03 06:13:19 AM UTC 24 |
| Peak memory | 260764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456601755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3456601755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3135506357 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 309111839 ps |
| CPU time | 24.08 seconds |
| Started | Oct 03 06:14:15 AM UTC 24 |
| Finished | Oct 03 06:14:41 AM UTC 24 |
| Peak memory | 262948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135506357 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_mem_ rw_with_rand_reset.3135506357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_rw.3056494750 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 22575957 ps |
| CPU time | 5.99 seconds |
| Started | Oct 03 06:13:21 AM UTC 24 |
| Finished | Oct 03 06:13:28 AM UTC 24 |
| Peak memory | 248476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056494750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3056494750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_intr_test.4115686958 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 22011713 ps |
| CPU time | 3.13 seconds |
| Started | Oct 03 06:13:03 AM UTC 24 |
| Finished | Oct 03 06:13:07 AM UTC 24 |
| Peak memory | 248500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115686958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.4115686958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1391100172 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 555083224 ps |
| CPU time | 22.29 seconds |
| Started | Oct 03 06:13:50 AM UTC 24 |
| Finished | Oct 03 06:14:14 AM UTC 24 |
| Peak memory | 258916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391100172 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outstanding.1391100172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3517552396 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 8431023584 ps |
| CPU time | 694.15 seconds |
| Started | Oct 03 06:12:24 AM UTC 24 |
| Finished | Oct 03 06:24:07 AM UTC 24 |
| Peak memory | 277612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517552396 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shado w_reg_errors_with_csr_rw.3517552396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_errors.204543419 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 1176608606 ps |
| CPU time | 28.31 seconds |
| Started | Oct 03 06:12:25 AM UTC 24 |
| Finished | Oct 03 06:12:55 AM UTC 24 |
| Peak memory | 260896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204543419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.204543419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2873594139 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 590530131 ps |
| CPU time | 20.67 seconds |
| Started | Oct 03 06:21:28 AM UTC 24 |
| Finished | Oct 03 06:21:49 AM UTC 24 |
| Peak memory | 266968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873594139 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_mem _rw_with_rand_reset.2873594139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/10.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_rw.3280067013 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 355210442 ps |
| CPU time | 7.13 seconds |
| Started | Oct 03 06:21:18 AM UTC 24 |
| Finished | Oct 03 06:21:26 AM UTC 24 |
| Peak memory | 248552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280067013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3280067013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/10.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3793499218 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 4539766982 ps |
| CPU time | 42.38 seconds |
| Started | Oct 03 06:21:18 AM UTC 24 |
| Finished | Oct 03 06:22:02 AM UTC 24 |
| Peak memory | 258780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793499218 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_outstanding.3793499218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/10.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2313623298 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 8906148489 ps |
| CPU time | 313.07 seconds |
| Started | Oct 03 06:20:49 AM UTC 24 |
| Finished | Oct 03 06:26:07 AM UTC 24 |
| Peak memory | 277676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313623298 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shad ow_reg_errors_with_csr_rw.2313623298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_errors.3760573769 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 142880879 ps |
| CPU time | 10.69 seconds |
| Started | Oct 03 06:21:00 AM UTC 24 |
| Finished | Oct 03 06:21:12 AM UTC 24 |
| Peak memory | 266980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760573769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3760573769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/10.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1732709819 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 650856110 ps |
| CPU time | 14.21 seconds |
| Started | Oct 03 06:22:13 AM UTC 24 |
| Finished | Oct 03 06:22:28 AM UTC 24 |
| Peak memory | 250588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732709819 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_mem _rw_with_rand_reset.1732709819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/11.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_rw.1538174824 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 285573847 ps |
| CPU time | 13.34 seconds |
| Started | Oct 03 06:22:09 AM UTC 24 |
| Finished | Oct 03 06:22:24 AM UTC 24 |
| Peak memory | 248676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538174824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1538174824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/11.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_intr_test.2126976976 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 14672686 ps |
| CPU time | 2.1 seconds |
| Started | Oct 03 06:22:08 AM UTC 24 |
| Finished | Oct 03 06:22:11 AM UTC 24 |
| Peak memory | 248624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126976976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2126976976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/11.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3937827104 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 654118319 ps |
| CPU time | 36.93 seconds |
| Started | Oct 03 06:22:11 AM UTC 24 |
| Finished | Oct 03 06:22:49 AM UTC 24 |
| Peak memory | 258716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937827104 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_outstanding.3937827104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/11.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2389845821 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 3500898110 ps |
| CPU time | 113.65 seconds |
| Started | Oct 03 06:21:41 AM UTC 24 |
| Finished | Oct 03 06:23:37 AM UTC 24 |
| Peak memory | 277616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389845821 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_errors.2389845821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.529815540 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 16342190036 ps |
| CPU time | 352.8 seconds |
| Started | Oct 03 06:21:28 AM UTC 24 |
| Finished | Oct 03 06:27:26 AM UTC 24 |
| Peak memory | 277540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529815540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shado w_reg_errors_with_csr_rw.529815540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_errors.4238323782 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 950287408 ps |
| CPU time | 20.9 seconds |
| Started | Oct 03 06:21:50 AM UTC 24 |
| Finished | Oct 03 06:22:12 AM UTC 24 |
| Peak memory | 265136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238323782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.4238323782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/11.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_intg_err.967207679 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 379328228 ps |
| CPU time | 4.23 seconds |
| Started | Oct 03 06:22:03 AM UTC 24 |
| Finished | Oct 03 06:22:09 AM UTC 24 |
| Peak memory | 248676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967207679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.967207679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/11.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1813068724 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 549076716 ps |
| CPU time | 16.38 seconds |
| Started | Oct 03 06:22:54 AM UTC 24 |
| Finished | Oct 03 06:23:11 AM UTC 24 |
| Peak memory | 250584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813068724 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_mem _rw_with_rand_reset.1813068724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/12.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_rw.1332657567 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 118906268 ps |
| CPU time | 8.23 seconds |
| Started | Oct 03 06:22:50 AM UTC 24 |
| Finished | Oct 03 06:22:59 AM UTC 24 |
| Peak memory | 248672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332657567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1332657567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/12.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_intr_test.2750585984 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 10838741 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 06:22:50 AM UTC 24 |
| Finished | Oct 03 06:22:52 AM UTC 24 |
| Peak memory | 246864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750585984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2750585984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/12.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2566352837 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 220567838 ps |
| CPU time | 36.25 seconds |
| Started | Oct 03 06:22:52 AM UTC 24 |
| Finished | Oct 03 06:23:30 AM UTC 24 |
| Peak memory | 260964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566352837 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_outstanding.2566352837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/12.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.4229103866 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 902632466 ps |
| CPU time | 143.98 seconds |
| Started | Oct 03 06:22:25 AM UTC 24 |
| Finished | Oct 03 06:24:52 AM UTC 24 |
| Peak memory | 277552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229103866 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors.4229103866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_errors.1918586471 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 154297358 ps |
| CPU time | 18.14 seconds |
| Started | Oct 03 06:22:29 AM UTC 24 |
| Finished | Oct 03 06:22:49 AM UTC 24 |
| Peak memory | 264932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918586471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1918586471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/12.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.4235704783 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 57712551 ps |
| CPU time | 6.23 seconds |
| Started | Oct 03 06:23:37 AM UTC 24 |
| Finished | Oct 03 06:23:45 AM UTC 24 |
| Peak memory | 250588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235704783 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_mem _rw_with_rand_reset.4235704783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/13.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_rw.3689314162 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 105352019 ps |
| CPU time | 7.59 seconds |
| Started | Oct 03 06:23:30 AM UTC 24 |
| Finished | Oct 03 06:23:39 AM UTC 24 |
| Peak memory | 248548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689314162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3689314162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/13.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_intr_test.3021828646 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 11471695 ps |
| CPU time | 2.19 seconds |
| Started | Oct 03 06:23:26 AM UTC 24 |
| Finished | Oct 03 06:23:29 AM UTC 24 |
| Peak memory | 248424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021828646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3021828646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/13.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3501640025 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 526958527 ps |
| CPU time | 35.13 seconds |
| Started | Oct 03 06:23:31 AM UTC 24 |
| Finished | Oct 03 06:24:08 AM UTC 24 |
| Peak memory | 258920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501640025 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_outstanding.3501640025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/13.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2790366478 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 3324564029 ps |
| CPU time | 104.65 seconds |
| Started | Oct 03 06:23:12 AM UTC 24 |
| Finished | Oct 03 06:24:59 AM UTC 24 |
| Peak memory | 279724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790366478 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_errors.2790366478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_errors.2419171635 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 64622756 ps |
| CPU time | 10.94 seconds |
| Started | Oct 03 06:23:13 AM UTC 24 |
| Finished | Oct 03 06:23:25 AM UTC 24 |
| Peak memory | 265124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419171635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2419171635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/13.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3162416698 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 890927740 ps |
| CPU time | 17.01 seconds |
| Started | Oct 03 06:23:54 AM UTC 24 |
| Finished | Oct 03 06:24:12 AM UTC 24 |
| Peak memory | 250660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162416698 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_mem _rw_with_rand_reset.3162416698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/14.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_rw.158258287 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 188698287 ps |
| CPU time | 8.44 seconds |
| Started | Oct 03 06:23:48 AM UTC 24 |
| Finished | Oct 03 06:23:57 AM UTC 24 |
| Peak memory | 248484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158258287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.158258287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/14.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_intr_test.4098173501 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 14172603 ps |
| CPU time | 2.12 seconds |
| Started | Oct 03 06:23:45 AM UTC 24 |
| Finished | Oct 03 06:23:48 AM UTC 24 |
| Peak memory | 248420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098173501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.4098173501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/14.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.196862414 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 257341656 ps |
| CPU time | 34.82 seconds |
| Started | Oct 03 06:23:50 AM UTC 24 |
| Finished | Oct 03 06:24:26 AM UTC 24 |
| Peak memory | 258716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196862414 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_outstanding.196862414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/14.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2511281084 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 5377212855 ps |
| CPU time | 131.7 seconds |
| Started | Oct 03 06:23:40 AM UTC 24 |
| Finished | Oct 03 06:25:54 AM UTC 24 |
| Peak memory | 279660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511281084 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_errors.2511281084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1597721027 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 15989246200 ps |
| CPU time | 777.25 seconds |
| Started | Oct 03 06:23:40 AM UTC 24 |
| Finished | Oct 03 06:36:48 AM UTC 24 |
| Peak memory | 277676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597721027 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shad ow_reg_errors_with_csr_rw.1597721027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_errors.1944506909 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 563182263 ps |
| CPU time | 10.66 seconds |
| Started | Oct 03 06:23:41 AM UTC 24 |
| Finished | Oct 03 06:23:53 AM UTC 24 |
| Peak memory | 260840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944506909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1944506909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/14.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.737568748 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 201097283 ps |
| CPU time | 22.92 seconds |
| Started | Oct 03 06:24:22 AM UTC 24 |
| Finished | Oct 03 06:24:46 AM UTC 24 |
| Peak memory | 262876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737568748 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_mem_ rw_with_rand_reset.737568748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/15.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_rw.1177404075 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 59216389 ps |
| CPU time | 7.73 seconds |
| Started | Oct 03 06:24:22 AM UTC 24 |
| Finished | Oct 03 06:24:31 AM UTC 24 |
| Peak memory | 248480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177404075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1177404075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/15.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_intr_test.2256097043 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 8248828 ps |
| CPU time | 1.81 seconds |
| Started | Oct 03 06:24:18 AM UTC 24 |
| Finished | Oct 03 06:24:21 AM UTC 24 |
| Peak memory | 244876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256097043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2256097043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/15.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3754787157 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 1025646848 ps |
| CPU time | 64.11 seconds |
| Started | Oct 03 06:24:22 AM UTC 24 |
| Finished | Oct 03 06:25:28 AM UTC 24 |
| Peak memory | 258724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754787157 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_outstanding.3754787157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/15.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_errors.3597183258 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 385730668 ps |
| CPU time | 13.95 seconds |
| Started | Oct 03 06:24:09 AM UTC 24 |
| Finished | Oct 03 06:24:25 AM UTC 24 |
| Peak memory | 267184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597183258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3597183258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/15.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1256126576 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 83640280 ps |
| CPU time | 8.49 seconds |
| Started | Oct 03 06:24:53 AM UTC 24 |
| Finished | Oct 03 06:25:03 AM UTC 24 |
| Peak memory | 250788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256126576 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_mem _rw_with_rand_reset.1256126576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/16.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_rw.2915874621 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 34985453 ps |
| CPU time | 8.28 seconds |
| Started | Oct 03 06:24:52 AM UTC 24 |
| Finished | Oct 03 06:25:01 AM UTC 24 |
| Peak memory | 248552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915874621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2915874621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/16.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_intr_test.1648184048 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 6785210 ps |
| CPU time | 2.25 seconds |
| Started | Oct 03 06:24:48 AM UTC 24 |
| Finished | Oct 03 06:24:52 AM UTC 24 |
| Peak memory | 246448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648184048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1648184048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/16.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2665355356 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 2986122078 ps |
| CPU time | 78.4 seconds |
| Started | Oct 03 06:24:53 AM UTC 24 |
| Finished | Oct 03 06:26:13 AM UTC 24 |
| Peak memory | 258980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665355356 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_outstanding.2665355356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/16.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1135886527 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 975550549 ps |
| CPU time | 110.36 seconds |
| Started | Oct 03 06:24:28 AM UTC 24 |
| Finished | Oct 03 06:26:20 AM UTC 24 |
| Peak memory | 277548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135886527 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_errors.1135886527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_errors.121165077 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 671545505 ps |
| CPU time | 17.16 seconds |
| Started | Oct 03 06:24:32 AM UTC 24 |
| Finished | Oct 03 06:24:51 AM UTC 24 |
| Peak memory | 265204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121165077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.121165077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/16.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_intg_err.295055648 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 1144187258 ps |
| CPU time | 29.02 seconds |
| Started | Oct 03 06:24:47 AM UTC 24 |
| Finished | Oct 03 06:25:17 AM UTC 24 |
| Peak memory | 248480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295055648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.295055648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/16.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3589994138 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 84913487 ps |
| CPU time | 10.74 seconds |
| Started | Oct 03 06:25:18 AM UTC 24 |
| Finished | Oct 03 06:25:30 AM UTC 24 |
| Peak memory | 250588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589994138 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_mem _rw_with_rand_reset.3589994138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/17.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_rw.766676280 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 238117007 ps |
| CPU time | 8.44 seconds |
| Started | Oct 03 06:25:15 AM UTC 24 |
| Finished | Oct 03 06:25:24 AM UTC 24 |
| Peak memory | 248740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766676280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.766676280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/17.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_intr_test.825217184 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 9647413 ps |
| CPU time | 1.89 seconds |
| Started | Oct 03 06:25:10 AM UTC 24 |
| Finished | Oct 03 06:25:13 AM UTC 24 |
| Peak memory | 244876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825217184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.825217184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/17.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.722571133 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 3286636629 ps |
| CPU time | 35.63 seconds |
| Started | Oct 03 06:25:18 AM UTC 24 |
| Finished | Oct 03 06:25:55 AM UTC 24 |
| Peak memory | 258776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722571133 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_outstanding.722571133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/17.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1691688679 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 2648888268 ps |
| CPU time | 100.12 seconds |
| Started | Oct 03 06:25:02 AM UTC 24 |
| Finished | Oct 03 06:26:44 AM UTC 24 |
| Peak memory | 267296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691688679 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_errors.1691688679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2228650102 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 24860032945 ps |
| CPU time | 499.51 seconds |
| Started | Oct 03 06:25:00 AM UTC 24 |
| Finished | Oct 03 06:33:27 AM UTC 24 |
| Peak memory | 281900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228650102 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shad ow_reg_errors_with_csr_rw.2228650102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_errors.548924031 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 242714604 ps |
| CPU time | 14.25 seconds |
| Started | Oct 03 06:25:02 AM UTC 24 |
| Finished | Oct 03 06:25:17 AM UTC 24 |
| Peak memory | 264932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548924031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.548924031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/17.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1701971243 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 44732042 ps |
| CPU time | 4.93 seconds |
| Started | Oct 03 06:25:03 AM UTC 24 |
| Finished | Oct 03 06:25:09 AM UTC 24 |
| Peak memory | 248472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701971243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1701971243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/17.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.789334671 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 362999431 ps |
| CPU time | 20.78 seconds |
| Started | Oct 03 06:25:50 AM UTC 24 |
| Finished | Oct 03 06:26:12 AM UTC 24 |
| Peak memory | 267172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789334671 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_mem_ rw_with_rand_reset.789334671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/18.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.525561849 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 217961616 ps |
| CPU time | 12.89 seconds |
| Started | Oct 03 06:25:36 AM UTC 24 |
| Finished | Oct 03 06:25:50 AM UTC 24 |
| Peak memory | 248680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525561849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.525561849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/18.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.370336522 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 12340308 ps |
| CPU time | 2.36 seconds |
| Started | Oct 03 06:25:31 AM UTC 24 |
| Finished | Oct 03 06:25:35 AM UTC 24 |
| Peak memory | 248432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370336522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.370336522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/18.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.713989995 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 607145172 ps |
| CPU time | 32.53 seconds |
| Started | Oct 03 06:25:40 AM UTC 24 |
| Finished | Oct 03 06:26:14 AM UTC 24 |
| Peak memory | 250724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713989995 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_outstanding.713989995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/18.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3157678775 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 20043205775 ps |
| CPU time | 224 seconds |
| Started | Oct 03 06:25:29 AM UTC 24 |
| Finished | Oct 03 06:29:17 AM UTC 24 |
| Peak memory | 277536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157678775 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors.3157678775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4081569992 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 8893872602 ps |
| CPU time | 393.71 seconds |
| Started | Oct 03 06:25:26 AM UTC 24 |
| Finished | Oct 03 06:32:06 AM UTC 24 |
| Peak memory | 277536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081569992 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shad ow_reg_errors_with_csr_rw.4081569992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.1886907849 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 311383948 ps |
| CPU time | 35.9 seconds |
| Started | Oct 03 06:25:29 AM UTC 24 |
| Finished | Oct 03 06:26:06 AM UTC 24 |
| Peak memory | 267248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886907849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1886907849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/18.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3234633547 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 79485265 ps |
| CPU time | 8.71 seconds |
| Started | Oct 03 06:26:11 AM UTC 24 |
| Finished | Oct 03 06:26:21 AM UTC 24 |
| Peak memory | 250660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234633547 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_mem _rw_with_rand_reset.3234633547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/19.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.410403928 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 118406766 ps |
| CPU time | 5.14 seconds |
| Started | Oct 03 06:26:09 AM UTC 24 |
| Finished | Oct 03 06:26:16 AM UTC 24 |
| Peak memory | 248552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410403928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.410403928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/19.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.340888195 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 12275196 ps |
| CPU time | 2.69 seconds |
| Started | Oct 03 06:26:07 AM UTC 24 |
| Finished | Oct 03 06:26:11 AM UTC 24 |
| Peak memory | 248420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340888195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.340888195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/19.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2520290542 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 1024727457 ps |
| CPU time | 21.34 seconds |
| Started | Oct 03 06:26:10 AM UTC 24 |
| Finished | Oct 03 06:26:33 AM UTC 24 |
| Peak memory | 258716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520290542 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_outstanding.2520290542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/19.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3090658331 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 6471985081 ps |
| CPU time | 222.59 seconds |
| Started | Oct 03 06:25:55 AM UTC 24 |
| Finished | Oct 03 06:29:41 AM UTC 24 |
| Peak memory | 281836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090658331 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors.3090658331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.2308687908 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 135709241 ps |
| CPU time | 8.02 seconds |
| Started | Oct 03 06:25:57 AM UTC 24 |
| Finished | Oct 03 06:26:06 AM UTC 24 |
| Peak memory | 265140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308687908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2308687908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/19.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1174995546 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 1676244607 ps |
| CPU time | 164.11 seconds |
| Started | Oct 03 06:14:56 AM UTC 24 |
| Finished | Oct 03 06:17:43 AM UTC 24 |
| Peak memory | 250524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174995546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1174995546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.144410939 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 73988914 ps |
| CPU time | 5.86 seconds |
| Started | Oct 03 06:14:43 AM UTC 24 |
| Finished | Oct 03 06:14:49 AM UTC 24 |
| Peak memory | 250728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144410939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/al ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.144410939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2299782788 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 70812455 ps |
| CPU time | 16.11 seconds |
| Started | Oct 03 06:15:20 AM UTC 24 |
| Finished | Oct 03 06:15:37 AM UTC 24 |
| Peak memory | 260900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299782788 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_mem_ rw_with_rand_reset.2299782788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_rw.2531057577 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 54742149 ps |
| CPU time | 7.61 seconds |
| Started | Oct 03 06:14:47 AM UTC 24 |
| Finished | Oct 03 06:14:55 AM UTC 24 |
| Peak memory | 248476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531057577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2531057577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_intr_test.267431635 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 20300531 ps |
| CPU time | 2.32 seconds |
| Started | Oct 03 06:14:42 AM UTC 24 |
| Finished | Oct 03 06:14:46 AM UTC 24 |
| Peak memory | 248412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267431635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.267431635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3587550374 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 384774388 ps |
| CPU time | 41.58 seconds |
| Started | Oct 03 06:14:57 AM UTC 24 |
| Finished | Oct 03 06:15:40 AM UTC 24 |
| Peak memory | 258916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587550374 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outstanding.3587550374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3524743849 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 4075892921 ps |
| CPU time | 113.64 seconds |
| Started | Oct 03 06:14:24 AM UTC 24 |
| Finished | Oct 03 06:16:20 AM UTC 24 |
| Peak memory | 277612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524743849 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors.3524743849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3062809239 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 8905789510 ps |
| CPU time | 743.54 seconds |
| Started | Oct 03 06:14:16 AM UTC 24 |
| Finished | Oct 03 06:26:50 AM UTC 24 |
| Peak memory | 281636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062809239 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shado w_reg_errors_with_csr_rw.3062809239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_errors.2928200493 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 287233509 ps |
| CPU time | 30.77 seconds |
| Started | Oct 03 06:14:24 AM UTC 24 |
| Finished | Oct 03 06:14:56 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928200493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2928200493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.226423647 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 10807633 ps |
| CPU time | 2.22 seconds |
| Started | Oct 03 06:26:14 AM UTC 24 |
| Finished | Oct 03 06:26:17 AM UTC 24 |
| Peak memory | 248420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226423647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.226423647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/20.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.1905724278 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 8765922 ps |
| CPU time | 2.46 seconds |
| Started | Oct 03 06:26:15 AM UTC 24 |
| Finished | Oct 03 06:26:18 AM UTC 24 |
| Peak memory | 248500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905724278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1905724278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/21.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.924734030 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 26714243 ps |
| CPU time | 1.92 seconds |
| Started | Oct 03 06:26:15 AM UTC 24 |
| Finished | Oct 03 06:26:18 AM UTC 24 |
| Peak memory | 246796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924734030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.924734030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/22.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.3362665873 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 9723191 ps |
| CPU time | 2.29 seconds |
| Started | Oct 03 06:26:17 AM UTC 24 |
| Finished | Oct 03 06:26:20 AM UTC 24 |
| Peak memory | 246380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362665873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.3362665873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/23.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.973994935 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 6833250 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 06:26:19 AM UTC 24 |
| Finished | Oct 03 06:26:21 AM UTC 24 |
| Peak memory | 246864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973994935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.973994935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/24.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.4230359681 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 6180203 ps |
| CPU time | 2.18 seconds |
| Started | Oct 03 06:26:19 AM UTC 24 |
| Finished | Oct 03 06:26:22 AM UTC 24 |
| Peak memory | 248424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230359681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.4230359681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/25.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.1336831465 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 26272804 ps |
| CPU time | 2.5 seconds |
| Started | Oct 03 06:26:22 AM UTC 24 |
| Finished | Oct 03 06:26:26 AM UTC 24 |
| Peak memory | 248688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336831465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1336831465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/26.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.388212264 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 12504483 ps |
| CPU time | 2.1 seconds |
| Started | Oct 03 06:26:22 AM UTC 24 |
| Finished | Oct 03 06:26:25 AM UTC 24 |
| Peak memory | 248688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388212264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.388212264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/27.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.2024681561 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 7116867 ps |
| CPU time | 2.07 seconds |
| Started | Oct 03 06:26:23 AM UTC 24 |
| Finished | Oct 03 06:26:27 AM UTC 24 |
| Peak memory | 246576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024681561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2024681561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/28.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.4105560816 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 26171510 ps |
| CPU time | 2.07 seconds |
| Started | Oct 03 06:26:23 AM UTC 24 |
| Finished | Oct 03 06:26:27 AM UTC 24 |
| Peak memory | 248560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105560816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.4105560816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/29.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_aliasing.4037481020 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 550220388 ps |
| CPU time | 73.36 seconds |
| Started | Oct 03 06:16:54 AM UTC 24 |
| Finished | Oct 03 06:18:09 AM UTC 24 |
| Peak memory | 250724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037481020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.4037481020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3665857249 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 4469162069 ps |
| CPU time | 352.16 seconds |
| Started | Oct 03 06:16:53 AM UTC 24 |
| Finished | Oct 03 06:22:51 AM UTC 24 |
| Peak memory | 250788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665857249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3665857249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2180759726 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 101656468 ps |
| CPU time | 13.97 seconds |
| Started | Oct 03 06:16:37 AM UTC 24 |
| Finished | Oct 03 06:16:52 AM UTC 24 |
| Peak memory | 250724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180759726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2180759726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.413062159 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 155099086 ps |
| CPU time | 20.74 seconds |
| Started | Oct 03 06:17:04 AM UTC 24 |
| Finished | Oct 03 06:17:26 AM UTC 24 |
| Peak memory | 262876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413062159 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_mem_r w_with_rand_reset.413062159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_rw.3973752659 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 125190564 ps |
| CPU time | 9.49 seconds |
| Started | Oct 03 06:16:53 AM UTC 24 |
| Finished | Oct 03 06:17:03 AM UTC 24 |
| Peak memory | 248476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973752659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3973752659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_intr_test.723759849 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 12935692 ps |
| CPU time | 2.17 seconds |
| Started | Oct 03 06:16:32 AM UTC 24 |
| Finished | Oct 03 06:16:36 AM UTC 24 |
| Peak memory | 248404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723759849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.723759849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2508758327 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 533475170 ps |
| CPU time | 39.75 seconds |
| Started | Oct 03 06:16:58 AM UTC 24 |
| Finished | Oct 03 06:17:40 AM UTC 24 |
| Peak memory | 258716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508758327 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outstanding.2508758327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3700185192 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 1888032851 ps |
| CPU time | 154.87 seconds |
| Started | Oct 03 06:15:41 AM UTC 24 |
| Finished | Oct 03 06:18:19 AM UTC 24 |
| Peak memory | 267240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700185192 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_errors.3700185192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.4040446634 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 8606095164 ps |
| CPU time | 797.7 seconds |
| Started | Oct 03 06:15:38 AM UTC 24 |
| Finished | Oct 03 06:29:07 AM UTC 24 |
| Peak memory | 277804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040446634 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shado w_reg_errors_with_csr_rw.4040446634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_errors.2704424573 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 446669642 ps |
| CPU time | 31.15 seconds |
| Started | Oct 03 06:16:21 AM UTC 24 |
| Finished | Oct 03 06:16:54 AM UTC 24 |
| Peak memory | 260912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704424573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2704424573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.1849369315 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 14775573 ps |
| CPU time | 1.52 seconds |
| Started | Oct 03 06:26:24 AM UTC 24 |
| Finished | Oct 03 06:26:26 AM UTC 24 |
| Peak memory | 246864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849369315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1849369315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/30.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.2823171172 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 15313985 ps |
| CPU time | 2.09 seconds |
| Started | Oct 03 06:26:24 AM UTC 24 |
| Finished | Oct 03 06:26:27 AM UTC 24 |
| Peak memory | 248264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823171172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2823171172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/31.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.1125403725 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 16185447 ps |
| CPU time | 2 seconds |
| Started | Oct 03 06:26:24 AM UTC 24 |
| Finished | Oct 03 06:26:27 AM UTC 24 |
| Peak memory | 246476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125403725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1125403725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/32.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.1293907849 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 18312069 ps |
| CPU time | 2.23 seconds |
| Started | Oct 03 06:26:25 AM UTC 24 |
| Finished | Oct 03 06:26:28 AM UTC 24 |
| Peak memory | 246436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293907849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1293907849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/33.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.513652725 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 17536105 ps |
| CPU time | 2.23 seconds |
| Started | Oct 03 06:26:26 AM UTC 24 |
| Finished | Oct 03 06:26:30 AM UTC 24 |
| Peak memory | 248688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513652725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.513652725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/34.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.293134479 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 9744829 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 06:26:28 AM UTC 24 |
| Finished | Oct 03 06:26:31 AM UTC 24 |
| Peak memory | 244876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293134479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.293134479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/35.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.3795696415 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 28821897 ps |
| CPU time | 3.46 seconds |
| Started | Oct 03 06:26:28 AM UTC 24 |
| Finished | Oct 03 06:26:33 AM UTC 24 |
| Peak memory | 246576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795696415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3795696415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/36.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.718706588 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 9920297 ps |
| CPU time | 2.2 seconds |
| Started | Oct 03 06:26:28 AM UTC 24 |
| Finished | Oct 03 06:26:31 AM UTC 24 |
| Peak memory | 248624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718706588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.718706588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/37.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.4232404331 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 6099253 ps |
| CPU time | 2.3 seconds |
| Started | Oct 03 06:26:28 AM UTC 24 |
| Finished | Oct 03 06:26:32 AM UTC 24 |
| Peak memory | 248612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232404331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.4232404331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/38.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.1538493645 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 9741700 ps |
| CPU time | 2.38 seconds |
| Started | Oct 03 06:26:28 AM UTC 24 |
| Finished | Oct 03 06:26:32 AM UTC 24 |
| Peak memory | 248500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538493645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1538493645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/39.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_aliasing.997161058 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 9573656262 ps |
| CPU time | 390.15 seconds |
| Started | Oct 03 06:17:44 AM UTC 24 |
| Finished | Oct 03 06:24:20 AM UTC 24 |
| Peak memory | 250592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997161058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/al ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.997161058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2468875888 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 30827232297 ps |
| CPU time | 433.1 seconds |
| Started | Oct 03 06:17:41 AM UTC 24 |
| Finished | Oct 03 06:25:00 AM UTC 24 |
| Peak memory | 248616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468875888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2468875888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1016092732 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 754487326 ps |
| CPU time | 17.65 seconds |
| Started | Oct 03 06:17:37 AM UTC 24 |
| Finished | Oct 03 06:17:55 AM UTC 24 |
| Peak memory | 260764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016092732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1016092732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3487603089 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 128425278 ps |
| CPU time | 12.76 seconds |
| Started | Oct 03 06:17:56 AM UTC 24 |
| Finished | Oct 03 06:18:11 AM UTC 24 |
| Peak memory | 264996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487603089 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_mem_ rw_with_rand_reset.3487603089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_rw.2884458999 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 66457390 ps |
| CPU time | 5.34 seconds |
| Started | Oct 03 06:17:39 AM UTC 24 |
| Finished | Oct 03 06:17:45 AM UTC 24 |
| Peak memory | 250592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884458999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2884458999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_intr_test.948578567 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 12320776 ps |
| CPU time | 2.26 seconds |
| Started | Oct 03 06:17:34 AM UTC 24 |
| Finished | Oct 03 06:17:38 AM UTC 24 |
| Peak memory | 248484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948578567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.948578567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.492182834 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 1234781597 ps |
| CPU time | 33.76 seconds |
| Started | Oct 03 06:17:46 AM UTC 24 |
| Finished | Oct 03 06:18:21 AM UTC 24 |
| Peak memory | 260760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492182834 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outstanding.492182834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3935202094 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 7405197796 ps |
| CPU time | 542.14 seconds |
| Started | Oct 03 06:17:21 AM UTC 24 |
| Finished | Oct 03 06:26:30 AM UTC 24 |
| Peak memory | 277612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935202094 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shado w_reg_errors_with_csr_rw.3935202094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_errors.4258703041 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 37346625 ps |
| CPU time | 5.42 seconds |
| Started | Oct 03 06:17:27 AM UTC 24 |
| Finished | Oct 03 06:17:34 AM UTC 24 |
| Peak memory | 261040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258703041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.4258703041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.3601163536 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 19552886 ps |
| CPU time | 2.32 seconds |
| Started | Oct 03 06:26:28 AM UTC 24 |
| Finished | Oct 03 06:26:32 AM UTC 24 |
| Peak memory | 248412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601163536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3601163536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/40.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.1159388885 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 7516686 ps |
| CPU time | 2.35 seconds |
| Started | Oct 03 06:26:30 AM UTC 24 |
| Finished | Oct 03 06:26:33 AM UTC 24 |
| Peak memory | 248688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159388885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1159388885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/41.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.3152665155 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 9887111 ps |
| CPU time | 1.99 seconds |
| Started | Oct 03 06:26:32 AM UTC 24 |
| Finished | Oct 03 06:26:35 AM UTC 24 |
| Peak memory | 246864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152665155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3152665155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/42.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.3992961638 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 15019963 ps |
| CPU time | 2.4 seconds |
| Started | Oct 03 06:26:32 AM UTC 24 |
| Finished | Oct 03 06:26:35 AM UTC 24 |
| Peak memory | 248496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992961638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3992961638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/43.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.3802861922 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 58317644 ps |
| CPU time | 2.15 seconds |
| Started | Oct 03 06:26:32 AM UTC 24 |
| Finished | Oct 03 06:26:35 AM UTC 24 |
| Peak memory | 248420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802861922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3802861922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/44.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.2830394432 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 11495186 ps |
| CPU time | 1.98 seconds |
| Started | Oct 03 06:26:33 AM UTC 24 |
| Finished | Oct 03 06:26:36 AM UTC 24 |
| Peak memory | 246796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830394432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2830394432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/45.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.3755878240 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 7261789 ps |
| CPU time | 2.05 seconds |
| Started | Oct 03 06:26:33 AM UTC 24 |
| Finished | Oct 03 06:26:36 AM UTC 24 |
| Peak memory | 248608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755878240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3755878240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/46.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.1185107502 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 8331602 ps |
| CPU time | 2.36 seconds |
| Started | Oct 03 06:26:33 AM UTC 24 |
| Finished | Oct 03 06:26:37 AM UTC 24 |
| Peak memory | 248624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185107502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1185107502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/47.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.3396776465 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 18375757 ps |
| CPU time | 2.96 seconds |
| Started | Oct 03 06:26:34 AM UTC 24 |
| Finished | Oct 03 06:26:37 AM UTC 24 |
| Peak memory | 248420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396776465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3396776465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/48.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.4130880351 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 17058275 ps |
| CPU time | 3.08 seconds |
| Started | Oct 03 06:26:34 AM UTC 24 |
| Finished | Oct 03 06:26:38 AM UTC 24 |
| Peak memory | 248688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130880351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.4130880351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/49.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3866925369 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 382195996 ps |
| CPU time | 12.19 seconds |
| Started | Oct 03 06:18:26 AM UTC 24 |
| Finished | Oct 03 06:18:40 AM UTC 24 |
| Peak memory | 250588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866925369 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_mem_ rw_with_rand_reset.3866925369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/5.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_rw.99155323 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 66866057 ps |
| CPU time | 8.62 seconds |
| Started | Oct 03 06:18:24 AM UTC 24 |
| Finished | Oct 03 06:18:34 AM UTC 24 |
| Peak memory | 248676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99155323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_han dler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.99155323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/5.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_intr_test.1922585448 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 10098031 ps |
| CPU time | 2.23 seconds |
| Started | Oct 03 06:18:22 AM UTC 24 |
| Finished | Oct 03 06:18:25 AM UTC 24 |
| Peak memory | 248488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922585448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1922585448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/5.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1425588361 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 275628043 ps |
| CPU time | 20.41 seconds |
| Started | Oct 03 06:18:26 AM UTC 24 |
| Finished | Oct 03 06:18:48 AM UTC 24 |
| Peak memory | 258716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425588361 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outstanding.1425588361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/5.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1638328406 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 7381895220 ps |
| CPU time | 323.81 seconds |
| Started | Oct 03 06:18:11 AM UTC 24 |
| Finished | Oct 03 06:23:40 AM UTC 24 |
| Peak memory | 277804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638328406 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors.1638328406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_errors.2954376043 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 182613080 ps |
| CPU time | 10.24 seconds |
| Started | Oct 03 06:18:12 AM UTC 24 |
| Finished | Oct 03 06:18:23 AM UTC 24 |
| Peak memory | 261040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954376043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2954376043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/5.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3544999655 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 602276718 ps |
| CPU time | 19.4 seconds |
| Started | Oct 03 06:19:07 AM UTC 24 |
| Finished | Oct 03 06:19:27 AM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544999655 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_mem_ rw_with_rand_reset.3544999655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/6.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_rw.2377022988 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 121791168 ps |
| CPU time | 7.17 seconds |
| Started | Oct 03 06:18:55 AM UTC 24 |
| Finished | Oct 03 06:19:03 AM UTC 24 |
| Peak memory | 250520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377022988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2377022988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/6.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1946503064 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 332286552 ps |
| CPU time | 41.7 seconds |
| Started | Oct 03 06:18:59 AM UTC 24 |
| Finished | Oct 03 06:19:42 AM UTC 24 |
| Peak memory | 260772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946503064 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outstanding.1946503064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/6.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3914401104 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 2550833680 ps |
| CPU time | 272.76 seconds |
| Started | Oct 03 06:18:35 AM UTC 24 |
| Finished | Oct 03 06:23:12 AM UTC 24 |
| Peak memory | 281836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914401104 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors.3914401104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_errors.713778542 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 66744710 ps |
| CPU time | 8.62 seconds |
| Started | Oct 03 06:18:41 AM UTC 24 |
| Finished | Oct 03 06:18:50 AM UTC 24 |
| Peak memory | 260964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713778542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.713778542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/6.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.4145143662 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 60224787 ps |
| CPU time | 8.65 seconds |
| Started | Oct 03 06:19:43 AM UTC 24 |
| Finished | Oct 03 06:19:53 AM UTC 24 |
| Peak memory | 261028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145143662 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_mem_ rw_with_rand_reset.4145143662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/7.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_rw.905918966 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 492854203 ps |
| CPU time | 14.75 seconds |
| Started | Oct 03 06:19:33 AM UTC 24 |
| Finished | Oct 03 06:19:49 AM UTC 24 |
| Peak memory | 248544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905918966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.905918966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/7.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_intr_test.3819984188 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 10595398 ps |
| CPU time | 2.55 seconds |
| Started | Oct 03 06:19:29 AM UTC 24 |
| Finished | Oct 03 06:19:32 AM UTC 24 |
| Peak memory | 248496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819984188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3819984188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/7.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.933885637 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 341967546 ps |
| CPU time | 40.04 seconds |
| Started | Oct 03 06:19:37 AM UTC 24 |
| Finished | Oct 03 06:20:19 AM UTC 24 |
| Peak memory | 258712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933885637 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outstanding.933885637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/7.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1410182996 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 2756069423 ps |
| CPU time | 305.57 seconds |
| Started | Oct 03 06:19:07 AM UTC 24 |
| Finished | Oct 03 06:24:17 AM UTC 24 |
| Peak memory | 277536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410182996 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors.1410182996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2802009879 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 78673994411 ps |
| CPU time | 1024.45 seconds |
| Started | Oct 03 06:19:07 AM UTC 24 |
| Finished | Oct 03 06:36:24 AM UTC 24 |
| Peak memory | 283672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802009879 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shado w_reg_errors_with_csr_rw.2802009879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_errors.2505196260 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 1149027919 ps |
| CPU time | 33.58 seconds |
| Started | Oct 03 06:19:17 AM UTC 24 |
| Finished | Oct 03 06:19:53 AM UTC 24 |
| Peak memory | 260840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505196260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2505196260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/7.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.962337700 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 377805981 ps |
| CPU time | 10.46 seconds |
| Started | Oct 03 06:20:15 AM UTC 24 |
| Finished | Oct 03 06:20:27 AM UTC 24 |
| Peak memory | 250852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962337700 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_mem_r w_with_rand_reset.962337700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/8.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_rw.3479624197 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 34639938 ps |
| CPU time | 4.81 seconds |
| Started | Oct 03 06:20:11 AM UTC 24 |
| Finished | Oct 03 06:20:17 AM UTC 24 |
| Peak memory | 248676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479624197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3479624197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/8.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_intr_test.542501384 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 16014199 ps |
| CPU time | 2.67 seconds |
| Started | Oct 03 06:20:08 AM UTC 24 |
| Finished | Oct 03 06:20:12 AM UTC 24 |
| Peak memory | 248480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542501384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.542501384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/8.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.50062671 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 2261195254 ps |
| CPU time | 33.98 seconds |
| Started | Oct 03 06:20:13 AM UTC 24 |
| Finished | Oct 03 06:20:49 AM UTC 24 |
| Peak memory | 259040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50062671 -assert nopostproc +UVM_TESTNAME=alert_handler _base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outstanding.50062671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/8.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_errors.2467455485 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 1325479032 ps |
| CPU time | 18.96 seconds |
| Started | Oct 03 06:19:54 AM UTC 24 |
| Finished | Oct 03 06:20:14 AM UTC 24 |
| Peak memory | 261108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467455485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2467455485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/8.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2952498301 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 180133383 ps |
| CPU time | 10.69 seconds |
| Started | Oct 03 06:20:47 AM UTC 24 |
| Finished | Oct 03 06:20:59 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952498301 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_mem_ rw_with_rand_reset.2952498301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/9.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_rw.311183954 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 34109095 ps |
| CPU time | 9.05 seconds |
| Started | Oct 03 06:20:36 AM UTC 24 |
| Finished | Oct 03 06:20:46 AM UTC 24 |
| Peak memory | 250524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311183954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.311183954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/9.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_intr_test.489297879 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 9577140 ps |
| CPU time | 2.41 seconds |
| Started | Oct 03 06:20:31 AM UTC 24 |
| Finished | Oct 03 06:20:35 AM UTC 24 |
| Peak memory | 248608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489297879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.489297879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/9.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3145228322 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 258803337 ps |
| CPU time | 32.9 seconds |
| Started | Oct 03 06:20:38 AM UTC 24 |
| Finished | Oct 03 06:21:12 AM UTC 24 |
| Peak memory | 250788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145228322 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outstanding.3145228322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/9.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_errors.2207254206 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 245920403 ps |
| CPU time | 26.83 seconds |
| Started | Oct 03 06:20:28 AM UTC 24 |
| Finished | Oct 03 06:20:56 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207254206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.2207254206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/9.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy.3600974556 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 91847600026 ps |
| CPU time | 1622.09 seconds |
| Started | Oct 03 04:37:10 AM UTC 24 |
| Finished | Oct 03 05:04:31 AM UTC 24 |
| Peak memory | 285668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600974556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3600974556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_alert_accum.2735719951 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1908684638 ps |
| CPU time | 116.07 seconds |
| Started | Oct 03 04:37:10 AM UTC 24 |
| Finished | Oct 03 04:39:08 AM UTC 24 |
| Peak memory | 266572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735719951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2735719951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_intr_timeout.3164651731 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 65085274 ps |
| CPU time | 2.82 seconds |
| Started | Oct 03 04:37:10 AM UTC 24 |
| Finished | Oct 03 04:37:13 AM UTC 24 |
| Peak memory | 250260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164651731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3164651731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg.4106611006 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 69378555569 ps |
| CPU time | 1558.48 seconds |
| Started | Oct 03 04:37:10 AM UTC 24 |
| Finished | Oct 03 05:03:29 AM UTC 24 |
| Peak memory | 285740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106611006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.4106611006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg_stub_clk.426931776 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 47477235368 ps |
| CPU time | 2075.29 seconds |
| Started | Oct 03 04:37:10 AM UTC 24 |
| Finished | Oct 03 05:12:12 AM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426931776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.426931776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_alerts.1476191293 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 177594538 ps |
| CPU time | 5.46 seconds |
| Started | Oct 03 04:37:09 AM UTC 24 |
| Finished | Oct 03 04:37:16 AM UTC 24 |
| Peak memory | 260500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476191293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1476191293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/0.alert_handler_smoke.2377945138 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1682436527 ps |
| CPU time | 26.51 seconds |
| Started | Oct 03 04:37:09 AM UTC 24 |
| Finished | Oct 03 04:37:37 AM UTC 24 |
| Peak memory | 260500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377945138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2377945138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/0.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy.3157495013 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 82391245916 ps |
| CPU time | 2019.28 seconds |
| Started | Oct 03 04:37:14 AM UTC 24 |
| Finished | Oct 03 05:11:19 AM UTC 24 |
| Peak memory | 302052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157495013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3157495013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy_stress.882408250 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 476575023 ps |
| CPU time | 8.87 seconds |
| Started | Oct 03 04:37:14 AM UTC 24 |
| Finished | Oct 03 04:37:24 AM UTC 24 |
| Peak memory | 260432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882408250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.882408250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_alert_accum.701729109 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3280037801 ps |
| CPU time | 78.41 seconds |
| Started | Oct 03 04:37:12 AM UTC 24 |
| Finished | Oct 03 04:38:32 AM UTC 24 |
| Peak memory | 266636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701729109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.701729109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_intr_timeout.3422975244 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 189783339 ps |
| CPU time | 16.26 seconds |
| Started | Oct 03 04:37:12 AM UTC 24 |
| Finished | Oct 03 04:37:29 AM UTC 24 |
| Peak memory | 266652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422975244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3422975244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg_stub_clk.747978244 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 31237836825 ps |
| CPU time | 2005.73 seconds |
| Started | Oct 03 04:37:14 AM UTC 24 |
| Finished | Oct 03 05:11:05 AM UTC 24 |
| Peak memory | 285740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747978244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.747978244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_alerts.3631486153 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 959542281 ps |
| CPU time | 37.93 seconds |
| Started | Oct 03 04:37:11 AM UTC 24 |
| Finished | Oct 03 04:37:51 AM UTC 24 |
| Peak memory | 266168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631486153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.3631486153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_classes.139651723 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 2330604233 ps |
| CPU time | 58.15 seconds |
| Started | Oct 03 04:37:11 AM UTC 24 |
| Finished | Oct 03 04:38:11 AM UTC 24 |
| Peak memory | 260564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139651723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.139651723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/1.alert_handler_sec_cm.2997543378 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 374226950 ps |
| CPU time | 18.61 seconds |
| Started | Oct 03 04:37:18 AM UTC 24 |
| Finished | Oct 03 04:37:38 AM UTC 24 |
| Peak memory | 292884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997543378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2997543378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/1.alert_handler_smoke.2021670839 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 2303546123 ps |
| CPU time | 42.4 seconds |
| Started | Oct 03 04:37:11 AM UTC 24 |
| Finished | Oct 03 04:37:55 AM UTC 24 |
| Peak memory | 266708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021670839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2021670839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all.1116351426 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 174797024485 ps |
| CPU time | 2696.56 seconds |
| Started | Oct 03 04:37:14 AM UTC 24 |
| Finished | Oct 03 05:22:44 AM UTC 24 |
| Peak memory | 300068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116351426 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_stress_all.1116351426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/1.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/10.alert_handler_alert_accum_saturation.2791290605 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 45842227 ps |
| CPU time | 3.98 seconds |
| Started | Oct 03 04:44:25 AM UTC 24 |
| Finished | Oct 03 04:44:30 AM UTC 24 |
| Peak memory | 260700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791290605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2791290605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/10.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy_stress.3045824696 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 204259876 ps |
| CPU time | 14.62 seconds |
| Started | Oct 03 04:44:09 AM UTC 24 |
| Finished | Oct 03 04:44:25 AM UTC 24 |
| Peak memory | 260516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045824696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3045824696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/10.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_alert_accum.2163844532 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 214735634 ps |
| CPU time | 19.03 seconds |
| Started | Oct 03 04:43:47 AM UTC 24 |
| Finished | Oct 03 04:44:08 AM UTC 24 |
| Peak memory | 264520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163844532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2163844532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/10.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_intr_timeout.497140144 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 3831235127 ps |
| CPU time | 71.6 seconds |
| Started | Oct 03 04:43:47 AM UTC 24 |
| Finished | Oct 03 04:45:01 AM UTC 24 |
| Peak memory | 266744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497140144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.497140144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/10.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg_stub_clk.1793682239 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 29126325769 ps |
| CPU time | 1765.58 seconds |
| Started | Oct 03 04:44:09 AM UTC 24 |
| Finished | Oct 03 05:13:56 AM UTC 24 |
| Peak memory | 283100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793682239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1793682239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/10.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_alerts.1861218450 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 901371663 ps |
| CPU time | 63.1 seconds |
| Started | Oct 03 04:43:34 AM UTC 24 |
| Finished | Oct 03 04:44:39 AM UTC 24 |
| Peak memory | 266612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861218450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1861218450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/10.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_classes.3049388157 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1905371304 ps |
| CPU time | 55.38 seconds |
| Started | Oct 03 04:43:37 AM UTC 24 |
| Finished | Oct 03 04:44:35 AM UTC 24 |
| Peak memory | 266596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049388157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3049388157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/10.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/10.alert_handler_sig_int_fail.3601106626 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 222281774 ps |
| CPU time | 5.03 seconds |
| Started | Oct 03 04:43:48 AM UTC 24 |
| Finished | Oct 03 04:43:55 AM UTC 24 |
| Peak memory | 260436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601106626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3601106626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/10.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/10.alert_handler_smoke.57670946 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 83475641 ps |
| CPU time | 12.84 seconds |
| Started | Oct 03 04:43:32 AM UTC 24 |
| Finished | Oct 03 04:43:46 AM UTC 24 |
| Peak memory | 260508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57670946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smo ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.57670946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/10.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/10.alert_handler_stress_all.397100288 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 188237778822 ps |
| CPU time | 3285.68 seconds |
| Started | Oct 03 04:44:17 AM UTC 24 |
| Finished | Oct 03 05:39:41 AM UTC 24 |
| Peak memory | 302044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397100288 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_stress_all.397100288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/10.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy.2184978406 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 5336218484 ps |
| CPU time | 820.88 seconds |
| Started | Oct 03 04:45:01 AM UTC 24 |
| Finished | Oct 03 04:58:54 AM UTC 24 |
| Peak memory | 283356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184978406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2184978406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/11.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy_stress.918432365 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 757771720 ps |
| CPU time | 53.23 seconds |
| Started | Oct 03 04:45:24 AM UTC 24 |
| Finished | Oct 03 04:46:19 AM UTC 24 |
| Peak memory | 260444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918432365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.918432365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/11.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_alert_accum.2889422135 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 637189791 ps |
| CPU time | 42.24 seconds |
| Started | Oct 03 04:44:55 AM UTC 24 |
| Finished | Oct 03 04:45:39 AM UTC 24 |
| Peak memory | 266568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889422135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2889422135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/11.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_intr_timeout.3751601912 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 334842641 ps |
| CPU time | 7.1 seconds |
| Started | Oct 03 04:44:48 AM UTC 24 |
| Finished | Oct 03 04:44:56 AM UTC 24 |
| Peak memory | 250456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751601912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3751601912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/11.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg.1851294560 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 36888425492 ps |
| CPU time | 2531.23 seconds |
| Started | Oct 03 04:45:08 AM UTC 24 |
| Finished | Oct 03 05:27:49 AM UTC 24 |
| Peak memory | 302124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851294560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1851294560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/11.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg_stub_clk.1317221707 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 19388281790 ps |
| CPU time | 1436.86 seconds |
| Started | Oct 03 04:45:19 AM UTC 24 |
| Finished | Oct 03 05:09:33 AM UTC 24 |
| Peak memory | 277220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317221707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1317221707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/11.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/11.alert_handler_ping_timeout.2915721824 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 13719240317 ps |
| CPU time | 357.88 seconds |
| Started | Oct 03 04:45:02 AM UTC 24 |
| Finished | Oct 03 04:51:04 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915721824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2915721824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_alerts.641367594 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 560459928 ps |
| CPU time | 23.89 seconds |
| Started | Oct 03 04:44:36 AM UTC 24 |
| Finished | Oct 03 04:45:01 AM UTC 24 |
| Peak memory | 266580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641367594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.641367594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/11.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_classes.2624495025 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1914107200 ps |
| CPU time | 41.51 seconds |
| Started | Oct 03 04:44:40 AM UTC 24 |
| Finished | Oct 03 04:45:23 AM UTC 24 |
| Peak memory | 260532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624495025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2624495025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/11.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/11.alert_handler_sig_int_fail.539110711 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 252647741 ps |
| CPU time | 8.5 seconds |
| Started | Oct 03 04:44:57 AM UTC 24 |
| Finished | Oct 03 04:45:07 AM UTC 24 |
| Peak memory | 250220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539110711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.539110711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/11.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/11.alert_handler_smoke.3304008040 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 111372926 ps |
| CPU time | 19.71 seconds |
| Started | Oct 03 04:44:33 AM UTC 24 |
| Finished | Oct 03 04:44:54 AM UTC 24 |
| Peak memory | 260440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304008040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3304008040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/11.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all.164607591 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 4125440285 ps |
| CPU time | 121.71 seconds |
| Started | Oct 03 04:45:31 AM UTC 24 |
| Finished | Oct 03 04:47:35 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164607591 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_stress_all.164607591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/11.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/12.alert_handler_alert_accum_saturation.1954703463 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 72696223 ps |
| CPU time | 5.18 seconds |
| Started | Oct 03 04:47:23 AM UTC 24 |
| Finished | Oct 03 04:47:30 AM UTC 24 |
| Peak memory | 260776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954703463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1954703463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/12.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy.757813625 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 67602684225 ps |
| CPU time | 1071.4 seconds |
| Started | Oct 03 04:46:40 AM UTC 24 |
| Finished | Oct 03 05:04:46 AM UTC 24 |
| Peak memory | 283092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757813625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.757813625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/12.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy_stress.4112305467 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 527266872 ps |
| CPU time | 24.74 seconds |
| Started | Oct 03 04:46:56 AM UTC 24 |
| Finished | Oct 03 04:47:22 AM UTC 24 |
| Peak memory | 260708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112305467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.4112305467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/12.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_alert_accum.393838467 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 863528821 ps |
| CPU time | 42.48 seconds |
| Started | Oct 03 04:45:59 AM UTC 24 |
| Finished | Oct 03 04:46:43 AM UTC 24 |
| Peak memory | 266676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393838467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.393838467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/12.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_intr_timeout.3249344026 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 311950307 ps |
| CPU time | 45.18 seconds |
| Started | Oct 03 04:45:59 AM UTC 24 |
| Finished | Oct 03 04:46:46 AM UTC 24 |
| Peak memory | 266576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249344026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3249344026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/12.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg_stub_clk.2670181077 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 39820618604 ps |
| CPU time | 2539.13 seconds |
| Started | Oct 03 04:46:54 AM UTC 24 |
| Finished | Oct 03 05:29:44 AM UTC 24 |
| Peak memory | 302324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670181077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2670181077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/12.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_alerts.614789635 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 114212188 ps |
| CPU time | 11.81 seconds |
| Started | Oct 03 04:45:45 AM UTC 24 |
| Finished | Oct 03 04:45:58 AM UTC 24 |
| Peak memory | 260504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614789635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.614789635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/12.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/12.alert_handler_sig_int_fail.2421112771 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 229556286 ps |
| CPU time | 33 seconds |
| Started | Oct 03 04:46:20 AM UTC 24 |
| Finished | Oct 03 04:46:55 AM UTC 24 |
| Peak memory | 260428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421112771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2421112771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/12.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/12.alert_handler_smoke.1492091961 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 234202360 ps |
| CPU time | 12.65 seconds |
| Started | Oct 03 04:45:44 AM UTC 24 |
| Finished | Oct 03 04:45:58 AM UTC 24 |
| Peak memory | 262560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492091961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1492091961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/12.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/13.alert_handler_alert_accum_saturation.3043929256 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 14208993 ps |
| CPU time | 4.38 seconds |
| Started | Oct 03 04:50:15 AM UTC 24 |
| Finished | Oct 03 04:50:20 AM UTC 24 |
| Peak memory | 260776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043929256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3043929256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/13.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy.2560446904 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 24214925986 ps |
| CPU time | 945.94 seconds |
| Started | Oct 03 04:49:05 AM UTC 24 |
| Finished | Oct 03 05:05:04 AM UTC 24 |
| Peak memory | 283164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560446904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2560446904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/13.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy_stress.241739377 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 1746978418 ps |
| CPU time | 22.42 seconds |
| Started | Oct 03 04:49:51 AM UTC 24 |
| Finished | Oct 03 04:50:15 AM UTC 24 |
| Peak memory | 260708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241739377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.241739377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/13.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_alert_accum.3038625152 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 5133134321 ps |
| CPU time | 195.01 seconds |
| Started | Oct 03 04:48:13 AM UTC 24 |
| Finished | Oct 03 04:51:31 AM UTC 24 |
| Peak memory | 267028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038625152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3038625152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/13.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_intr_timeout.3276321142 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 7464496178 ps |
| CPU time | 53.83 seconds |
| Started | Oct 03 04:47:51 AM UTC 24 |
| Finished | Oct 03 04:48:46 AM UTC 24 |
| Peak memory | 260888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276321142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3276321142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/13.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg_stub_clk.156181387 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 89628322531 ps |
| CPU time | 1263.61 seconds |
| Started | Oct 03 04:49:43 AM UTC 24 |
| Finished | Oct 03 05:11:04 AM UTC 24 |
| Peak memory | 299480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156181387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.156181387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/13.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/13.alert_handler_ping_timeout.1491261049 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 6212333121 ps |
| CPU time | 200.54 seconds |
| Started | Oct 03 04:49:12 AM UTC 24 |
| Finished | Oct 03 04:52:36 AM UTC 24 |
| Peak memory | 260772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491261049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1491261049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/13.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_alerts.466211973 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 555276570 ps |
| CPU time | 34.41 seconds |
| Started | Oct 03 04:47:36 AM UTC 24 |
| Finished | Oct 03 04:48:12 AM UTC 24 |
| Peak memory | 260428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466211973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.466211973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/13.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_classes.1682297575 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 687434797 ps |
| CPU time | 77.05 seconds |
| Started | Oct 03 04:47:45 AM UTC 24 |
| Finished | Oct 03 04:49:04 AM UTC 24 |
| Peak memory | 260428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682297575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1682297575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/13.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/13.alert_handler_sig_int_fail.1470002066 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 3314416027 ps |
| CPU time | 43.62 seconds |
| Started | Oct 03 04:48:47 AM UTC 24 |
| Finished | Oct 03 04:49:32 AM UTC 24 |
| Peak memory | 260564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470002066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1470002066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/13.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/13.alert_handler_smoke.2533935208 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 164665210 ps |
| CPU time | 18.69 seconds |
| Started | Oct 03 04:47:30 AM UTC 24 |
| Finished | Oct 03 04:47:50 AM UTC 24 |
| Peak memory | 260512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533935208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2533935208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/13.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all.3636915582 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 52851814715 ps |
| CPU time | 1879.76 seconds |
| Started | Oct 03 04:50:08 AM UTC 24 |
| Finished | Oct 03 05:21:51 AM UTC 24 |
| Peak memory | 293328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636915582 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_stress_all.3636915582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/13.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all_with_rand_reset.1124533029 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1921555024 ps |
| CPU time | 270.44 seconds |
| Started | Oct 03 04:50:16 AM UTC 24 |
| Finished | Oct 03 04:54:51 AM UTC 24 |
| Peak memory | 277144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1124533029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.a lert_handler_stress_all_with_rand_reset.1124533029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/13.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/14.alert_handler_alert_accum_saturation.1824241567 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 246833494 ps |
| CPU time | 8.03 seconds |
| Started | Oct 03 04:52:19 AM UTC 24 |
| Finished | Oct 03 04:52:28 AM UTC 24 |
| Peak memory | 260776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824241567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1824241567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/14.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy.2008822194 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 10698527629 ps |
| CPU time | 822.99 seconds |
| Started | Oct 03 04:51:32 AM UTC 24 |
| Finished | Oct 03 05:05:27 AM UTC 24 |
| Peak memory | 283092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008822194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2008822194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/14.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy_stress.3235489755 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 188581528 ps |
| CPU time | 14.92 seconds |
| Started | Oct 03 04:52:01 AM UTC 24 |
| Finished | Oct 03 04:52:17 AM UTC 24 |
| Peak memory | 260444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235489755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3235489755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/14.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_alert_accum.1979438798 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 17478396997 ps |
| CPU time | 291.92 seconds |
| Started | Oct 03 04:51:14 AM UTC 24 |
| Finished | Oct 03 04:56:10 AM UTC 24 |
| Peak memory | 266700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979438798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1979438798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/14.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_intr_timeout.2415348088 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 3027705566 ps |
| CPU time | 39.43 seconds |
| Started | Oct 03 04:51:06 AM UTC 24 |
| Finished | Oct 03 04:51:47 AM UTC 24 |
| Peak memory | 266712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415348088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2415348088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/14.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg.1933964937 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 29237306918 ps |
| CPU time | 713.48 seconds |
| Started | Oct 03 04:51:48 AM UTC 24 |
| Finished | Oct 03 05:03:50 AM UTC 24 |
| Peak memory | 283164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933964937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1933964937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/14.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg_stub_clk.98235840 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 16542098099 ps |
| CPU time | 952.66 seconds |
| Started | Oct 03 04:51:56 AM UTC 24 |
| Finished | Oct 03 05:08:00 AM UTC 24 |
| Peak memory | 283096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98235840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.98235840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/14.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/14.alert_handler_ping_timeout.1649799811 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 31274878964 ps |
| CPU time | 403.35 seconds |
| Started | Oct 03 04:51:48 AM UTC 24 |
| Finished | Oct 03 04:58:37 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649799811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1649799811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/14.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_alerts.3308259920 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 4206149651 ps |
| CPU time | 92.04 seconds |
| Started | Oct 03 04:50:24 AM UTC 24 |
| Finished | Oct 03 04:51:59 AM UTC 24 |
| Peak memory | 267000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308259920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3308259920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/14.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_classes.769372856 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 524489620 ps |
| CPU time | 18.89 seconds |
| Started | Oct 03 04:50:53 AM UTC 24 |
| Finished | Oct 03 04:51:13 AM UTC 24 |
| Peak memory | 260432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769372856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.769372856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/14.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/14.alert_handler_sig_int_fail.1158971650 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1075392878 ps |
| CPU time | 51.06 seconds |
| Started | Oct 03 04:51:19 AM UTC 24 |
| Finished | Oct 03 04:52:12 AM UTC 24 |
| Peak memory | 260628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158971650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1158971650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/14.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/14.alert_handler_smoke.29369200 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 749135671 ps |
| CPU time | 28.78 seconds |
| Started | Oct 03 04:50:21 AM UTC 24 |
| Finished | Oct 03 04:50:51 AM UTC 24 |
| Peak memory | 266836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29369200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smo ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.29369200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/14.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all.1517966387 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 14132754123 ps |
| CPU time | 162.69 seconds |
| Started | Oct 03 04:52:13 AM UTC 24 |
| Finished | Oct 03 04:54:59 AM UTC 24 |
| Peak memory | 266708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517966387 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_stress_all.1517966387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/14.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all_with_rand_reset.3400523219 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 4535836351 ps |
| CPU time | 198.24 seconds |
| Started | Oct 03 04:52:29 AM UTC 24 |
| Finished | Oct 03 04:55:51 AM UTC 24 |
| Peak memory | 283288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3400523219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.a lert_handler_stress_all_with_rand_reset.3400523219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/14.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/15.alert_handler_alert_accum_saturation.4263270858 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 50256897 ps |
| CPU time | 6.57 seconds |
| Started | Oct 03 04:55:41 AM UTC 24 |
| Finished | Oct 03 04:55:49 AM UTC 24 |
| Peak memory | 260776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263270858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.4263270858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/15.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy.3970009665 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 75167613256 ps |
| CPU time | 1280.35 seconds |
| Started | Oct 03 04:54:08 AM UTC 24 |
| Finished | Oct 03 05:15:43 AM UTC 24 |
| Peak memory | 283164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970009665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3970009665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/15.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy_stress.3584677026 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 446756765 ps |
| CPU time | 30.19 seconds |
| Started | Oct 03 04:55:00 AM UTC 24 |
| Finished | Oct 03 04:55:32 AM UTC 24 |
| Peak memory | 260708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584677026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3584677026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/15.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_alert_accum.1372272503 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 31954621595 ps |
| CPU time | 201.69 seconds |
| Started | Oct 03 04:53:35 AM UTC 24 |
| Finished | Oct 03 04:57:00 AM UTC 24 |
| Peak memory | 266772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372272503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1372272503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/15.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_intr_timeout.1388442598 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1848678725 ps |
| CPU time | 52.66 seconds |
| Started | Oct 03 04:53:12 AM UTC 24 |
| Finished | Oct 03 04:54:07 AM UTC 24 |
| Peak memory | 266576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388442598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1388442598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/15.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg.1853901335 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 80345598381 ps |
| CPU time | 2639.51 seconds |
| Started | Oct 03 04:54:21 AM UTC 24 |
| Finished | Oct 03 05:38:51 AM UTC 24 |
| Peak memory | 298220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853901335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1853901335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/15.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg_stub_clk.1612230118 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 17820518397 ps |
| CPU time | 857.09 seconds |
| Started | Oct 03 04:54:52 AM UTC 24 |
| Finished | Oct 03 05:09:20 AM UTC 24 |
| Peak memory | 283356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612230118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1612230118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/15.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/15.alert_handler_ping_timeout.730235722 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 9980577382 ps |
| CPU time | 117.28 seconds |
| Started | Oct 03 04:54:15 AM UTC 24 |
| Finished | Oct 03 04:56:14 AM UTC 24 |
| Peak memory | 260564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730235722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.730235722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/15.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_alerts.1865075238 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 3499395475 ps |
| CPU time | 36.48 seconds |
| Started | Oct 03 04:52:57 AM UTC 24 |
| Finished | Oct 03 04:53:35 AM UTC 24 |
| Peak memory | 260508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865075238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1865075238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/15.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_classes.624521644 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 2251646844 ps |
| CPU time | 43.42 seconds |
| Started | Oct 03 04:53:00 AM UTC 24 |
| Finished | Oct 03 04:53:45 AM UTC 24 |
| Peak memory | 260792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624521644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.624521644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/15.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/15.alert_handler_sig_int_fail.2615921434 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 622819938 ps |
| CPU time | 26.24 seconds |
| Started | Oct 03 04:53:46 AM UTC 24 |
| Finished | Oct 03 04:54:14 AM UTC 24 |
| Peak memory | 260564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615921434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2615921434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/15.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/15.alert_handler_smoke.2801816690 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 295501958 ps |
| CPU time | 17.14 seconds |
| Started | Oct 03 04:52:38 AM UTC 24 |
| Finished | Oct 03 04:52:56 AM UTC 24 |
| Peak memory | 260440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801816690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2801816690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/15.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all_with_rand_reset.1843568883 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 4326041956 ps |
| CPU time | 551.72 seconds |
| Started | Oct 03 04:55:50 AM UTC 24 |
| Finished | Oct 03 05:05:09 AM UTC 24 |
| Peak memory | 283288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1843568883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.a lert_handler_stress_all_with_rand_reset.1843568883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/15.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/16.alert_handler_alert_accum_saturation.1396596995 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 17066116 ps |
| CPU time | 4.38 seconds |
| Started | Oct 03 04:58:47 AM UTC 24 |
| Finished | Oct 03 04:58:53 AM UTC 24 |
| Peak memory | 260776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396596995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1396596995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/16.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy.2550585806 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 14356443087 ps |
| CPU time | 755.51 seconds |
| Started | Oct 03 04:57:01 AM UTC 24 |
| Finished | Oct 03 05:09:46 AM UTC 24 |
| Peak memory | 283292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550585806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2550585806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/16.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy_stress.1963423474 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 2031547355 ps |
| CPU time | 35.11 seconds |
| Started | Oct 03 04:58:38 AM UTC 24 |
| Finished | Oct 03 04:59:14 AM UTC 24 |
| Peak memory | 260444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963423474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1963423474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/16.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_alert_accum.686488435 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 1062460978 ps |
| CPU time | 57.25 seconds |
| Started | Oct 03 04:56:36 AM UTC 24 |
| Finished | Oct 03 04:57:35 AM UTC 24 |
| Peak memory | 266604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686488435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.686488435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/16.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_intr_timeout.175874977 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 7462751353 ps |
| CPU time | 58.35 seconds |
| Started | Oct 03 04:56:16 AM UTC 24 |
| Finished | Oct 03 04:57:16 AM UTC 24 |
| Peak memory | 260664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175874977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.175874977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/16.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/16.alert_handler_ping_timeout.3311754370 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 4871994752 ps |
| CPU time | 167.02 seconds |
| Started | Oct 03 04:57:17 AM UTC 24 |
| Finished | Oct 03 05:00:07 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311754370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3311754370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/16.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_alerts.516273155 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1497238640 ps |
| CPU time | 22.82 seconds |
| Started | Oct 03 04:56:11 AM UTC 24 |
| Finished | Oct 03 04:56:36 AM UTC 24 |
| Peak memory | 260428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516273155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.516273155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/16.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_classes.1475710325 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1613270806 ps |
| CPU time | 28.89 seconds |
| Started | Oct 03 04:56:15 AM UTC 24 |
| Finished | Oct 03 04:56:45 AM UTC 24 |
| Peak memory | 260788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475710325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1475710325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/16.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/16.alert_handler_sig_int_fail.2397473919 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 784313216 ps |
| CPU time | 72.06 seconds |
| Started | Oct 03 04:56:46 AM UTC 24 |
| Finished | Oct 03 04:58:00 AM UTC 24 |
| Peak memory | 260428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397473919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2397473919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/16.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/16.alert_handler_smoke.515951519 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 1979063146 ps |
| CPU time | 22.09 seconds |
| Started | Oct 03 04:55:52 AM UTC 24 |
| Finished | Oct 03 04:56:15 AM UTC 24 |
| Peak memory | 260508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515951519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.515951519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/16.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all.4011884643 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 3945051001 ps |
| CPU time | 153.99 seconds |
| Started | Oct 03 04:58:42 AM UTC 24 |
| Finished | Oct 03 05:01:19 AM UTC 24 |
| Peak memory | 266644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011884643 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_stress_all.4011884643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/16.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/17.alert_handler_alert_accum_saturation.3778627710 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 132644143 ps |
| CPU time | 5.07 seconds |
| Started | Oct 03 05:00:42 AM UTC 24 |
| Finished | Oct 03 05:00:48 AM UTC 24 |
| Peak memory | 260700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778627710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3778627710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/17.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy.1374445251 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 95340514821 ps |
| CPU time | 3252.81 seconds |
| Started | Oct 03 04:59:58 AM UTC 24 |
| Finished | Oct 03 05:54:49 AM UTC 24 |
| Peak memory | 302048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374445251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1374445251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/17.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy_stress.340401115 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 5269885906 ps |
| CPU time | 88.02 seconds |
| Started | Oct 03 05:00:23 AM UTC 24 |
| Finished | Oct 03 05:01:53 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340401115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.340401115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/17.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_intr_timeout.3767836960 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 1176896976 ps |
| CPU time | 57.94 seconds |
| Started | Oct 03 04:59:25 AM UTC 24 |
| Finished | Oct 03 05:00:25 AM UTC 24 |
| Peak memory | 260432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767836960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3767836960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/17.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg_stub_clk.428847776 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 72157355386 ps |
| CPU time | 2302.99 seconds |
| Started | Oct 03 05:00:16 AM UTC 24 |
| Finished | Oct 03 05:39:05 AM UTC 24 |
| Peak memory | 295908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428847776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.428847776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/17.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_alerts.21976112 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 223916196 ps |
| CPU time | 9.3 seconds |
| Started | Oct 03 04:59:15 AM UTC 24 |
| Finished | Oct 03 04:59:25 AM UTC 24 |
| Peak memory | 260728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21976112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ran dom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.21976112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/17.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_classes.832643824 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 349418397 ps |
| CPU time | 51.39 seconds |
| Started | Oct 03 04:59:22 AM UTC 24 |
| Finished | Oct 03 05:00:15 AM UTC 24 |
| Peak memory | 266680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832643824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.832643824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/17.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/17.alert_handler_sig_int_fail.1594929876 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 334834543 ps |
| CPU time | 11.55 seconds |
| Started | Oct 03 04:59:45 AM UTC 24 |
| Finished | Oct 03 04:59:58 AM UTC 24 |
| Peak memory | 260500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594929876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1594929876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/17.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/17.alert_handler_smoke.1403636965 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 3103578009 ps |
| CPU time | 47.61 seconds |
| Started | Oct 03 04:58:55 AM UTC 24 |
| Finished | Oct 03 04:59:45 AM UTC 24 |
| Peak memory | 266648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403636965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1403636965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/17.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/17.alert_handler_stress_all.913032470 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 210781608195 ps |
| CPU time | 1138.76 seconds |
| Started | Oct 03 05:00:26 AM UTC 24 |
| Finished | Oct 03 05:19:38 AM UTC 24 |
| Peak memory | 276936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913032470 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_stress_all.913032470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/17.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/18.alert_handler_alert_accum_saturation.3016081956 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 32037173 ps |
| CPU time | 5.09 seconds |
| Started | Oct 03 05:03:58 AM UTC 24 |
| Finished | Oct 03 05:04:04 AM UTC 24 |
| Peak memory | 260704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016081956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.3016081956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/18.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy.3873209144 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 70792724214 ps |
| CPU time | 1492.41 seconds |
| Started | Oct 03 05:03:08 AM UTC 24 |
| Finished | Oct 03 05:28:19 AM UTC 24 |
| Peak memory | 277276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873209144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3873209144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/18.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy_stress.2200971789 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 327305875 ps |
| CPU time | 13.9 seconds |
| Started | Oct 03 05:03:42 AM UTC 24 |
| Finished | Oct 03 05:03:57 AM UTC 24 |
| Peak memory | 260708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200971789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2200971789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/18.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_alert_accum.3514309110 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 5954440988 ps |
| CPU time | 75.95 seconds |
| Started | Oct 03 05:02:09 AM UTC 24 |
| Finished | Oct 03 05:03:26 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514309110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3514309110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/18.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_intr_timeout.3975851660 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 56593711 ps |
| CPU time | 8.77 seconds |
| Started | Oct 03 05:01:58 AM UTC 24 |
| Finished | Oct 03 05:02:08 AM UTC 24 |
| Peak memory | 260504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975851660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3975851660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/18.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg.4208106457 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 28752289318 ps |
| CPU time | 1675.58 seconds |
| Started | Oct 03 05:03:27 AM UTC 24 |
| Finished | Oct 03 05:31:43 AM UTC 24 |
| Peak memory | 283356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208106457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.4208106457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/18.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg_stub_clk.978971986 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 30242751736 ps |
| CPU time | 1649.18 seconds |
| Started | Oct 03 05:03:30 AM UTC 24 |
| Finished | Oct 03 05:31:21 AM UTC 24 |
| Peak memory | 293404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978971986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.978971986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/18.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/18.alert_handler_ping_timeout.958470997 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 12199137078 ps |
| CPU time | 80.34 seconds |
| Started | Oct 03 05:03:09 AM UTC 24 |
| Finished | Oct 03 05:04:31 AM UTC 24 |
| Peak memory | 260564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958470997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.958470997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/18.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_alerts.1437402662 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 2037372429 ps |
| CPU time | 75.81 seconds |
| Started | Oct 03 05:01:50 AM UTC 24 |
| Finished | Oct 03 05:03:08 AM UTC 24 |
| Peak memory | 266584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437402662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1437402662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/18.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/18.alert_handler_smoke.2745621571 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 1309951506 ps |
| CPU time | 27.49 seconds |
| Started | Oct 03 05:01:20 AM UTC 24 |
| Finished | Oct 03 05:01:49 AM UTC 24 |
| Peak memory | 266584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745621571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2745621571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/18.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all.441217074 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 37856796196 ps |
| CPU time | 1438.07 seconds |
| Started | Oct 03 05:03:53 AM UTC 24 |
| Finished | Oct 03 05:28:09 AM UTC 24 |
| Peak memory | 297420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441217074 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_stress_all.441217074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/18.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/19.alert_handler_alert_accum_saturation.2050789248 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 136700123 ps |
| CPU time | 5.7 seconds |
| Started | Oct 03 05:05:11 AM UTC 24 |
| Finished | Oct 03 05:05:17 AM UTC 24 |
| Peak memory | 260704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050789248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2050789248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/19.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy.4183204143 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 31347686667 ps |
| CPU time | 1015.62 seconds |
| Started | Oct 03 05:04:53 AM UTC 24 |
| Finished | Oct 03 05:22:02 AM UTC 24 |
| Peak memory | 283088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183204143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.4183204143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/19.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy_stress.4023957462 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 981668761 ps |
| CPU time | 8.5 seconds |
| Started | Oct 03 05:05:06 AM UTC 24 |
| Finished | Oct 03 05:05:16 AM UTC 24 |
| Peak memory | 260708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023957462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.4023957462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/19.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_alert_accum.2951554274 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 1295127843 ps |
| CPU time | 103.24 seconds |
| Started | Oct 03 05:04:45 AM UTC 24 |
| Finished | Oct 03 05:06:31 AM UTC 24 |
| Peak memory | 266644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951554274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2951554274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/19.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_intr_timeout.223756941 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 213966097 ps |
| CPU time | 11.24 seconds |
| Started | Oct 03 05:04:40 AM UTC 24 |
| Finished | Oct 03 05:04:53 AM UTC 24 |
| Peak memory | 264824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223756941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.223756941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/19.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg.3504826199 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 27585006801 ps |
| CPU time | 1625.27 seconds |
| Started | Oct 03 05:05:06 AM UTC 24 |
| Finished | Oct 03 05:32:32 AM UTC 24 |
| Peak memory | 299476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504826199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3504826199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/19.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/19.alert_handler_ping_timeout.141383893 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 6766088317 ps |
| CPU time | 128.12 seconds |
| Started | Oct 03 05:04:59 AM UTC 24 |
| Finished | Oct 03 05:07:09 AM UTC 24 |
| Peak memory | 260636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141383893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.141383893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/19.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_alerts.843262178 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 258598254 ps |
| CPU time | 6.6 seconds |
| Started | Oct 03 05:04:32 AM UTC 24 |
| Finished | Oct 03 05:04:40 AM UTC 24 |
| Peak memory | 260504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843262178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.843262178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/19.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_classes.2941168735 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 1437169266 ps |
| CPU time | 30.62 seconds |
| Started | Oct 03 05:04:33 AM UTC 24 |
| Finished | Oct 03 05:05:05 AM UTC 24 |
| Peak memory | 260724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941168735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2941168735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/19.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/19.alert_handler_sig_int_fail.386307546 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 182920861 ps |
| CPU time | 20.59 seconds |
| Started | Oct 03 05:04:47 AM UTC 24 |
| Finished | Oct 03 05:05:09 AM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386307546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.386307546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/19.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/19.alert_handler_smoke.1957164275 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 790240506 ps |
| CPU time | 37.21 seconds |
| Started | Oct 03 05:04:19 AM UTC 24 |
| Finished | Oct 03 05:04:58 AM UTC 24 |
| Peak memory | 266848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957164275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1957164275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/19.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all.918228323 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 23699709162 ps |
| CPU time | 1593.02 seconds |
| Started | Oct 03 05:05:11 AM UTC 24 |
| Finished | Oct 03 05:32:02 AM UTC 24 |
| Peak memory | 299468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918228323 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_stress_all.918228323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/19.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all_with_rand_reset.1044775204 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 15775122841 ps |
| CPU time | 362.09 seconds |
| Started | Oct 03 05:05:17 AM UTC 24 |
| Finished | Oct 03 05:11:24 AM UTC 24 |
| Peak memory | 277272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1044775204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.a lert_handler_stress_all_with_rand_reset.1044775204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/19.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/2.alert_handler_alert_accum_saturation.1993794127 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 44495390 ps |
| CPU time | 4.26 seconds |
| Started | Oct 03 04:37:54 AM UTC 24 |
| Finished | Oct 03 04:38:00 AM UTC 24 |
| Peak memory | 260968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993794127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1993794127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy.3943099375 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 23033440888 ps |
| CPU time | 1865.68 seconds |
| Started | Oct 03 04:37:38 AM UTC 24 |
| Finished | Oct 03 05:09:06 AM UTC 24 |
| Peak memory | 285744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943099375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3943099375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy_stress.3022987008 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 662288929 ps |
| CPU time | 31.31 seconds |
| Started | Oct 03 04:37:48 AM UTC 24 |
| Finished | Oct 03 04:38:21 AM UTC 24 |
| Peak memory | 260436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022987008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3022987008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_alert_accum.1999000920 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 38542661149 ps |
| CPU time | 361.72 seconds |
| Started | Oct 03 04:37:30 AM UTC 24 |
| Finished | Oct 03 04:43:37 AM UTC 24 |
| Peak memory | 266696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999000920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1999000920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_intr_timeout.162768050 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 994434805 ps |
| CPU time | 42.14 seconds |
| Started | Oct 03 04:37:26 AM UTC 24 |
| Finished | Oct 03 04:38:10 AM UTC 24 |
| Peak memory | 266572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162768050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.162768050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg.3380400280 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 46442885741 ps |
| CPU time | 1329.56 seconds |
| Started | Oct 03 04:37:42 AM UTC 24 |
| Finished | Oct 03 05:00:08 AM UTC 24 |
| Peak memory | 276940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380400280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3380400280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg_stub_clk.2255528997 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 12675497352 ps |
| CPU time | 747.99 seconds |
| Started | Oct 03 04:37:44 AM UTC 24 |
| Finished | Oct 03 04:50:22 AM UTC 24 |
| Peak memory | 283168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255528997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2255528997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/2.alert_handler_ping_timeout.706450785 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 96072267686 ps |
| CPU time | 465.32 seconds |
| Started | Oct 03 04:37:38 AM UTC 24 |
| Finished | Oct 03 04:45:30 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706450785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.706450785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_classes.1302371949 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 4946044465 ps |
| CPU time | 49.2 seconds |
| Started | Oct 03 04:37:22 AM UTC 24 |
| Finished | Oct 03 04:38:13 AM UTC 24 |
| Peak memory | 260664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302371949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1302371949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/2.alert_handler_sec_cm.801749296 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 2171167668 ps |
| CPU time | 30.45 seconds |
| Started | Oct 03 04:37:57 AM UTC 24 |
| Finished | Oct 03 04:38:28 AM UTC 24 |
| Peak memory | 296964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801749296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_h andler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.801749296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/2.alert_handler_smoke.1936676850 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1785501992 ps |
| CPU time | 60.44 seconds |
| Started | Oct 03 04:37:18 AM UTC 24 |
| Finished | Oct 03 04:38:20 AM UTC 24 |
| Peak memory | 266836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936676850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1936676850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/2.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/20.alert_handler_entropy.3932346588 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 211314405774 ps |
| CPU time | 2754.09 seconds |
| Started | Oct 03 05:06:12 AM UTC 24 |
| Finished | Oct 03 05:52:37 AM UTC 24 |
| Peak memory | 302048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932346588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3932346588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/20.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_alert_accum.1218698666 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 5651639543 ps |
| CPU time | 135.23 seconds |
| Started | Oct 03 05:06:04 AM UTC 24 |
| Finished | Oct 03 05:08:22 AM UTC 24 |
| Peak memory | 266772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218698666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1218698666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/20.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_intr_timeout.1767363327 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 168871549 ps |
| CPU time | 13.64 seconds |
| Started | Oct 03 05:05:49 AM UTC 24 |
| Finished | Oct 03 05:06:04 AM UTC 24 |
| Peak memory | 264664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767363327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1767363327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/20.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg.2264640585 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 30030213873 ps |
| CPU time | 2062.19 seconds |
| Started | Oct 03 05:06:59 AM UTC 24 |
| Finished | Oct 03 05:41:46 AM UTC 24 |
| Peak memory | 302124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264640585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2264640585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/20.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg_stub_clk.2068396231 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 341770354101 ps |
| CPU time | 2632.94 seconds |
| Started | Oct 03 05:07:10 AM UTC 24 |
| Finished | Oct 03 05:51:34 AM UTC 24 |
| Peak memory | 302060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068396231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2068396231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/20.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_alerts.3453190987 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 830823186 ps |
| CPU time | 17.47 seconds |
| Started | Oct 03 05:05:29 AM UTC 24 |
| Finished | Oct 03 05:05:48 AM UTC 24 |
| Peak memory | 260472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453190987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3453190987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/20.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_classes.657076578 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1016099950 ps |
| CPU time | 29.82 seconds |
| Started | Oct 03 05:05:39 AM UTC 24 |
| Finished | Oct 03 05:06:10 AM UTC 24 |
| Peak memory | 260452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657076578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.657076578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/20.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/20.alert_handler_sig_int_fail.3913792579 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 3073095889 ps |
| CPU time | 50.95 seconds |
| Started | Oct 03 05:06:05 AM UTC 24 |
| Finished | Oct 03 05:06:58 AM UTC 24 |
| Peak memory | 266708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913792579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3913792579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/20.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/20.alert_handler_smoke.1931454024 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 365107482 ps |
| CPU time | 19.45 seconds |
| Started | Oct 03 05:05:18 AM UTC 24 |
| Finished | Oct 03 05:05:39 AM UTC 24 |
| Peak memory | 260512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931454024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1931454024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/20.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all.206241226 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 40620174578 ps |
| CPU time | 2101.25 seconds |
| Started | Oct 03 05:07:25 AM UTC 24 |
| Finished | Oct 03 05:42:52 AM UTC 24 |
| Peak memory | 296164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206241226 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_stress_all.206241226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/20.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all_with_rand_reset.1424639524 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 7548498853 ps |
| CPU time | 214.45 seconds |
| Started | Oct 03 05:08:03 AM UTC 24 |
| Finished | Oct 03 05:11:41 AM UTC 24 |
| Peak memory | 283288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1424639524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.a lert_handler_stress_all_with_rand_reset.1424639524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/20.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/21.alert_handler_entropy.1343750879 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 112664466554 ps |
| CPU time | 2043.07 seconds |
| Started | Oct 03 05:09:25 AM UTC 24 |
| Finished | Oct 03 05:43:52 AM UTC 24 |
| Peak memory | 285668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343750879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1343750879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/21.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_alert_accum.1271456008 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 1582018738 ps |
| CPU time | 186.51 seconds |
| Started | Oct 03 05:09:15 AM UTC 24 |
| Finished | Oct 03 05:12:25 AM UTC 24 |
| Peak memory | 266708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271456008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1271456008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/21.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_intr_timeout.1105019319 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1981239073 ps |
| CPU time | 29.17 seconds |
| Started | Oct 03 05:09:08 AM UTC 24 |
| Finished | Oct 03 05:09:39 AM UTC 24 |
| Peak memory | 266648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105019319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1105019319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/21.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg_stub_clk.1971847789 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 28226303659 ps |
| CPU time | 1025.33 seconds |
| Started | Oct 03 05:09:44 AM UTC 24 |
| Finished | Oct 03 05:27:03 AM UTC 24 |
| Peak memory | 283364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971847789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1971847789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/21.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_alerts.460341892 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 478844168 ps |
| CPU time | 39.85 seconds |
| Started | Oct 03 05:08:33 AM UTC 24 |
| Finished | Oct 03 05:09:14 AM UTC 24 |
| Peak memory | 266648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460341892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.460341892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/21.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_classes.474365520 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 379542158 ps |
| CPU time | 20.45 seconds |
| Started | Oct 03 05:09:02 AM UTC 24 |
| Finished | Oct 03 05:09:24 AM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474365520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.474365520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/21.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/21.alert_handler_sig_int_fail.2068614141 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 1847756633 ps |
| CPU time | 77.2 seconds |
| Started | Oct 03 05:09:23 AM UTC 24 |
| Finished | Oct 03 05:10:42 AM UTC 24 |
| Peak memory | 266572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068614141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.2068614141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/21.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/21.alert_handler_smoke.2730159776 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 237222563 ps |
| CPU time | 36.01 seconds |
| Started | Oct 03 05:08:23 AM UTC 24 |
| Finished | Oct 03 05:09:01 AM UTC 24 |
| Peak memory | 266644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730159776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2730159776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/21.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all.554543666 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 64067641898 ps |
| CPU time | 2259.84 seconds |
| Started | Oct 03 05:09:48 AM UTC 24 |
| Finished | Oct 03 05:47:56 AM UTC 24 |
| Peak memory | 296164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554543666 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_stress_all.554543666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/21.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all_with_rand_reset.3142491718 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 8548179011 ps |
| CPU time | 198.33 seconds |
| Started | Oct 03 05:10:20 AM UTC 24 |
| Finished | Oct 03 05:13:42 AM UTC 24 |
| Peak memory | 281168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3142491718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.a lert_handler_stress_all_with_rand_reset.3142491718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/21.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/22.alert_handler_entropy.725029112 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 58944384710 ps |
| CPU time | 1285.95 seconds |
| Started | Oct 03 05:11:26 AM UTC 24 |
| Finished | Oct 03 05:33:08 AM UTC 24 |
| Peak memory | 276948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725029112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.725029112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/22.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_alert_accum.763479323 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 4496682665 ps |
| CPU time | 268.96 seconds |
| Started | Oct 03 05:11:10 AM UTC 24 |
| Finished | Oct 03 05:15:43 AM UTC 24 |
| Peak memory | 266996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763479323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.763479323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/22.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_intr_timeout.446330299 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 618459720 ps |
| CPU time | 57.17 seconds |
| Started | Oct 03 05:11:07 AM UTC 24 |
| Finished | Oct 03 05:12:06 AM UTC 24 |
| Peak memory | 266680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446330299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.446330299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/22.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg.859967600 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 9556571751 ps |
| CPU time | 905.45 seconds |
| Started | Oct 03 05:11:33 AM UTC 24 |
| Finished | Oct 03 05:26:49 AM UTC 24 |
| Peak memory | 283088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859967600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.859967600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/22.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg_stub_clk.1690376520 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 238075212150 ps |
| CPU time | 3413.92 seconds |
| Started | Oct 03 05:11:38 AM UTC 24 |
| Finished | Oct 03 06:09:10 AM UTC 24 |
| Peak memory | 298228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690376520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1690376520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/22.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/22.alert_handler_ping_timeout.2842705693 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 2810817954 ps |
| CPU time | 120.56 seconds |
| Started | Oct 03 05:11:32 AM UTC 24 |
| Finished | Oct 03 05:13:34 AM UTC 24 |
| Peak memory | 260772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842705693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2842705693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_alerts.99584727 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 2145096094 ps |
| CPU time | 46.44 seconds |
| Started | Oct 03 05:10:43 AM UTC 24 |
| Finished | Oct 03 05:11:31 AM UTC 24 |
| Peak memory | 266584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99584727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ran dom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.99584727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/22.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_classes.3884337695 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 316414430 ps |
| CPU time | 21.93 seconds |
| Started | Oct 03 05:11:07 AM UTC 24 |
| Finished | Oct 03 05:11:31 AM UTC 24 |
| Peak memory | 260444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884337695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3884337695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/22.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/22.alert_handler_sig_int_fail.3612875788 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 277601783 ps |
| CPU time | 34.19 seconds |
| Started | Oct 03 05:11:21 AM UTC 24 |
| Finished | Oct 03 05:11:57 AM UTC 24 |
| Peak memory | 266580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612875788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3612875788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/22.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/22.alert_handler_smoke.716249718 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 409691727 ps |
| CPU time | 44.14 seconds |
| Started | Oct 03 05:10:24 AM UTC 24 |
| Finished | Oct 03 05:11:10 AM UTC 24 |
| Peak memory | 266580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716249718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.716249718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/22.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all.2249052166 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 19450934419 ps |
| CPU time | 1389.24 seconds |
| Started | Oct 03 05:11:42 AM UTC 24 |
| Finished | Oct 03 05:35:08 AM UTC 24 |
| Peak memory | 299548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249052166 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_stress_all.2249052166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/22.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/23.alert_handler_entropy.905297660 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 110376276294 ps |
| CPU time | 3278.46 seconds |
| Started | Oct 03 05:12:37 AM UTC 24 |
| Finished | Oct 03 06:07:53 AM UTC 24 |
| Peak memory | 302056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905297660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.905297660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/23.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_alert_accum.3571022179 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 8875958410 ps |
| CPU time | 134.03 seconds |
| Started | Oct 03 05:12:26 AM UTC 24 |
| Finished | Oct 03 05:14:43 AM UTC 24 |
| Peak memory | 266700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571022179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3571022179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/23.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_intr_timeout.1719928435 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 307861439 ps |
| CPU time | 6.55 seconds |
| Started | Oct 03 05:12:21 AM UTC 24 |
| Finished | Oct 03 05:12:28 AM UTC 24 |
| Peak memory | 250264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719928435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1719928435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/23.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg.414514330 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 23093320953 ps |
| CPU time | 1380.96 seconds |
| Started | Oct 03 05:12:46 AM UTC 24 |
| Finished | Oct 03 05:36:04 AM UTC 24 |
| Peak memory | 283356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414514330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.414514330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/23.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg_stub_clk.3204187993 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 205138767782 ps |
| CPU time | 1654.33 seconds |
| Started | Oct 03 05:13:31 AM UTC 24 |
| Finished | Oct 03 05:41:25 AM UTC 24 |
| Peak memory | 283164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204187993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3204187993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/23.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/23.alert_handler_ping_timeout.4108768093 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 6443588962 ps |
| CPU time | 244.32 seconds |
| Started | Oct 03 05:12:44 AM UTC 24 |
| Finished | Oct 03 05:16:53 AM UTC 24 |
| Peak memory | 260644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108768093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.4108768093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/23.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_alerts.160767641 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 365532189 ps |
| CPU time | 9.35 seconds |
| Started | Oct 03 05:12:09 AM UTC 24 |
| Finished | Oct 03 05:12:20 AM UTC 24 |
| Peak memory | 260696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160767641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.160767641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/23.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_classes.1055498791 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 203963518 ps |
| CPU time | 21.35 seconds |
| Started | Oct 03 05:12:14 AM UTC 24 |
| Finished | Oct 03 05:12:36 AM UTC 24 |
| Peak memory | 266676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055498791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1055498791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/23.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/23.alert_handler_sig_int_fail.562422509 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 241629686 ps |
| CPU time | 13.2 seconds |
| Started | Oct 03 05:12:29 AM UTC 24 |
| Finished | Oct 03 05:12:44 AM UTC 24 |
| Peak memory | 260464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562422509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.562422509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/23.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/23.alert_handler_smoke.2043501513 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 367951871 ps |
| CPU time | 34.52 seconds |
| Started | Oct 03 05:12:08 AM UTC 24 |
| Finished | Oct 03 05:12:44 AM UTC 24 |
| Peak memory | 260440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043501513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2043501513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/23.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all.2371503687 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 12306476109 ps |
| CPU time | 201.67 seconds |
| Started | Oct 03 05:13:35 AM UTC 24 |
| Finished | Oct 03 05:17:00 AM UTC 24 |
| Peak memory | 262684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371503687 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_stress_all.2371503687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/23.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/24.alert_handler_entropy.3051967359 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 38317026562 ps |
| CPU time | 1356.84 seconds |
| Started | Oct 03 05:15:27 AM UTC 24 |
| Finished | Oct 03 05:38:22 AM UTC 24 |
| Peak memory | 293596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051967359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3051967359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/24.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_alert_accum.2945029333 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 1919797809 ps |
| CPU time | 99.74 seconds |
| Started | Oct 03 05:15:09 AM UTC 24 |
| Finished | Oct 03 05:16:52 AM UTC 24 |
| Peak memory | 266644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945029333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2945029333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/24.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_intr_timeout.3430568640 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 170486222 ps |
| CPU time | 17.09 seconds |
| Started | Oct 03 05:14:50 AM UTC 24 |
| Finished | Oct 03 05:15:08 AM UTC 24 |
| Peak memory | 260504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430568640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3430568640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/24.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg.432597585 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 204474908771 ps |
| CPU time | 3149 seconds |
| Started | Oct 03 05:15:46 AM UTC 24 |
| Finished | Oct 03 06:08:52 AM UTC 24 |
| Peak memory | 302120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432597585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.432597585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/24.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg_stub_clk.154995629 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 81284059268 ps |
| CPU time | 3129.76 seconds |
| Started | Oct 03 05:16:03 AM UTC 24 |
| Finished | Oct 03 06:08:49 AM UTC 24 |
| Peak memory | 302128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154995629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.154995629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/24.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/24.alert_handler_ping_timeout.1681842333 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 8599146707 ps |
| CPU time | 264.32 seconds |
| Started | Oct 03 05:15:44 AM UTC 24 |
| Finished | Oct 03 05:20:12 AM UTC 24 |
| Peak memory | 260580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681842333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1681842333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/24.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_alerts.958118483 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 2565191803 ps |
| CPU time | 64.97 seconds |
| Started | Oct 03 05:14:19 AM UTC 24 |
| Finished | Oct 03 05:15:26 AM UTC 24 |
| Peak memory | 266904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958118483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.958118483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/24.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_classes.415249716 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 1225885874 ps |
| CPU time | 37.83 seconds |
| Started | Oct 03 05:14:44 AM UTC 24 |
| Finished | Oct 03 05:15:23 AM UTC 24 |
| Peak memory | 266596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415249716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.415249716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/24.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/24.alert_handler_smoke.586004912 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 168441716 ps |
| CPU time | 19.65 seconds |
| Started | Oct 03 05:13:57 AM UTC 24 |
| Finished | Oct 03 05:14:18 AM UTC 24 |
| Peak memory | 266844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586004912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.586004912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/24.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all.25018723 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 4265546992 ps |
| CPU time | 217.38 seconds |
| Started | Oct 03 05:16:18 AM UTC 24 |
| Finished | Oct 03 05:20:00 AM UTC 24 |
| Peak memory | 266640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25018723 -assert nopostproc +UVM_TES TNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_stress_all.25018723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/24.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all_with_rand_reset.3160509248 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 9020964889 ps |
| CPU time | 563.96 seconds |
| Started | Oct 03 05:16:23 AM UTC 24 |
| Finished | Oct 03 05:25:55 AM UTC 24 |
| Peak memory | 283544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3160509248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.a lert_handler_stress_all_with_rand_reset.3160509248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/24.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/25.alert_handler_entropy.3363281049 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 108863753732 ps |
| CPU time | 2539.13 seconds |
| Started | Oct 03 05:17:58 AM UTC 24 |
| Finished | Oct 03 06:00:50 AM UTC 24 |
| Peak memory | 297952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363281049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3363281049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/25.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_alert_accum.3299373397 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 4328725372 ps |
| CPU time | 140.93 seconds |
| Started | Oct 03 05:17:17 AM UTC 24 |
| Finished | Oct 03 05:19:40 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299373397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3299373397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/25.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_intr_timeout.3505288808 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 4779287141 ps |
| CPU time | 54.07 seconds |
| Started | Oct 03 05:17:02 AM UTC 24 |
| Finished | Oct 03 05:17:58 AM UTC 24 |
| Peak memory | 260632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505288808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3505288808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/25.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg_stub_clk.115658009 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 69908620879 ps |
| CPU time | 1561.42 seconds |
| Started | Oct 03 05:19:15 AM UTC 24 |
| Finished | Oct 03 05:45:35 AM UTC 24 |
| Peak memory | 283164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115658009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.115658009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/25.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/25.alert_handler_ping_timeout.3229338526 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 64168581560 ps |
| CPU time | 217.43 seconds |
| Started | Oct 03 05:17:59 AM UTC 24 |
| Finished | Oct 03 05:21:40 AM UTC 24 |
| Peak memory | 260572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229338526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3229338526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/25.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_alerts.3184819871 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 819907523 ps |
| CPU time | 60.86 seconds |
| Started | Oct 03 05:16:54 AM UTC 24 |
| Finished | Oct 03 05:17:57 AM UTC 24 |
| Peak memory | 266576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184819871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3184819871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/25.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_classes.2617602023 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1099396691 ps |
| CPU time | 19.77 seconds |
| Started | Oct 03 05:16:54 AM UTC 24 |
| Finished | Oct 03 05:17:15 AM UTC 24 |
| Peak memory | 260428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617602023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2617602023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/25.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/25.alert_handler_sig_int_fail.2330604193 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1082199270 ps |
| CPU time | 48.78 seconds |
| Started | Oct 03 05:17:35 AM UTC 24 |
| Finished | Oct 03 05:18:25 AM UTC 24 |
| Peak memory | 260500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330604193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2330604193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/25.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/25.alert_handler_smoke.2454092425 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 1300013251 ps |
| CPU time | 142.81 seconds |
| Started | Oct 03 05:16:48 AM UTC 24 |
| Finished | Oct 03 05:19:14 AM UTC 24 |
| Peak memory | 260704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454092425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2454092425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/25.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/26.alert_handler_entropy.1477658018 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 80129793332 ps |
| CPU time | 3194.17 seconds |
| Started | Oct 03 05:20:21 AM UTC 24 |
| Finished | Oct 03 06:14:12 AM UTC 24 |
| Peak memory | 302048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477658018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1477658018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/26.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_alert_accum.2095940831 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 16012671184 ps |
| CPU time | 149.94 seconds |
| Started | Oct 03 05:20:06 AM UTC 24 |
| Finished | Oct 03 05:22:39 AM UTC 24 |
| Peak memory | 266700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095940831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2095940831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/26.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_intr_timeout.472737446 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 1515534952 ps |
| CPU time | 47.02 seconds |
| Started | Oct 03 05:20:01 AM UTC 24 |
| Finished | Oct 03 05:20:50 AM UTC 24 |
| Peak memory | 266576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472737446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.472737446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/26.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg.4083868650 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 35053562421 ps |
| CPU time | 2470.45 seconds |
| Started | Oct 03 05:20:45 AM UTC 24 |
| Finished | Oct 03 06:02:24 AM UTC 24 |
| Peak memory | 302052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083868650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.4083868650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/26.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg_stub_clk.3744722669 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 9807020916 ps |
| CPU time | 1106.31 seconds |
| Started | Oct 03 05:20:51 AM UTC 24 |
| Finished | Oct 03 05:39:31 AM UTC 24 |
| Peak memory | 283096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744722669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3744722669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/26.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/26.alert_handler_ping_timeout.3794470747 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 20275075104 ps |
| CPU time | 196.83 seconds |
| Started | Oct 03 05:20:39 AM UTC 24 |
| Finished | Oct 03 05:23:59 AM UTC 24 |
| Peak memory | 260572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794470747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3794470747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/26.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_alerts.185265516 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 389646276 ps |
| CPU time | 10.04 seconds |
| Started | Oct 03 05:19:42 AM UTC 24 |
| Finished | Oct 03 05:19:53 AM UTC 24 |
| Peak memory | 260732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185265516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.185265516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/26.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_classes.288220661 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 2417219257 ps |
| CPU time | 48.52 seconds |
| Started | Oct 03 05:19:54 AM UTC 24 |
| Finished | Oct 03 05:20:44 AM UTC 24 |
| Peak memory | 266640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288220661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.288220661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/26.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/26.alert_handler_sig_int_fail.3006431237 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 385540944 ps |
| CPU time | 23.72 seconds |
| Started | Oct 03 05:20:13 AM UTC 24 |
| Finished | Oct 03 05:20:38 AM UTC 24 |
| Peak memory | 260692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006431237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3006431237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/26.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/26.alert_handler_smoke.3345095009 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 5879355442 ps |
| CPU time | 23.59 seconds |
| Started | Oct 03 05:19:40 AM UTC 24 |
| Finished | Oct 03 05:20:05 AM UTC 24 |
| Peak memory | 260556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345095009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3345095009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/26.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all.3670884522 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 61040791284 ps |
| CPU time | 1300.92 seconds |
| Started | Oct 03 05:21:00 AM UTC 24 |
| Finished | Oct 03 05:42:57 AM UTC 24 |
| Peak memory | 283164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670884522 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_stress_all.3670884522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/26.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all_with_rand_reset.2309875484 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 6500857501 ps |
| CPU time | 506.95 seconds |
| Started | Oct 03 05:21:06 AM UTC 24 |
| Finished | Oct 03 05:29:40 AM UTC 24 |
| Peak memory | 277336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2309875484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.a lert_handler_stress_all_with_rand_reset.2309875484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/26.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/27.alert_handler_entropy.2776619272 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 232201859809 ps |
| CPU time | 3269.73 seconds |
| Started | Oct 03 05:22:11 AM UTC 24 |
| Finished | Oct 03 06:17:18 AM UTC 24 |
| Peak memory | 302048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776619272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2776619272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/27.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_alert_accum.1583612450 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 1603299049 ps |
| CPU time | 75.5 seconds |
| Started | Oct 03 05:22:04 AM UTC 24 |
| Finished | Oct 03 05:23:22 AM UTC 24 |
| Peak memory | 266572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583612450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1583612450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/27.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_intr_timeout.3724697848 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 96740928 ps |
| CPU time | 14.93 seconds |
| Started | Oct 03 05:21:55 AM UTC 24 |
| Finished | Oct 03 05:22:11 AM UTC 24 |
| Peak memory | 260432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724697848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3724697848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/27.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg.4164185530 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 44623167862 ps |
| CPU time | 1630.13 seconds |
| Started | Oct 03 05:22:23 AM UTC 24 |
| Finished | Oct 03 05:49:53 AM UTC 24 |
| Peak memory | 283356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164185530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.4164185530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/27.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg_stub_clk.2578524673 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 47510354196 ps |
| CPU time | 1959.19 seconds |
| Started | Oct 03 05:22:35 AM UTC 24 |
| Finished | Oct 03 05:55:37 AM UTC 24 |
| Peak memory | 295380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578524673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2578524673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/27.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/27.alert_handler_ping_timeout.3910842717 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 54141013280 ps |
| CPU time | 133.22 seconds |
| Started | Oct 03 05:22:18 AM UTC 24 |
| Finished | Oct 03 05:24:33 AM UTC 24 |
| Peak memory | 260564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910842717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3910842717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_alerts.686511547 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 472074605 ps |
| CPU time | 34.36 seconds |
| Started | Oct 03 05:21:41 AM UTC 24 |
| Finished | Oct 03 05:22:17 AM UTC 24 |
| Peak memory | 266612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686511547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.686511547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/27.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_classes.1583300183 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 192078359 ps |
| CPU time | 15.38 seconds |
| Started | Oct 03 05:21:54 AM UTC 24 |
| Finished | Oct 03 05:22:10 AM UTC 24 |
| Peak memory | 266676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583300183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1583300183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/27.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/27.alert_handler_sig_int_fail.2032159507 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 348234774 ps |
| CPU time | 21.7 seconds |
| Started | Oct 03 05:22:11 AM UTC 24 |
| Finished | Oct 03 05:22:34 AM UTC 24 |
| Peak memory | 260428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032159507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2032159507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/27.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/27.alert_handler_smoke.1521471368 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 672703348 ps |
| CPU time | 37.82 seconds |
| Started | Oct 03 05:21:15 AM UTC 24 |
| Finished | Oct 03 05:21:54 AM UTC 24 |
| Peak memory | 260512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521471368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1521471368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/27.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all.3460425884 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 23734036179 ps |
| CPU time | 1658.78 seconds |
| Started | Oct 03 05:22:39 AM UTC 24 |
| Finished | Oct 03 05:50:37 AM UTC 24 |
| Peak memory | 283164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460425884 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_stress_all.3460425884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/27.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/28.alert_handler_entropy.57529538 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 7456961829 ps |
| CPU time | 830.82 seconds |
| Started | Oct 03 05:23:43 AM UTC 24 |
| Finished | Oct 03 05:37:45 AM UTC 24 |
| Peak memory | 295384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57529538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/a lert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.57529538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/28.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_alert_accum.736667827 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 4757189865 ps |
| CPU time | 323.14 seconds |
| Started | Oct 03 05:23:32 AM UTC 24 |
| Finished | Oct 03 05:29:00 AM UTC 24 |
| Peak memory | 262616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736667827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.736667827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/28.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_intr_timeout.1110923520 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 245109044 ps |
| CPU time | 7.65 seconds |
| Started | Oct 03 05:23:25 AM UTC 24 |
| Finished | Oct 03 05:23:34 AM UTC 24 |
| Peak memory | 250192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110923520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1110923520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/28.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg.2615129547 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 43913693145 ps |
| CPU time | 2496.73 seconds |
| Started | Oct 03 05:24:03 AM UTC 24 |
| Finished | Oct 03 06:06:09 AM UTC 24 |
| Peak memory | 302052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615129547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2615129547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/28.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg_stub_clk.1810543246 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 44508330330 ps |
| CPU time | 3246.74 seconds |
| Started | Oct 03 05:24:18 AM UTC 24 |
| Finished | Oct 03 06:19:03 AM UTC 24 |
| Peak memory | 302132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810543246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1810543246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/28.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/28.alert_handler_ping_timeout.1138491585 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 29215002270 ps |
| CPU time | 289.48 seconds |
| Started | Oct 03 05:24:01 AM UTC 24 |
| Finished | Oct 03 05:28:54 AM UTC 24 |
| Peak memory | 260572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138491585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1138491585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/28.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_alerts.1507517221 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 668555700 ps |
| CPU time | 53.78 seconds |
| Started | Oct 03 05:23:22 AM UTC 24 |
| Finished | Oct 03 05:24:17 AM UTC 24 |
| Peak memory | 266608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507517221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1507517221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/28.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_classes.1021827144 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 94327222 ps |
| CPU time | 7.02 seconds |
| Started | Oct 03 05:23:23 AM UTC 24 |
| Finished | Oct 03 05:23:31 AM UTC 24 |
| Peak memory | 262476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021827144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1021827144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/28.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/28.alert_handler_smoke.2036274931 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 1223558161 ps |
| CPU time | 39.7 seconds |
| Started | Oct 03 05:23:01 AM UTC 24 |
| Finished | Oct 03 05:23:43 AM UTC 24 |
| Peak memory | 266656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036274931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2036274931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/28.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/29.alert_handler_entropy.3698139537 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 28123333191 ps |
| CPU time | 766.38 seconds |
| Started | Oct 03 05:26:15 AM UTC 24 |
| Finished | Oct 03 05:39:12 AM UTC 24 |
| Peak memory | 277212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698139537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3698139537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/29.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_alert_accum.705935108 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 107867442 ps |
| CPU time | 8.59 seconds |
| Started | Oct 03 05:26:05 AM UTC 24 |
| Finished | Oct 03 05:26:15 AM UTC 24 |
| Peak memory | 266572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705935108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.705935108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/29.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_intr_timeout.929417582 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 85088128 ps |
| CPU time | 9.33 seconds |
| Started | Oct 03 05:25:57 AM UTC 24 |
| Finished | Oct 03 05:26:07 AM UTC 24 |
| Peak memory | 260464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929417582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.929417582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/29.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg.4259584965 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 129186910537 ps |
| CPU time | 1247 seconds |
| Started | Oct 03 05:26:53 AM UTC 24 |
| Finished | Oct 03 05:47:56 AM UTC 24 |
| Peak memory | 283356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259584965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.4259584965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/29.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg_stub_clk.3091560873 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 92487740658 ps |
| CPU time | 1536.39 seconds |
| Started | Oct 03 05:26:53 AM UTC 24 |
| Finished | Oct 03 05:52:47 AM UTC 24 |
| Peak memory | 283236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091560873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3091560873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/29.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/29.alert_handler_ping_timeout.2144053293 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 42690766075 ps |
| CPU time | 462.55 seconds |
| Started | Oct 03 05:26:41 AM UTC 24 |
| Finished | Oct 03 05:34:30 AM UTC 24 |
| Peak memory | 260572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144053293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2144053293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/29.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_alerts.937636490 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 1085834122 ps |
| CPU time | 25.15 seconds |
| Started | Oct 03 05:25:38 AM UTC 24 |
| Finished | Oct 03 05:26:04 AM UTC 24 |
| Peak memory | 266572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937636490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.937636490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/29.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_classes.3645285056 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 3064331669 ps |
| CPU time | 52.99 seconds |
| Started | Oct 03 05:25:56 AM UTC 24 |
| Finished | Oct 03 05:26:50 AM UTC 24 |
| Peak memory | 260788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645285056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3645285056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/29.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/29.alert_handler_sig_int_fail.91515832 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 415922036 ps |
| CPU time | 31.44 seconds |
| Started | Oct 03 05:26:08 AM UTC 24 |
| Finished | Oct 03 05:26:41 AM UTC 24 |
| Peak memory | 260428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91515832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig _int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.91515832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/29.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/29.alert_handler_smoke.433699399 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 264912598 ps |
| CPU time | 21.29 seconds |
| Started | Oct 03 05:25:34 AM UTC 24 |
| Finished | Oct 03 05:25:56 AM UTC 24 |
| Peak memory | 266652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433699399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.433699399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/29.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all.1448654333 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 8096088868 ps |
| CPU time | 158.53 seconds |
| Started | Oct 03 05:26:53 AM UTC 24 |
| Finished | Oct 03 05:29:34 AM UTC 24 |
| Peak memory | 266780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448654333 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_stress_all.1448654333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/29.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all_with_rand_reset.3266995056 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1502394399 ps |
| CPU time | 239 seconds |
| Started | Oct 03 05:27:04 AM UTC 24 |
| Finished | Oct 03 05:31:07 AM UTC 24 |
| Peak memory | 283160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3266995056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.a lert_handler_stress_all_with_rand_reset.3266995056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/29.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy.615613115 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 48281110108 ps |
| CPU time | 1977.12 seconds |
| Started | Oct 03 04:38:13 AM UTC 24 |
| Finished | Oct 03 05:11:35 AM UTC 24 |
| Peak memory | 302128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615613115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.615613115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy_stress.2934755702 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 937062188 ps |
| CPU time | 27.27 seconds |
| Started | Oct 03 04:38:21 AM UTC 24 |
| Finished | Oct 03 04:38:50 AM UTC 24 |
| Peak memory | 260764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934755702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2934755702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_alert_accum.2429455391 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 25742615699 ps |
| CPU time | 224.39 seconds |
| Started | Oct 03 04:38:11 AM UTC 24 |
| Finished | Oct 03 04:41:59 AM UTC 24 |
| Peak memory | 266696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429455391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2429455391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_intr_timeout.664399467 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 241982711 ps |
| CPU time | 21.4 seconds |
| Started | Oct 03 04:38:11 AM UTC 24 |
| Finished | Oct 03 04:38:34 AM UTC 24 |
| Peak memory | 266644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664399467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.664399467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg.1432545495 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 10852992039 ps |
| CPU time | 1210.17 seconds |
| Started | Oct 03 04:38:14 AM UTC 24 |
| Finished | Oct 03 04:58:39 AM UTC 24 |
| Peak memory | 299480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432545495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1432545495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg_stub_clk.1346459407 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 20250361217 ps |
| CPU time | 645.23 seconds |
| Started | Oct 03 04:38:17 AM UTC 24 |
| Finished | Oct 03 04:49:11 AM UTC 24 |
| Peak memory | 281120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346459407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1346459407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/3.alert_handler_ping_timeout.148195257 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 21413249828 ps |
| CPU time | 227.66 seconds |
| Started | Oct 03 04:38:14 AM UTC 24 |
| Finished | Oct 03 04:42:05 AM UTC 24 |
| Peak memory | 260564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148195257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.148195257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_alerts.553067733 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1700426244 ps |
| CPU time | 22.6 seconds |
| Started | Oct 03 04:38:01 AM UTC 24 |
| Finished | Oct 03 04:38:25 AM UTC 24 |
| Peak memory | 266616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553067733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.553067733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/3.alert_handler_sec_cm.3258547134 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 697160632 ps |
| CPU time | 17.38 seconds |
| Started | Oct 03 04:38:27 AM UTC 24 |
| Finished | Oct 03 04:38:45 AM UTC 24 |
| Peak memory | 292876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258547134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3258547134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/3.alert_handler_smoke.4265637262 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 662450710 ps |
| CPU time | 39.11 seconds |
| Started | Oct 03 04:37:59 AM UTC 24 |
| Finished | Oct 03 04:38:39 AM UTC 24 |
| Peak memory | 266836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265637262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.4265637262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/3.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/30.alert_handler_entropy.337708127 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 67775274910 ps |
| CPU time | 2450.31 seconds |
| Started | Oct 03 05:28:20 AM UTC 24 |
| Finished | Oct 03 06:09:38 AM UTC 24 |
| Peak memory | 302052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337708127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.337708127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/30.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_alert_accum.3483681000 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 3350719406 ps |
| CPU time | 69.82 seconds |
| Started | Oct 03 05:28:05 AM UTC 24 |
| Finished | Oct 03 05:29:17 AM UTC 24 |
| Peak memory | 266636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483681000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3483681000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/30.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_intr_timeout.1253887948 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 2503042314 ps |
| CPU time | 52.53 seconds |
| Started | Oct 03 05:28:02 AM UTC 24 |
| Finished | Oct 03 05:28:56 AM UTC 24 |
| Peak memory | 260760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253887948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1253887948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/30.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg.3042050664 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 55364604657 ps |
| CPU time | 1470.61 seconds |
| Started | Oct 03 05:28:31 AM UTC 24 |
| Finished | Oct 03 05:53:18 AM UTC 24 |
| Peak memory | 299476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042050664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3042050664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/30.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg_stub_clk.2509759962 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 792347968919 ps |
| CPU time | 2570.31 seconds |
| Started | Oct 03 05:28:52 AM UTC 24 |
| Finished | Oct 03 06:12:10 AM UTC 24 |
| Peak memory | 298036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509759962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2509759962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/30.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_alerts.2988074662 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 950852121 ps |
| CPU time | 38.64 seconds |
| Started | Oct 03 05:27:24 AM UTC 24 |
| Finished | Oct 03 05:28:04 AM UTC 24 |
| Peak memory | 266872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988074662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2988074662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/30.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_classes.4103589585 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 262681497 ps |
| CPU time | 8.96 seconds |
| Started | Oct 03 05:27:51 AM UTC 24 |
| Finished | Oct 03 05:28:01 AM UTC 24 |
| Peak memory | 260444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103589585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.4103589585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/30.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/30.alert_handler_sig_int_fail.2888244001 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 243744590 ps |
| CPU time | 16.58 seconds |
| Started | Oct 03 05:28:12 AM UTC 24 |
| Finished | Oct 03 05:28:30 AM UTC 24 |
| Peak memory | 260428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888244001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2888244001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/30.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/30.alert_handler_smoke.3301164594 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 4533777048 ps |
| CPU time | 108.43 seconds |
| Started | Oct 03 05:27:04 AM UTC 24 |
| Finished | Oct 03 05:28:55 AM UTC 24 |
| Peak memory | 266712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301164594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3301164594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/30.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all.3497911455 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 4172302052 ps |
| CPU time | 56.81 seconds |
| Started | Oct 03 05:28:55 AM UTC 24 |
| Finished | Oct 03 05:29:53 AM UTC 24 |
| Peak memory | 266716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497911455 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_stress_all.3497911455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/30.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/31.alert_handler_entropy.485902205 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 53856420585 ps |
| CPU time | 1362.96 seconds |
| Started | Oct 03 05:29:41 AM UTC 24 |
| Finished | Oct 03 05:52:41 AM UTC 24 |
| Peak memory | 299552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485902205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.485902205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/31.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_alert_accum.1520450107 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 209462399 ps |
| CPU time | 14.69 seconds |
| Started | Oct 03 05:29:33 AM UTC 24 |
| Finished | Oct 03 05:29:49 AM UTC 24 |
| Peak memory | 266836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520450107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1520450107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/31.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_intr_timeout.4133410322 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1685729401 ps |
| CPU time | 65.13 seconds |
| Started | Oct 03 05:29:21 AM UTC 24 |
| Finished | Oct 03 05:30:28 AM UTC 24 |
| Peak memory | 260696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133410322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.4133410322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/31.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg.420071701 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 20765741765 ps |
| CPU time | 1343.09 seconds |
| Started | Oct 03 05:29:50 AM UTC 24 |
| Finished | Oct 03 05:52:29 AM UTC 24 |
| Peak memory | 283156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420071701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.420071701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/31.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg_stub_clk.1719612832 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 227166340635 ps |
| CPU time | 3470.2 seconds |
| Started | Oct 03 05:29:53 AM UTC 24 |
| Finished | Oct 03 06:28:25 AM UTC 24 |
| Peak memory | 302060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719612832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1719612832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/31.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/31.alert_handler_ping_timeout.1458574524 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 71728391514 ps |
| CPU time | 276.53 seconds |
| Started | Oct 03 05:29:46 AM UTC 24 |
| Finished | Oct 03 05:34:26 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458574524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1458574524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/31.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_alerts.2207473219 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 730373720 ps |
| CPU time | 17.34 seconds |
| Started | Oct 03 05:29:01 AM UTC 24 |
| Finished | Oct 03 05:29:20 AM UTC 24 |
| Peak memory | 260460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207473219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2207473219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/31.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_classes.1707190341 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 582657807 ps |
| CPU time | 32.73 seconds |
| Started | Oct 03 05:29:18 AM UTC 24 |
| Finished | Oct 03 05:29:52 AM UTC 24 |
| Peak memory | 266572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707190341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1707190341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/31.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/31.alert_handler_sig_int_fail.355572579 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 449922300 ps |
| CPU time | 41.14 seconds |
| Started | Oct 03 05:29:35 AM UTC 24 |
| Finished | Oct 03 05:30:18 AM UTC 24 |
| Peak memory | 260448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355572579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.355572579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/31.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/31.alert_handler_smoke.3271289931 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 253468180 ps |
| CPU time | 33.41 seconds |
| Started | Oct 03 05:28:57 AM UTC 24 |
| Finished | Oct 03 05:29:32 AM UTC 24 |
| Peak memory | 260692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271289931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3271289931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/31.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all.1675596526 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 10233848975 ps |
| CPU time | 491.57 seconds |
| Started | Oct 03 05:29:54 AM UTC 24 |
| Finished | Oct 03 05:38:13 AM UTC 24 |
| Peak memory | 276944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675596526 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_stress_all.1675596526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/31.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/32.alert_handler_entropy.958361174 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 37715174262 ps |
| CPU time | 1441.7 seconds |
| Started | Oct 03 05:32:05 AM UTC 24 |
| Finished | Oct 03 05:56:23 AM UTC 24 |
| Peak memory | 283092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958361174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.958361174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/32.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_alert_accum.3744947823 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 10524014012 ps |
| CPU time | 368.48 seconds |
| Started | Oct 03 05:31:45 AM UTC 24 |
| Finished | Oct 03 05:37:59 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744947823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3744947823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/32.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_intr_timeout.3434622305 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 1440616300 ps |
| CPU time | 61.77 seconds |
| Started | Oct 03 05:31:24 AM UTC 24 |
| Finished | Oct 03 05:32:27 AM UTC 24 |
| Peak memory | 260696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434622305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3434622305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/32.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg_stub_clk.4138238714 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 243534498008 ps |
| CPU time | 1659.1 seconds |
| Started | Oct 03 05:32:28 AM UTC 24 |
| Finished | Oct 03 06:00:27 AM UTC 24 |
| Peak memory | 283172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138238714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.4138238714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/32.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/32.alert_handler_ping_timeout.1821866210 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 29743653126 ps |
| CPU time | 530.53 seconds |
| Started | Oct 03 05:32:06 AM UTC 24 |
| Finished | Oct 03 05:41:03 AM UTC 24 |
| Peak memory | 260572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821866210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1821866210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/32.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_alerts.871933232 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 689057056 ps |
| CPU time | 55.51 seconds |
| Started | Oct 03 05:31:04 AM UTC 24 |
| Finished | Oct 03 05:32:02 AM UTC 24 |
| Peak memory | 260696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871933232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.871933232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/32.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_classes.3585601653 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 4467203031 ps |
| CPU time | 103.8 seconds |
| Started | Oct 03 05:31:08 AM UTC 24 |
| Finished | Oct 03 05:32:55 AM UTC 24 |
| Peak memory | 260660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585601653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3585601653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/32.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/32.alert_handler_sig_int_fail.2389330759 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 42542154 ps |
| CPU time | 8.71 seconds |
| Started | Oct 03 05:32:04 AM UTC 24 |
| Finished | Oct 03 05:32:14 AM UTC 24 |
| Peak memory | 260500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389330759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.2389330759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/32.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/32.alert_handler_smoke.3683290803 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 3153870011 ps |
| CPU time | 33.11 seconds |
| Started | Oct 03 05:30:29 AM UTC 24 |
| Finished | Oct 03 05:31:04 AM UTC 24 |
| Peak memory | 266648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683290803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3683290803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/32.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/33.alert_handler_entropy.1831684900 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 26631214079 ps |
| CPU time | 2183.16 seconds |
| Started | Oct 03 05:34:27 AM UTC 24 |
| Finished | Oct 03 06:11:17 AM UTC 24 |
| Peak memory | 285932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831684900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1831684900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/33.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_alert_accum.3469567677 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 2905323919 ps |
| CPU time | 62.36 seconds |
| Started | Oct 03 05:33:52 AM UTC 24 |
| Finished | Oct 03 05:34:56 AM UTC 24 |
| Peak memory | 266636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469567677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3469567677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/33.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_intr_timeout.1966649036 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 274379393 ps |
| CPU time | 41.57 seconds |
| Started | Oct 03 05:33:41 AM UTC 24 |
| Finished | Oct 03 05:34:24 AM UTC 24 |
| Peak memory | 266840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966649036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1966649036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/33.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg.357213947 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 22159008525 ps |
| CPU time | 1469.66 seconds |
| Started | Oct 03 05:34:51 AM UTC 24 |
| Finished | Oct 03 05:59:39 AM UTC 24 |
| Peak memory | 283084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357213947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.357213947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/33.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg_stub_clk.2736000270 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 21375662763 ps |
| CPU time | 599.19 seconds |
| Started | Oct 03 05:34:53 AM UTC 24 |
| Finished | Oct 03 05:45:00 AM UTC 24 |
| Peak memory | 276956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736000270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2736000270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/33.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/33.alert_handler_ping_timeout.1903084406 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 11920903773 ps |
| CPU time | 564.51 seconds |
| Started | Oct 03 05:34:32 AM UTC 24 |
| Finished | Oct 03 05:44:03 AM UTC 24 |
| Peak memory | 266716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903084406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1903084406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_alerts.313035251 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 493927006 ps |
| CPU time | 40.2 seconds |
| Started | Oct 03 05:33:09 AM UTC 24 |
| Finished | Oct 03 05:33:51 AM UTC 24 |
| Peak memory | 266572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313035251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.313035251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/33.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_classes.1082361657 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 603285942 ps |
| CPU time | 19.53 seconds |
| Started | Oct 03 05:33:20 AM UTC 24 |
| Finished | Oct 03 05:33:40 AM UTC 24 |
| Peak memory | 264756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082361657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1082361657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/33.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/33.alert_handler_sig_int_fail.817565414 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 701475746 ps |
| CPU time | 22.53 seconds |
| Started | Oct 03 05:34:25 AM UTC 24 |
| Finished | Oct 03 05:34:50 AM UTC 24 |
| Peak memory | 266612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817565414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.817565414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/33.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/33.alert_handler_smoke.3298625183 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 840399411 ps |
| CPU time | 19.89 seconds |
| Started | Oct 03 05:32:57 AM UTC 24 |
| Finished | Oct 03 05:33:19 AM UTC 24 |
| Peak memory | 264536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298625183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3298625183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/33.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all_with_rand_reset.1153981759 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 15434603596 ps |
| CPU time | 479.3 seconds |
| Started | Oct 03 05:35:11 AM UTC 24 |
| Finished | Oct 03 05:43:17 AM UTC 24 |
| Peak memory | 283288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1153981759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.a lert_handler_stress_all_with_rand_reset.1153981759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/33.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/34.alert_handler_entropy.2111245885 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 7264432462 ps |
| CPU time | 748.71 seconds |
| Started | Oct 03 05:37:01 AM UTC 24 |
| Finished | Oct 03 05:49:39 AM UTC 24 |
| Peak memory | 283092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111245885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2111245885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/34.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_alert_accum.2135024837 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 4106986188 ps |
| CPU time | 334.18 seconds |
| Started | Oct 03 05:36:10 AM UTC 24 |
| Finished | Oct 03 05:41:50 AM UTC 24 |
| Peak memory | 262868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135024837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2135024837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/34.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_intr_timeout.2745933145 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 1935354676 ps |
| CPU time | 54.42 seconds |
| Started | Oct 03 05:36:06 AM UTC 24 |
| Finished | Oct 03 05:37:03 AM UTC 24 |
| Peak memory | 266576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745933145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2745933145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/34.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg.806104676 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 33858804488 ps |
| CPU time | 1110.07 seconds |
| Started | Oct 03 05:37:14 AM UTC 24 |
| Finished | Oct 03 05:55:58 AM UTC 24 |
| Peak memory | 283164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806104676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.806104676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/34.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg_stub_clk.985178944 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 9688226527 ps |
| CPU time | 995.1 seconds |
| Started | Oct 03 05:37:47 AM UTC 24 |
| Finished | Oct 03 05:54:35 AM UTC 24 |
| Peak memory | 283092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985178944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.985178944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/34.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/34.alert_handler_ping_timeout.2685578762 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 13638934276 ps |
| CPU time | 492.45 seconds |
| Started | Oct 03 05:37:03 AM UTC 24 |
| Finished | Oct 03 05:45:22 AM UTC 24 |
| Peak memory | 260644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685578762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2685578762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/34.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_alerts.3037180472 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 285617697 ps |
| CPU time | 37.79 seconds |
| Started | Oct 03 05:35:42 AM UTC 24 |
| Finished | Oct 03 05:36:21 AM UTC 24 |
| Peak memory | 266596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037180472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3037180472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/34.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_classes.752147120 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 72270799 ps |
| CPU time | 11.3 seconds |
| Started | Oct 03 05:35:57 AM UTC 24 |
| Finished | Oct 03 05:36:09 AM UTC 24 |
| Peak memory | 260728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752147120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.752147120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/34.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/34.alert_handler_sig_int_fail.2407485606 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 195231640 ps |
| CPU time | 37.1 seconds |
| Started | Oct 03 05:36:22 AM UTC 24 |
| Finished | Oct 03 05:37:00 AM UTC 24 |
| Peak memory | 260428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407485606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2407485606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/34.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/34.alert_handler_smoke.2194486823 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 2256282581 ps |
| CPU time | 28.69 seconds |
| Started | Oct 03 05:35:26 AM UTC 24 |
| Finished | Oct 03 05:35:56 AM UTC 24 |
| Peak memory | 266636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194486823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2194486823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/34.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all.1643659667 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 45087766287 ps |
| CPU time | 2864.95 seconds |
| Started | Oct 03 05:37:59 AM UTC 24 |
| Finished | Oct 03 06:26:19 AM UTC 24 |
| Peak memory | 302124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643659667 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_stress_all.1643659667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/34.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/35.alert_handler_entropy.629692532 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 102376724566 ps |
| CPU time | 2099.87 seconds |
| Started | Oct 03 05:39:14 AM UTC 24 |
| Finished | Oct 03 06:14:40 AM UTC 24 |
| Peak memory | 295984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629692532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.629692532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/35.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_alert_accum.1248648120 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 3820181667 ps |
| CPU time | 209.35 seconds |
| Started | Oct 03 05:39:07 AM UTC 24 |
| Finished | Oct 03 05:42:40 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248648120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1248648120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/35.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_intr_timeout.1697610132 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 471590493 ps |
| CPU time | 42.24 seconds |
| Started | Oct 03 05:38:54 AM UTC 24 |
| Finished | Oct 03 05:39:38 AM UTC 24 |
| Peak memory | 260432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697610132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1697610132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/35.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg.313957477 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 70153271535 ps |
| CPU time | 1747.41 seconds |
| Started | Oct 03 05:39:23 AM UTC 24 |
| Finished | Oct 03 06:08:52 AM UTC 24 |
| Peak memory | 295372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313957477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.313957477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/35.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg_stub_clk.4065407867 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 47751274417 ps |
| CPU time | 3234.23 seconds |
| Started | Oct 03 05:39:33 AM UTC 24 |
| Finished | Oct 03 06:34:07 AM UTC 24 |
| Peak memory | 302056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065407867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.4065407867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/35.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/35.alert_handler_ping_timeout.850850126 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 2951749489 ps |
| CPU time | 101.62 seconds |
| Started | Oct 03 05:39:17 AM UTC 24 |
| Finished | Oct 03 05:41:01 AM UTC 24 |
| Peak memory | 266716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850850126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.850850126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/35.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_alerts.774420281 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 587780211 ps |
| CPU time | 55.5 seconds |
| Started | Oct 03 05:38:24 AM UTC 24 |
| Finished | Oct 03 05:39:21 AM UTC 24 |
| Peak memory | 266576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774420281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.774420281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/35.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_classes.42818877 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 1020546868 ps |
| CPU time | 57.84 seconds |
| Started | Oct 03 05:38:54 AM UTC 24 |
| Finished | Oct 03 05:39:53 AM UTC 24 |
| Peak memory | 260428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42818877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ran dom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.42818877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/35.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/35.alert_handler_sig_int_fail.2185201492 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 399832241 ps |
| CPU time | 4.59 seconds |
| Started | Oct 03 05:39:11 AM UTC 24 |
| Finished | Oct 03 05:39:16 AM UTC 24 |
| Peak memory | 250452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185201492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2185201492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/35.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/35.alert_handler_smoke.1421968106 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1968597180 ps |
| CPU time | 47.2 seconds |
| Started | Oct 03 05:38:20 AM UTC 24 |
| Finished | Oct 03 05:39:09 AM UTC 24 |
| Peak memory | 266584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421968106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1421968106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/35.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all.4062480249 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 74414204228 ps |
| CPU time | 2403.6 seconds |
| Started | Oct 03 05:39:38 AM UTC 24 |
| Finished | Oct 03 06:20:08 AM UTC 24 |
| Peak memory | 302124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062480249 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_stress_all.4062480249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/35.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/36.alert_handler_entropy.2292121828 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 62824743675 ps |
| CPU time | 1193.03 seconds |
| Started | Oct 03 05:41:06 AM UTC 24 |
| Finished | Oct 03 06:01:15 AM UTC 24 |
| Peak memory | 281308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292121828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2292121828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/36.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_alert_accum.2477157640 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 1347989716 ps |
| CPU time | 149.49 seconds |
| Started | Oct 03 05:41:01 AM UTC 24 |
| Finished | Oct 03 05:43:34 AM UTC 24 |
| Peak memory | 266772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477157640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2477157640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/36.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_intr_timeout.3709567246 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 2429374250 ps |
| CPU time | 58.87 seconds |
| Started | Oct 03 05:40:52 AM UTC 24 |
| Finished | Oct 03 05:41:53 AM UTC 24 |
| Peak memory | 266712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709567246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3709567246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/36.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg.2423327561 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 16999824589 ps |
| CPU time | 884.63 seconds |
| Started | Oct 03 05:41:28 AM UTC 24 |
| Finished | Oct 03 05:56:24 AM UTC 24 |
| Peak memory | 283160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423327561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2423327561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/36.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg_stub_clk.3881014147 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 43204745007 ps |
| CPU time | 1959.87 seconds |
| Started | Oct 03 05:41:33 AM UTC 24 |
| Finished | Oct 03 06:14:35 AM UTC 24 |
| Peak memory | 283368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881014147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3881014147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/36.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/36.alert_handler_ping_timeout.1721915645 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 24060408793 ps |
| CPU time | 421.83 seconds |
| Started | Oct 03 05:41:18 AM UTC 24 |
| Finished | Oct 03 05:48:24 AM UTC 24 |
| Peak memory | 260564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721915645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1721915645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/36.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_alerts.2636891762 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 315458091 ps |
| CPU time | 39.03 seconds |
| Started | Oct 03 05:40:37 AM UTC 24 |
| Finished | Oct 03 05:41:17 AM UTC 24 |
| Peak memory | 266608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636891762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2636891762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/36.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_classes.838125619 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 177425023 ps |
| CPU time | 11.16 seconds |
| Started | Oct 03 05:40:39 AM UTC 24 |
| Finished | Oct 03 05:40:51 AM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838125619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.838125619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/36.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/36.alert_handler_sig_int_fail.1834642208 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 1003028701 ps |
| CPU time | 86.5 seconds |
| Started | Oct 03 05:41:03 AM UTC 24 |
| Finished | Oct 03 05:42:32 AM UTC 24 |
| Peak memory | 260500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834642208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1834642208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/36.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/36.alert_handler_smoke.3098736525 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 4392841565 ps |
| CPU time | 69.05 seconds |
| Started | Oct 03 05:39:54 AM UTC 24 |
| Finished | Oct 03 05:41:05 AM UTC 24 |
| Peak memory | 266712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098736525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3098736525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/36.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/37.alert_handler_entropy.2914886511 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 133050678097 ps |
| CPU time | 2017.23 seconds |
| Started | Oct 03 05:42:55 AM UTC 24 |
| Finished | Oct 03 06:16:57 AM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914886511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2914886511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/37.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_alert_accum.4012961417 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 5199448661 ps |
| CPU time | 163.41 seconds |
| Started | Oct 03 05:42:33 AM UTC 24 |
| Finished | Oct 03 05:45:19 AM UTC 24 |
| Peak memory | 260556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012961417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.4012961417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/37.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_intr_timeout.3346901254 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 277432598 ps |
| CPU time | 41.08 seconds |
| Started | Oct 03 05:42:28 AM UTC 24 |
| Finished | Oct 03 05:43:10 AM UTC 24 |
| Peak memory | 260436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346901254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3346901254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/37.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg_stub_clk.3210008939 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 266793186181 ps |
| CPU time | 1153 seconds |
| Started | Oct 03 05:43:06 AM UTC 24 |
| Finished | Oct 03 06:02:33 AM UTC 24 |
| Peak memory | 299480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210008939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3210008939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/37.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/37.alert_handler_ping_timeout.886068176 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 11766802388 ps |
| CPU time | 508.21 seconds |
| Started | Oct 03 05:42:59 AM UTC 24 |
| Finished | Oct 03 05:51:34 AM UTC 24 |
| Peak memory | 266708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886068176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.886068176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_alerts.12420212 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 294984536 ps |
| CPU time | 6.02 seconds |
| Started | Oct 03 05:42:06 AM UTC 24 |
| Finished | Oct 03 05:42:14 AM UTC 24 |
| Peak memory | 250488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12420212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ran dom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.12420212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/37.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_classes.2818154976 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 16402256983 ps |
| CPU time | 47.99 seconds |
| Started | Oct 03 05:42:15 AM UTC 24 |
| Finished | Oct 03 05:43:04 AM UTC 24 |
| Peak memory | 260660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818154976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2818154976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/37.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/37.alert_handler_sig_int_fail.3396917440 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 456848010 ps |
| CPU time | 22.39 seconds |
| Started | Oct 03 05:42:41 AM UTC 24 |
| Finished | Oct 03 05:43:05 AM UTC 24 |
| Peak memory | 266572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396917440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3396917440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/37.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/37.alert_handler_smoke.841697387 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 608497093 ps |
| CPU time | 31.88 seconds |
| Started | Oct 03 05:41:54 AM UTC 24 |
| Finished | Oct 03 05:42:27 AM UTC 24 |
| Peak memory | 266576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841697387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.841697387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/37.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/37.alert_handler_stress_all.3143271810 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 45748521956 ps |
| CPU time | 1453.83 seconds |
| Started | Oct 03 05:43:11 AM UTC 24 |
| Finished | Oct 03 06:07:44 AM UTC 24 |
| Peak memory | 299472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143271810 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_stress_all.3143271810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/37.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/38.alert_handler_entropy.3002571398 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 181769511525 ps |
| CPU time | 2586.21 seconds |
| Started | Oct 03 05:44:51 AM UTC 24 |
| Finished | Oct 03 06:28:27 AM UTC 24 |
| Peak memory | 302048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002571398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3002571398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/38.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_alert_accum.2062891510 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 48253036414 ps |
| CPU time | 196.3 seconds |
| Started | Oct 03 05:44:04 AM UTC 24 |
| Finished | Oct 03 05:47:23 AM UTC 24 |
| Peak memory | 266772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062891510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2062891510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/38.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_intr_timeout.3941525943 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 13148595173 ps |
| CPU time | 58.3 seconds |
| Started | Oct 03 05:43:58 AM UTC 24 |
| Finished | Oct 03 05:44:57 AM UTC 24 |
| Peak memory | 266968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941525943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3941525943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/38.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg_stub_clk.3653356702 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 37602737716 ps |
| CPU time | 2782.16 seconds |
| Started | Oct 03 05:45:10 AM UTC 24 |
| Finished | Oct 03 06:32:06 AM UTC 24 |
| Peak memory | 298036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653356702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3653356702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/38.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/38.alert_handler_ping_timeout.4224379873 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 34663602116 ps |
| CPU time | 387.5 seconds |
| Started | Oct 03 05:44:58 AM UTC 24 |
| Finished | Oct 03 05:51:31 AM UTC 24 |
| Peak memory | 260572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224379873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.4224379873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_alerts.4161466305 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 3640454906 ps |
| CPU time | 68.99 seconds |
| Started | Oct 03 05:43:39 AM UTC 24 |
| Finished | Oct 03 05:44:50 AM UTC 24 |
| Peak memory | 266936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161466305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.4161466305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/38.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_classes.3214846401 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1121395017 ps |
| CPU time | 52.39 seconds |
| Started | Oct 03 05:43:53 AM UTC 24 |
| Finished | Oct 03 05:44:48 AM UTC 24 |
| Peak memory | 266868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214846401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3214846401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/38.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/38.alert_handler_sig_int_fail.3259773362 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 468421776 ps |
| CPU time | 45.65 seconds |
| Started | Oct 03 05:44:48 AM UTC 24 |
| Finished | Oct 03 05:45:35 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259773362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3259773362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/38.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/38.alert_handler_smoke.2216449756 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 187123811 ps |
| CPU time | 21.71 seconds |
| Started | Oct 03 05:43:34 AM UTC 24 |
| Finished | Oct 03 05:43:57 AM UTC 24 |
| Peak memory | 266584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216449756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2216449756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/38.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all.3628746070 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 383633979 ps |
| CPU time | 46.81 seconds |
| Started | Oct 03 05:45:20 AM UTC 24 |
| Finished | Oct 03 05:46:08 AM UTC 24 |
| Peak memory | 266716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628746070 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_stress_all.3628746070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/38.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all_with_rand_reset.3785597664 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 7337509001 ps |
| CPU time | 178.44 seconds |
| Started | Oct 03 05:45:22 AM UTC 24 |
| Finished | Oct 03 05:48:24 AM UTC 24 |
| Peak memory | 277076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3785597664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.a lert_handler_stress_all_with_rand_reset.3785597664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/38.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_alert_accum.3056612426 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 3553569612 ps |
| CPU time | 197.51 seconds |
| Started | Oct 03 05:46:11 AM UTC 24 |
| Finished | Oct 03 05:49:32 AM UTC 24 |
| Peak memory | 266636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056612426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3056612426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/39.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_intr_timeout.2587174025 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 305167135 ps |
| CPU time | 20.54 seconds |
| Started | Oct 03 05:46:09 AM UTC 24 |
| Finished | Oct 03 05:46:31 AM UTC 24 |
| Peak memory | 260504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587174025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.2587174025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/39.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg.1599335635 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 37628906668 ps |
| CPU time | 2511.02 seconds |
| Started | Oct 03 05:47:24 AM UTC 24 |
| Finished | Oct 03 06:29:44 AM UTC 24 |
| Peak memory | 302052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599335635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1599335635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/39.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg_stub_clk.107451579 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 58914964554 ps |
| CPU time | 3200.25 seconds |
| Started | Oct 03 05:47:37 AM UTC 24 |
| Finished | Oct 03 06:41:35 AM UTC 24 |
| Peak memory | 302056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107451579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.107451579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/39.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/39.alert_handler_ping_timeout.1514725683 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 16190304154 ps |
| CPU time | 366.61 seconds |
| Started | Oct 03 05:47:06 AM UTC 24 |
| Finished | Oct 03 05:53:18 AM UTC 24 |
| Peak memory | 260636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514725683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1514725683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/39.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_alerts.3384605188 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 42679369 ps |
| CPU time | 6.11 seconds |
| Started | Oct 03 05:45:37 AM UTC 24 |
| Finished | Oct 03 05:45:45 AM UTC 24 |
| Peak memory | 260728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384605188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3384605188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/39.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_classes.945043925 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 273033706 ps |
| CPU time | 23.51 seconds |
| Started | Oct 03 05:45:46 AM UTC 24 |
| Finished | Oct 03 05:46:10 AM UTC 24 |
| Peak memory | 264632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945043925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.945043925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/39.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/39.alert_handler_sig_int_fail.3821070345 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1329622297 ps |
| CPU time | 63.61 seconds |
| Started | Oct 03 05:46:31 AM UTC 24 |
| Finished | Oct 03 05:47:36 AM UTC 24 |
| Peak memory | 266684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821070345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3821070345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/39.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/39.alert_handler_smoke.1650490128 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 3474822498 ps |
| CPU time | 85.96 seconds |
| Started | Oct 03 05:45:37 AM UTC 24 |
| Finished | Oct 03 05:47:05 AM UTC 24 |
| Peak memory | 266652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650490128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.1650490128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/39.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all.2794584598 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 3913777406 ps |
| CPU time | 430.3 seconds |
| Started | Oct 03 05:47:37 AM UTC 24 |
| Finished | Oct 03 05:54:53 AM UTC 24 |
| Peak memory | 276880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794584598 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_stress_all.2794584598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/39.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all_with_rand_reset.1404877943 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 2976785188 ps |
| CPU time | 426.39 seconds |
| Started | Oct 03 05:48:00 AM UTC 24 |
| Finished | Oct 03 05:55:12 AM UTC 24 |
| Peak memory | 279128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1404877943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.a lert_handler_stress_all_with_rand_reset.1404877943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/39.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/4.alert_handler_alert_accum_saturation.1910343002 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 40567601 ps |
| CPU time | 4.17 seconds |
| Started | Oct 03 04:38:44 AM UTC 24 |
| Finished | Oct 03 04:38:50 AM UTC 24 |
| Peak memory | 260776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910343002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1910343002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy.1054537917 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 172116975627 ps |
| CPU time | 2653.3 seconds |
| Started | Oct 03 04:38:35 AM UTC 24 |
| Finished | Oct 03 05:23:19 AM UTC 24 |
| Peak memory | 297956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054537917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1054537917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy_stress.4094867772 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1100620014 ps |
| CPU time | 44.52 seconds |
| Started | Oct 03 04:38:44 AM UTC 24 |
| Finished | Oct 03 04:39:30 AM UTC 24 |
| Peak memory | 260436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094867772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.4094867772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_alert_accum.3039132791 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 6114795224 ps |
| CPU time | 173.4 seconds |
| Started | Oct 03 04:38:32 AM UTC 24 |
| Finished | Oct 03 04:41:29 AM UTC 24 |
| Peak memory | 266696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039132791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3039132791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_intr_timeout.1223013305 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 543019694 ps |
| CPU time | 9.57 seconds |
| Started | Oct 03 04:38:32 AM UTC 24 |
| Finished | Oct 03 04:38:43 AM UTC 24 |
| Peak memory | 260700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223013305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1223013305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg_stub_clk.1039461578 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 12439612231 ps |
| CPU time | 1300.18 seconds |
| Started | Oct 03 04:38:43 AM UTC 24 |
| Finished | Oct 03 05:00:40 AM UTC 24 |
| Peak memory | 299480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039461578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1039461578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_alerts.1686132802 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 87014174 ps |
| CPU time | 14.27 seconds |
| Started | Oct 03 04:38:28 AM UTC 24 |
| Finished | Oct 03 04:38:43 AM UTC 24 |
| Peak memory | 264700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686132802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1686132802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/4.alert_handler_sec_cm.2975938079 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 432796309 ps |
| CPU time | 38.04 seconds |
| Started | Oct 03 04:38:51 AM UTC 24 |
| Finished | Oct 03 04:39:30 AM UTC 24 |
| Peak memory | 294788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975938079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2975938079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/4.alert_handler_sig_int_fail.2860759768 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 602452882 ps |
| CPU time | 45.22 seconds |
| Started | Oct 03 04:38:33 AM UTC 24 |
| Finished | Oct 03 04:39:21 AM UTC 24 |
| Peak memory | 266680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860759768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2860759768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/4.alert_handler_smoke.694403076 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 504983556 ps |
| CPU time | 26.38 seconds |
| Started | Oct 03 04:38:27 AM UTC 24 |
| Finished | Oct 03 04:38:54 AM UTC 24 |
| Peak memory | 260700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694403076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.694403076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all.1874004871 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 89773852098 ps |
| CPU time | 2883.23 seconds |
| Started | Oct 03 04:38:44 AM UTC 24 |
| Finished | Oct 03 05:27:21 AM UTC 24 |
| Peak memory | 302044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874004871 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_stress_all.1874004871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/4.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/40.alert_handler_entropy.1038443807 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 34086093274 ps |
| CPU time | 846.31 seconds |
| Started | Oct 03 05:48:57 AM UTC 24 |
| Finished | Oct 03 06:03:14 AM UTC 24 |
| Peak memory | 283164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038443807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1038443807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/40.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_alert_accum.3381100169 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 1821226763 ps |
| CPU time | 245.43 seconds |
| Started | Oct 03 05:48:42 AM UTC 24 |
| Finished | Oct 03 05:52:52 AM UTC 24 |
| Peak memory | 266572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381100169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3381100169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/40.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_intr_timeout.3985546590 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 62201196 ps |
| CPU time | 13.08 seconds |
| Started | Oct 03 05:48:41 AM UTC 24 |
| Finished | Oct 03 05:48:55 AM UTC 24 |
| Peak memory | 260696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985546590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3985546590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/40.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg.645676428 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 6098681242 ps |
| CPU time | 603.04 seconds |
| Started | Oct 03 05:49:34 AM UTC 24 |
| Finished | Oct 03 05:59:44 AM UTC 24 |
| Peak memory | 283088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645676428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.645676428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/40.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg_stub_clk.1040292008 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 87912603531 ps |
| CPU time | 3196.59 seconds |
| Started | Oct 03 05:49:42 AM UTC 24 |
| Finished | Oct 03 06:43:36 AM UTC 24 |
| Peak memory | 302052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040292008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1040292008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/40.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/40.alert_handler_ping_timeout.1649336049 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 55684890898 ps |
| CPU time | 566.73 seconds |
| Started | Oct 03 05:48:59 AM UTC 24 |
| Finished | Oct 03 05:58:33 AM UTC 24 |
| Peak memory | 260644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649336049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1649336049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/40.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_alerts.3496556096 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 338204687 ps |
| CPU time | 13.99 seconds |
| Started | Oct 03 05:48:25 AM UTC 24 |
| Finished | Oct 03 05:48:40 AM UTC 24 |
| Peak memory | 260728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496556096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3496556096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/40.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_classes.3532158695 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 1196371107 ps |
| CPU time | 19.51 seconds |
| Started | Oct 03 05:48:25 AM UTC 24 |
| Finished | Oct 03 05:48:46 AM UTC 24 |
| Peak memory | 260724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532158695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3532158695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/40.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/40.alert_handler_sig_int_fail.2354668936 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 1516458559 ps |
| CPU time | 76.64 seconds |
| Started | Oct 03 05:48:46 AM UTC 24 |
| Finished | Oct 03 05:50:05 AM UTC 24 |
| Peak memory | 266644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354668936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2354668936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/40.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/40.alert_handler_smoke.1625759108 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 2121477976 ps |
| CPU time | 40.38 seconds |
| Started | Oct 03 05:48:00 AM UTC 24 |
| Finished | Oct 03 05:48:41 AM UTC 24 |
| Peak memory | 260704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625759108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1625759108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/40.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/41.alert_handler_entropy.2816008473 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 15212276065 ps |
| CPU time | 1837.39 seconds |
| Started | Oct 03 05:51:03 AM UTC 24 |
| Finished | Oct 03 06:22:05 AM UTC 24 |
| Peak memory | 299472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816008473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2816008473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/41.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_alert_accum.3168230239 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 6180248292 ps |
| CPU time | 115.8 seconds |
| Started | Oct 03 05:50:53 AM UTC 24 |
| Finished | Oct 03 05:52:51 AM UTC 24 |
| Peak memory | 266700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168230239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3168230239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/41.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_intr_timeout.946596389 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 120788398 ps |
| CPU time | 6.84 seconds |
| Started | Oct 03 05:50:43 AM UTC 24 |
| Finished | Oct 03 05:50:52 AM UTC 24 |
| Peak memory | 250488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946596389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.946596389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/41.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg.1907986862 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 23499695841 ps |
| CPU time | 1499.32 seconds |
| Started | Oct 03 05:51:08 AM UTC 24 |
| Finished | Oct 03 06:16:24 AM UTC 24 |
| Peak memory | 283164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907986862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1907986862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/41.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg_stub_clk.530911516 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 37486106581 ps |
| CPU time | 2401.33 seconds |
| Started | Oct 03 05:51:32 AM UTC 24 |
| Finished | Oct 03 06:32:02 AM UTC 24 |
| Peak memory | 302056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530911516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.530911516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/41.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/41.alert_handler_ping_timeout.1921707681 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 18836134740 ps |
| CPU time | 166.2 seconds |
| Started | Oct 03 05:51:06 AM UTC 24 |
| Finished | Oct 03 05:53:55 AM UTC 24 |
| Peak memory | 264932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921707681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1921707681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/41.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_alerts.1151905035 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 1859744673 ps |
| CPU time | 23.2 seconds |
| Started | Oct 03 05:50:18 AM UTC 24 |
| Finished | Oct 03 05:50:43 AM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151905035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1151905035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/41.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_classes.2208338223 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 406951463 ps |
| CPU time | 12.99 seconds |
| Started | Oct 03 05:50:39 AM UTC 24 |
| Finished | Oct 03 05:50:53 AM UTC 24 |
| Peak memory | 260724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208338223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2208338223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/41.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/41.alert_handler_sig_int_fail.3047000133 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 78777070 ps |
| CPU time | 9.33 seconds |
| Started | Oct 03 05:50:55 AM UTC 24 |
| Finished | Oct 03 05:51:05 AM UTC 24 |
| Peak memory | 250452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047000133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3047000133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/41.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/41.alert_handler_smoke.208537160 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 4951358460 ps |
| CPU time | 59.53 seconds |
| Started | Oct 03 05:50:06 AM UTC 24 |
| Finished | Oct 03 05:51:07 AM UTC 24 |
| Peak memory | 260636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208537160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.208537160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/41.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all.2711826475 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 8861665022 ps |
| CPU time | 818.82 seconds |
| Started | Oct 03 05:51:37 AM UTC 24 |
| Finished | Oct 03 06:05:26 AM UTC 24 |
| Peak memory | 283356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711826475 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_stress_all.2711826475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/41.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all_with_rand_reset.1895460009 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 9968847793 ps |
| CPU time | 651.01 seconds |
| Started | Oct 03 05:51:37 AM UTC 24 |
| Finished | Oct 03 06:02:37 AM UTC 24 |
| Peak memory | 293528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1895460009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.a lert_handler_stress_all_with_rand_reset.1895460009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/41.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/42.alert_handler_entropy.3192532320 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 83118968031 ps |
| CPU time | 2869 seconds |
| Started | Oct 03 05:53:17 AM UTC 24 |
| Finished | Oct 03 06:41:39 AM UTC 24 |
| Peak memory | 302316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192532320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3192532320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/42.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_alert_accum.2762821265 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 2863911994 ps |
| CPU time | 83.48 seconds |
| Started | Oct 03 05:52:52 AM UTC 24 |
| Finished | Oct 03 05:54:18 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762821265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2762821265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/42.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_intr_timeout.4128133249 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 530631241 ps |
| CPU time | 31.09 seconds |
| Started | Oct 03 05:52:49 AM UTC 24 |
| Finished | Oct 03 05:53:21 AM UTC 24 |
| Peak memory | 260504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128133249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.4128133249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/42.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg.923343402 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 180033285488 ps |
| CPU time | 2984.19 seconds |
| Started | Oct 03 05:53:21 AM UTC 24 |
| Finished | Oct 03 06:43:40 AM UTC 24 |
| Peak memory | 302116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923343402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.923343402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/42.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg_stub_clk.1095648428 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 29265848876 ps |
| CPU time | 2284.23 seconds |
| Started | Oct 03 05:53:22 AM UTC 24 |
| Finished | Oct 03 06:31:54 AM UTC 24 |
| Peak memory | 283364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095648428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1095648428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/42.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/42.alert_handler_ping_timeout.2360985415 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 31809583175 ps |
| CPU time | 278.29 seconds |
| Started | Oct 03 05:53:21 AM UTC 24 |
| Finished | Oct 03 05:58:03 AM UTC 24 |
| Peak memory | 260564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360985415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2360985415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/42.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_alerts.2068828345 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 10612258193 ps |
| CPU time | 87.96 seconds |
| Started | Oct 03 05:52:40 AM UTC 24 |
| Finished | Oct 03 05:54:10 AM UTC 24 |
| Peak memory | 266808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068828345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2068828345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/42.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_classes.1685279194 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 3371862718 ps |
| CPU time | 85.78 seconds |
| Started | Oct 03 05:52:44 AM UTC 24 |
| Finished | Oct 03 05:54:12 AM UTC 24 |
| Peak memory | 260524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685279194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1685279194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/42.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/42.alert_handler_sig_int_fail.395213563 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 2752588916 ps |
| CPU time | 52.25 seconds |
| Started | Oct 03 05:52:53 AM UTC 24 |
| Finished | Oct 03 05:53:48 AM UTC 24 |
| Peak memory | 266744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395213563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.395213563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/42.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/42.alert_handler_smoke.2354465066 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 323311349 ps |
| CPU time | 42.73 seconds |
| Started | Oct 03 05:52:31 AM UTC 24 |
| Finished | Oct 03 05:53:16 AM UTC 24 |
| Peak memory | 266848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354465066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2354465066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/42.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all.312899466 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 16501068103 ps |
| CPU time | 1831.33 seconds |
| Started | Oct 03 05:53:49 AM UTC 24 |
| Finished | Oct 03 06:24:43 AM UTC 24 |
| Peak memory | 299796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312899466 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_stress_all.312899466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/42.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/43.alert_handler_entropy.1299696968 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 23597186789 ps |
| CPU time | 2062.24 seconds |
| Started | Oct 03 05:54:53 AM UTC 24 |
| Finished | Oct 03 06:29:40 AM UTC 24 |
| Peak memory | 293328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299696968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1299696968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/43.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_alert_accum.2740746909 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 2987907868 ps |
| CPU time | 110.19 seconds |
| Started | Oct 03 05:54:37 AM UTC 24 |
| Finished | Oct 03 05:56:29 AM UTC 24 |
| Peak memory | 260492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740746909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2740746909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/43.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_intr_timeout.956150542 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 381031369 ps |
| CPU time | 33.34 seconds |
| Started | Oct 03 05:54:36 AM UTC 24 |
| Finished | Oct 03 05:55:11 AM UTC 24 |
| Peak memory | 266836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956150542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.956150542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/43.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg.2710925923 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 20818918745 ps |
| CPU time | 1544.19 seconds |
| Started | Oct 03 05:55:12 AM UTC 24 |
| Finished | Oct 03 06:21:15 AM UTC 24 |
| Peak memory | 293404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710925923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.2710925923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/43.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg_stub_clk.1544656787 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 23655977877 ps |
| CPU time | 1413.86 seconds |
| Started | Oct 03 05:55:14 AM UTC 24 |
| Finished | Oct 03 06:19:04 AM UTC 24 |
| Peak memory | 283100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544656787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1544656787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/43.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/43.alert_handler_ping_timeout.3767791925 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 6299826425 ps |
| CPU time | 312.39 seconds |
| Started | Oct 03 05:54:54 AM UTC 24 |
| Finished | Oct 03 06:00:11 AM UTC 24 |
| Peak memory | 260644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767791925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3767791925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/43.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_alerts.1845413015 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 498205958 ps |
| CPU time | 36.83 seconds |
| Started | Oct 03 05:54:13 AM UTC 24 |
| Finished | Oct 03 05:54:51 AM UTC 24 |
| Peak memory | 260472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845413015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1845413015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/43.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_classes.3652184392 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1445266227 ps |
| CPU time | 14.89 seconds |
| Started | Oct 03 05:54:19 AM UTC 24 |
| Finished | Oct 03 05:54:35 AM UTC 24 |
| Peak memory | 260428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652184392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3652184392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/43.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/43.alert_handler_sig_int_fail.491823027 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 260510756 ps |
| CPU time | 45.7 seconds |
| Started | Oct 03 05:54:51 AM UTC 24 |
| Finished | Oct 03 05:55:39 AM UTC 24 |
| Peak memory | 260464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491823027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.491823027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/43.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/43.alert_handler_smoke.3911201687 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 4841965094 ps |
| CPU time | 69.29 seconds |
| Started | Oct 03 05:54:11 AM UTC 24 |
| Finished | Oct 03 05:55:22 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911201687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3911201687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/43.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all.1912226670 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 117051530674 ps |
| CPU time | 2271.64 seconds |
| Started | Oct 03 05:55:23 AM UTC 24 |
| Finished | Oct 03 06:33:42 AM UTC 24 |
| Peak memory | 295456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912226670 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_stress_all.1912226670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/43.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all_with_rand_reset.1508557741 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 10034034970 ps |
| CPU time | 405.44 seconds |
| Started | Oct 03 05:55:40 AM UTC 24 |
| Finished | Oct 03 06:02:31 AM UTC 24 |
| Peak memory | 283216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1508557741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.a lert_handler_stress_all_with_rand_reset.1508557741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/43.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/44.alert_handler_entropy.2784937394 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 15439937767 ps |
| CPU time | 1709.38 seconds |
| Started | Oct 03 05:56:35 AM UTC 24 |
| Finished | Oct 03 06:25:26 AM UTC 24 |
| Peak memory | 299476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784937394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2784937394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/44.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_alert_accum.4053520910 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 5209902520 ps |
| CPU time | 289.12 seconds |
| Started | Oct 03 05:56:30 AM UTC 24 |
| Finished | Oct 03 06:01:24 AM UTC 24 |
| Peak memory | 266772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053520910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.4053520910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/44.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_intr_timeout.178021094 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 668228774 ps |
| CPU time | 69.25 seconds |
| Started | Oct 03 05:56:26 AM UTC 24 |
| Finished | Oct 03 05:57:37 AM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178021094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.178021094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/44.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg.1448275638 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 43959822753 ps |
| CPU time | 2593.88 seconds |
| Started | Oct 03 05:56:44 AM UTC 24 |
| Finished | Oct 03 06:40:29 AM UTC 24 |
| Peak memory | 302052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448275638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1448275638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/44.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg_stub_clk.2114355494 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 22122717883 ps |
| CPU time | 1540.62 seconds |
| Started | Oct 03 05:57:38 AM UTC 24 |
| Finished | Oct 03 06:23:37 AM UTC 24 |
| Peak memory | 283172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114355494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2114355494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/44.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/44.alert_handler_ping_timeout.3010285741 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 18662317498 ps |
| CPU time | 651.94 seconds |
| Started | Oct 03 05:56:44 AM UTC 24 |
| Finished | Oct 03 06:07:44 AM UTC 24 |
| Peak memory | 260644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010285741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3010285741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/44.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_alerts.1040761869 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 1914025581 ps |
| CPU time | 41.03 seconds |
| Started | Oct 03 05:56:00 AM UTC 24 |
| Finished | Oct 03 05:56:43 AM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040761869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1040761869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/44.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_classes.3867246616 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 260016761 ps |
| CPU time | 15.41 seconds |
| Started | Oct 03 05:56:26 AM UTC 24 |
| Finished | Oct 03 05:56:43 AM UTC 24 |
| Peak memory | 260532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867246616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3867246616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/44.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/44.alert_handler_sig_int_fail.2991000845 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 817350045 ps |
| CPU time | 63.62 seconds |
| Started | Oct 03 05:56:33 AM UTC 24 |
| Finished | Oct 03 05:57:38 AM UTC 24 |
| Peak memory | 260428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991000845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2991000845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/44.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/44.alert_handler_smoke.3099341877 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 4124865854 ps |
| CPU time | 50.83 seconds |
| Started | Oct 03 05:55:40 AM UTC 24 |
| Finished | Oct 03 05:56:32 AM UTC 24 |
| Peak memory | 266648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099341877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3099341877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/44.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/45.alert_handler_entropy.3306684756 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 36452439782 ps |
| CPU time | 865.26 seconds |
| Started | Oct 03 05:59:45 AM UTC 24 |
| Finished | Oct 03 06:14:22 AM UTC 24 |
| Peak memory | 283088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306684756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3306684756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/45.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_alert_accum.1005042664 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 5454310626 ps |
| CPU time | 292.93 seconds |
| Started | Oct 03 05:59:04 AM UTC 24 |
| Finished | Oct 03 06:04:01 AM UTC 24 |
| Peak memory | 266772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005042664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1005042664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/45.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_intr_timeout.386233471 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 317278206 ps |
| CPU time | 13.96 seconds |
| Started | Oct 03 05:58:48 AM UTC 24 |
| Finished | Oct 03 05:59:03 AM UTC 24 |
| Peak memory | 260728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386233471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.386233471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/45.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg.2087982986 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 118157865112 ps |
| CPU time | 3552.05 seconds |
| Started | Oct 03 06:00:12 AM UTC 24 |
| Finished | Oct 03 07:00:06 AM UTC 24 |
| Peak memory | 302052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087982986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2087982986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/45.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg_stub_clk.1875395094 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 26592931612 ps |
| CPU time | 1877.24 seconds |
| Started | Oct 03 06:00:16 AM UTC 24 |
| Finished | Oct 03 06:31:56 AM UTC 24 |
| Peak memory | 295384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875395094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1875395094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/45.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/45.alert_handler_ping_timeout.3923674357 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 77109446964 ps |
| CPU time | 631.06 seconds |
| Started | Oct 03 05:59:58 AM UTC 24 |
| Finished | Oct 03 06:10:36 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923674357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3923674357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/45.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_alerts.590426270 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 4332578006 ps |
| CPU time | 80.47 seconds |
| Started | Oct 03 05:58:34 AM UTC 24 |
| Finished | Oct 03 05:59:56 AM UTC 24 |
| Peak memory | 260796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590426270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.590426270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/45.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_classes.771222108 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 125428893 ps |
| CPU time | 11.89 seconds |
| Started | Oct 03 05:58:34 AM UTC 24 |
| Finished | Oct 03 05:58:47 AM UTC 24 |
| Peak memory | 266576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771222108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.771222108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/45.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/45.alert_handler_sig_int_fail.1130312515 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 674603701 ps |
| CPU time | 33.12 seconds |
| Started | Oct 03 05:59:40 AM UTC 24 |
| Finished | Oct 03 06:00:15 AM UTC 24 |
| Peak memory | 260428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130312515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1130312515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/45.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/45.alert_handler_smoke.967481373 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 2690633157 ps |
| CPU time | 28.39 seconds |
| Started | Oct 03 05:58:04 AM UTC 24 |
| Finished | Oct 03 05:58:33 AM UTC 24 |
| Peak memory | 266640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967481373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.967481373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/45.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/46.alert_handler_entropy.2196585675 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 33047879572 ps |
| CPU time | 1114.07 seconds |
| Started | Oct 03 06:01:40 AM UTC 24 |
| Finished | Oct 03 06:20:29 AM UTC 24 |
| Peak memory | 283088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196585675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2196585675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/46.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_alert_accum.217447302 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 18841316267 ps |
| CPU time | 173.53 seconds |
| Started | Oct 03 06:01:25 AM UTC 24 |
| Finished | Oct 03 06:04:21 AM UTC 24 |
| Peak memory | 266804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217447302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.217447302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/46.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_intr_timeout.3758521141 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 254301178 ps |
| CPU time | 24.13 seconds |
| Started | Oct 03 06:01:18 AM UTC 24 |
| Finished | Oct 03 06:01:43 AM UTC 24 |
| Peak memory | 266648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758521141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3758521141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/46.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/46.alert_handler_ping_timeout.3865117711 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 18194448491 ps |
| CPU time | 295.12 seconds |
| Started | Oct 03 06:01:44 AM UTC 24 |
| Finished | Oct 03 06:06:44 AM UTC 24 |
| Peak memory | 260568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865117711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3865117711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_alerts.1091087258 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 18801660 ps |
| CPU time | 3.87 seconds |
| Started | Oct 03 06:00:56 AM UTC 24 |
| Finished | Oct 03 06:01:01 AM UTC 24 |
| Peak memory | 260432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091087258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1091087258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/46.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_classes.2646485930 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 997440075 ps |
| CPU time | 31.84 seconds |
| Started | Oct 03 06:01:02 AM UTC 24 |
| Finished | Oct 03 06:01:36 AM UTC 24 |
| Peak memory | 266572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646485930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2646485930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/46.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/46.alert_handler_smoke.3170332152 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 361730325 ps |
| CPU time | 44.94 seconds |
| Started | Oct 03 06:00:52 AM UTC 24 |
| Finished | Oct 03 06:01:39 AM UTC 24 |
| Peak memory | 266912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170332152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3170332152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/46.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all.1242968017 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 232616849444 ps |
| CPU time | 2140.64 seconds |
| Started | Oct 03 06:02:36 AM UTC 24 |
| Finished | Oct 03 06:38:42 AM UTC 24 |
| Peak memory | 293332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242968017 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_stress_all.1242968017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/46.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/47.alert_handler_entropy.634264581 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 427485900040 ps |
| CPU time | 2519.64 seconds |
| Started | Oct 03 06:03:40 AM UTC 24 |
| Finished | Oct 03 06:46:11 AM UTC 24 |
| Peak memory | 302128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634264581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.634264581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/47.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_alert_accum.1132022972 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 5770859999 ps |
| CPU time | 147.28 seconds |
| Started | Oct 03 06:03:27 AM UTC 24 |
| Finished | Oct 03 06:05:57 AM UTC 24 |
| Peak memory | 260820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132022972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1132022972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/47.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_intr_timeout.3874111236 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 270459778 ps |
| CPU time | 14.77 seconds |
| Started | Oct 03 06:03:16 AM UTC 24 |
| Finished | Oct 03 06:03:32 AM UTC 24 |
| Peak memory | 260432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874111236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3874111236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/47.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg.1872554551 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 32147140512 ps |
| CPU time | 2192.59 seconds |
| Started | Oct 03 06:04:02 AM UTC 24 |
| Finished | Oct 03 06:41:02 AM UTC 24 |
| Peak memory | 283164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872554551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1872554551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/47.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg_stub_clk.1776546644 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 196053336349 ps |
| CPU time | 2325.32 seconds |
| Started | Oct 03 06:04:22 AM UTC 24 |
| Finished | Oct 03 06:43:37 AM UTC 24 |
| Peak memory | 301128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776546644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1776546644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/47.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/47.alert_handler_ping_timeout.3691328860 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 5469961323 ps |
| CPU time | 290.09 seconds |
| Started | Oct 03 06:03:51 AM UTC 24 |
| Finished | Oct 03 06:08:45 AM UTC 24 |
| Peak memory | 260568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691328860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3691328860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/47.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_alerts.2253112443 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 204798958 ps |
| CPU time | 30.59 seconds |
| Started | Oct 03 06:02:55 AM UTC 24 |
| Finished | Oct 03 06:03:27 AM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253112443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2253112443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/47.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_classes.635470200 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 257348041 ps |
| CPU time | 27.44 seconds |
| Started | Oct 03 06:03:10 AM UTC 24 |
| Finished | Oct 03 06:03:38 AM UTC 24 |
| Peak memory | 266680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635470200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.635470200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/47.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/47.alert_handler_sig_int_fail.3129111825 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 755771224 ps |
| CPU time | 15.51 seconds |
| Started | Oct 03 06:03:32 AM UTC 24 |
| Finished | Oct 03 06:03:50 AM UTC 24 |
| Peak memory | 264524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129111825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3129111825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/47.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/47.alert_handler_smoke.190608428 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 379090399 ps |
| CPU time | 23.97 seconds |
| Started | Oct 03 06:02:43 AM UTC 24 |
| Finished | Oct 03 06:03:09 AM UTC 24 |
| Peak memory | 266652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190608428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.190608428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/47.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all.3045583908 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 1272249777 ps |
| CPU time | 118.77 seconds |
| Started | Oct 03 06:05:28 AM UTC 24 |
| Finished | Oct 03 06:07:29 AM UTC 24 |
| Peak memory | 266908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045583908 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_stress_all.3045583908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/47.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all_with_rand_reset.2485985695 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 10701328835 ps |
| CPU time | 303.88 seconds |
| Started | Oct 03 06:05:57 AM UTC 24 |
| Finished | Oct 03 06:11:06 AM UTC 24 |
| Peak memory | 279120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2485985695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.a lert_handler_stress_all_with_rand_reset.2485985695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/47.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/48.alert_handler_entropy.3275698194 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 11007379815 ps |
| CPU time | 667.77 seconds |
| Started | Oct 03 06:07:13 AM UTC 24 |
| Finished | Oct 03 06:18:30 AM UTC 24 |
| Peak memory | 283356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275698194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3275698194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/48.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_alert_accum.809099928 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 1556327266 ps |
| CPU time | 56.18 seconds |
| Started | Oct 03 06:07:01 AM UTC 24 |
| Finished | Oct 03 06:07:59 AM UTC 24 |
| Peak memory | 266600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809099928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.809099928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/48.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_intr_timeout.4102379993 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 183601687 ps |
| CPU time | 26.05 seconds |
| Started | Oct 03 06:06:45 AM UTC 24 |
| Finished | Oct 03 06:07:12 AM UTC 24 |
| Peak memory | 260504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102379993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.4102379993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/48.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg.3020082412 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 14723866426 ps |
| CPU time | 1548.63 seconds |
| Started | Oct 03 06:07:46 AM UTC 24 |
| Finished | Oct 03 06:33:54 AM UTC 24 |
| Peak memory | 295452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020082412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3020082412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/48.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg_stub_clk.3771304532 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 43852908478 ps |
| CPU time | 1556.8 seconds |
| Started | Oct 03 06:07:46 AM UTC 24 |
| Finished | Oct 03 06:34:04 AM UTC 24 |
| Peak memory | 299748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771304532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3771304532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/48.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/48.alert_handler_ping_timeout.1337155724 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 11439645422 ps |
| CPU time | 371.93 seconds |
| Started | Oct 03 06:07:30 AM UTC 24 |
| Finished | Oct 03 06:13:46 AM UTC 24 |
| Peak memory | 260568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337155724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1337155724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/48.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_alerts.339306417 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 1711004938 ps |
| CPU time | 59.33 seconds |
| Started | Oct 03 06:06:11 AM UTC 24 |
| Finished | Oct 03 06:07:13 AM UTC 24 |
| Peak memory | 266648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339306417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.339306417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/48.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_classes.1217763341 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 601458445 ps |
| CPU time | 27.73 seconds |
| Started | Oct 03 06:06:31 AM UTC 24 |
| Finished | Oct 03 06:07:00 AM UTC 24 |
| Peak memory | 260788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217763341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1217763341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/48.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/48.alert_handler_sig_int_fail.1538169391 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 615013853 ps |
| CPU time | 54.39 seconds |
| Started | Oct 03 06:07:13 AM UTC 24 |
| Finished | Oct 03 06:08:09 AM UTC 24 |
| Peak memory | 260428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538169391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1538169391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/48.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/48.alert_handler_smoke.3642630672 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 4624112126 ps |
| CPU time | 29.12 seconds |
| Started | Oct 03 06:05:59 AM UTC 24 |
| Finished | Oct 03 06:06:29 AM UTC 24 |
| Peak memory | 266784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642630672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3642630672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/48.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all_with_rand_reset.657610834 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 2524672225 ps |
| CPU time | 260.55 seconds |
| Started | Oct 03 06:08:00 AM UTC 24 |
| Finished | Oct 03 06:12:24 AM UTC 24 |
| Peak memory | 277208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=657610834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.al ert_handler_stress_all_with_rand_reset.657610834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/48.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/49.alert_handler_entropy.1830744569 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 13781990940 ps |
| CPU time | 1196.32 seconds |
| Started | Oct 03 06:09:13 AM UTC 24 |
| Finished | Oct 03 06:29:24 AM UTC 24 |
| Peak memory | 293404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830744569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1830744569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/49.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_alert_accum.3799342513 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 592872210 ps |
| CPU time | 78.46 seconds |
| Started | Oct 03 06:08:56 AM UTC 24 |
| Finished | Oct 03 06:10:16 AM UTC 24 |
| Peak memory | 266644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799342513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3799342513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/49.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_intr_timeout.1257188642 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 692290134 ps |
| CPU time | 31.91 seconds |
| Started | Oct 03 06:08:51 AM UTC 24 |
| Finished | Oct 03 06:09:25 AM UTC 24 |
| Peak memory | 260504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257188642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.1257188642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/49.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg.1243995818 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 89182049002 ps |
| CPU time | 1482.62 seconds |
| Started | Oct 03 06:09:32 AM UTC 24 |
| Finished | Oct 03 06:34:34 AM UTC 24 |
| Peak memory | 283228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243995818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1243995818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/49.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg_stub_clk.1024183761 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 49903084000 ps |
| CPU time | 2883.39 seconds |
| Started | Oct 03 06:09:41 AM UTC 24 |
| Finished | Oct 03 06:58:19 AM UTC 24 |
| Peak memory | 302388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024183761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1024183761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/49.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/49.alert_handler_ping_timeout.3723246856 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 24821411310 ps |
| CPU time | 441.44 seconds |
| Started | Oct 03 06:09:25 AM UTC 24 |
| Finished | Oct 03 06:16:52 AM UTC 24 |
| Peak memory | 260568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723246856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3723246856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_alerts.18576694 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 659502768 ps |
| CPU time | 58.64 seconds |
| Started | Oct 03 06:08:41 AM UTC 24 |
| Finished | Oct 03 06:09:41 AM UTC 24 |
| Peak memory | 266616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18576694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ran dom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.18576694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/49.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_classes.2803284121 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 326332118 ps |
| CPU time | 43.18 seconds |
| Started | Oct 03 06:08:46 AM UTC 24 |
| Finished | Oct 03 06:09:31 AM UTC 24 |
| Peak memory | 260724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803284121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2803284121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/49.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/49.alert_handler_smoke.1284017646 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 586673104 ps |
| CPU time | 28.51 seconds |
| Started | Oct 03 06:08:10 AM UTC 24 |
| Finished | Oct 03 06:08:40 AM UTC 24 |
| Peak memory | 260512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284017646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1284017646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/49.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all.2604033789 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 54848276174 ps |
| CPU time | 3179.9 seconds |
| Started | Oct 03 06:09:42 AM UTC 24 |
| Finished | Oct 03 07:03:20 AM UTC 24 |
| Peak memory | 302052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604033789 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_stress_all.2604033789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/49.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all_with_rand_reset.2699787714 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 3436408704 ps |
| CPU time | 418.89 seconds |
| Started | Oct 03 06:10:17 AM UTC 24 |
| Finished | Oct 03 06:17:21 AM UTC 24 |
| Peak memory | 279056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2699787714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.a lert_handler_stress_all_with_rand_reset.2699787714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/49.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/5.alert_handler_alert_accum_saturation.4121441217 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 38031484 ps |
| CPU time | 3.83 seconds |
| Started | Oct 03 04:39:32 AM UTC 24 |
| Finished | Oct 03 04:39:37 AM UTC 24 |
| Peak memory | 260700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121441217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.4121441217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/5.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy.2763313621 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 80072728203 ps |
| CPU time | 3182.72 seconds |
| Started | Oct 03 04:39:14 AM UTC 24 |
| Finished | Oct 03 05:32:54 AM UTC 24 |
| Peak memory | 302056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763313621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2763313621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/5.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy_stress.4132962836 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 490020745 ps |
| CPU time | 20.98 seconds |
| Started | Oct 03 04:39:25 AM UTC 24 |
| Finished | Oct 03 04:39:48 AM UTC 24 |
| Peak memory | 260512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132962836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.4132962836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/5.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_alert_accum.2562223943 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 4045372686 ps |
| CPU time | 83.81 seconds |
| Started | Oct 03 04:39:07 AM UTC 24 |
| Finished | Oct 03 04:40:33 AM UTC 24 |
| Peak memory | 260752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562223943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2562223943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/5.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_intr_timeout.1052895391 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1665990993 ps |
| CPU time | 34.9 seconds |
| Started | Oct 03 04:39:05 AM UTC 24 |
| Finished | Oct 03 04:39:41 AM UTC 24 |
| Peak memory | 260436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052895391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1052895391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/5.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg_stub_clk.1643837351 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 76747943867 ps |
| CPU time | 2812.39 seconds |
| Started | Oct 03 04:39:21 AM UTC 24 |
| Finished | Oct 03 05:26:49 AM UTC 24 |
| Peak memory | 302320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643837351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1643837351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/5.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/5.alert_handler_ping_timeout.137210671 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 61326784787 ps |
| CPU time | 502.25 seconds |
| Started | Oct 03 04:39:16 AM UTC 24 |
| Finished | Oct 03 04:47:45 AM UTC 24 |
| Peak memory | 260636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137210671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.137210671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_alerts.1969789047 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1020308230 ps |
| CPU time | 37.95 seconds |
| Started | Oct 03 04:38:55 AM UTC 24 |
| Finished | Oct 03 04:39:34 AM UTC 24 |
| Peak memory | 260692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969789047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1969789047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/5.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_classes.3489531428 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 2106234646 ps |
| CPU time | 34.44 seconds |
| Started | Oct 03 04:38:57 AM UTC 24 |
| Finished | Oct 03 04:39:33 AM UTC 24 |
| Peak memory | 266580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489531428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3489531428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/5.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/5.alert_handler_sig_int_fail.2004213453 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 237271433 ps |
| CPU time | 13.26 seconds |
| Started | Oct 03 04:39:10 AM UTC 24 |
| Finished | Oct 03 04:39:24 AM UTC 24 |
| Peak memory | 264560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004213453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2004213453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/5.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/5.alert_handler_smoke.935429256 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 206303863 ps |
| CPU time | 25.49 seconds |
| Started | Oct 03 04:38:51 AM UTC 24 |
| Finished | Oct 03 04:39:18 AM UTC 24 |
| Peak memory | 266580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935429256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.935429256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/5.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/6.alert_handler_alert_accum_saturation.1455029031 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 147817881 ps |
| CPU time | 5.01 seconds |
| Started | Oct 03 04:40:19 AM UTC 24 |
| Finished | Oct 03 04:40:26 AM UTC 24 |
| Peak memory | 260700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455029031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1455029031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/6.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy_stress.337779807 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1034130605 ps |
| CPU time | 15.91 seconds |
| Started | Oct 03 04:40:14 AM UTC 24 |
| Finished | Oct 03 04:40:31 AM UTC 24 |
| Peak memory | 260504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337779807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.337779807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/6.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_alert_accum.1574220301 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 985495717 ps |
| CPU time | 59.34 seconds |
| Started | Oct 03 04:39:44 AM UTC 24 |
| Finished | Oct 03 04:40:45 AM UTC 24 |
| Peak memory | 266832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574220301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1574220301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/6.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_intr_timeout.1558559202 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 10764231686 ps |
| CPU time | 94.34 seconds |
| Started | Oct 03 04:39:42 AM UTC 24 |
| Finished | Oct 03 04:41:19 AM UTC 24 |
| Peak memory | 266708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558559202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1558559202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/6.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg.2917927121 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 38673037999 ps |
| CPU time | 2440.73 seconds |
| Started | Oct 03 04:39:52 AM UTC 24 |
| Finished | Oct 03 05:21:04 AM UTC 24 |
| Peak memory | 285996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917927121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2917927121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/6.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg_stub_clk.2872632580 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 17852540502 ps |
| CPU time | 1198.87 seconds |
| Started | Oct 03 04:40:06 AM UTC 24 |
| Finished | Oct 03 05:00:21 AM UTC 24 |
| Peak memory | 283092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872632580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2872632580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/6.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/6.alert_handler_ping_timeout.3223701866 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 14426452206 ps |
| CPU time | 215.98 seconds |
| Started | Oct 03 04:39:50 AM UTC 24 |
| Finished | Oct 03 04:43:30 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223701866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3223701866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/6.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_alerts.3167868477 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 121846800 ps |
| CPU time | 7.59 seconds |
| Started | Oct 03 04:39:35 AM UTC 24 |
| Finished | Oct 03 04:39:44 AM UTC 24 |
| Peak memory | 260428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167868477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3167868477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/6.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_classes.1303845170 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 287558399 ps |
| CPU time | 8.85 seconds |
| Started | Oct 03 04:39:37 AM UTC 24 |
| Finished | Oct 03 04:39:47 AM UTC 24 |
| Peak memory | 250224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303845170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1303845170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/6.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/6.alert_handler_sig_int_fail.2674965679 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1052523626 ps |
| CPU time | 40.09 seconds |
| Started | Oct 03 04:39:48 AM UTC 24 |
| Finished | Oct 03 04:40:29 AM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674965679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2674965679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/6.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/6.alert_handler_smoke.106857194 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 2204699420 ps |
| CPU time | 29.99 seconds |
| Started | Oct 03 04:39:34 AM UTC 24 |
| Finished | Oct 03 04:40:05 AM UTC 24 |
| Peak memory | 260500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106857194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.106857194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/6.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/7.alert_handler_alert_accum_saturation.3829116490 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 32110659 ps |
| CPU time | 5.39 seconds |
| Started | Oct 03 04:41:03 AM UTC 24 |
| Finished | Oct 03 04:41:10 AM UTC 24 |
| Peak memory | 260840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829116490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3829116490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/7.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy.538571083 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 35718138214 ps |
| CPU time | 2858.46 seconds |
| Started | Oct 03 04:40:35 AM UTC 24 |
| Finished | Oct 03 05:28:49 AM UTC 24 |
| Peak memory | 302128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538571083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.538571083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/7.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy_stress.1714059389 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 908286944 ps |
| CPU time | 20.41 seconds |
| Started | Oct 03 04:40:47 AM UTC 24 |
| Finished | Oct 03 04:41:09 AM UTC 24 |
| Peak memory | 260508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714059389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1714059389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/7.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_alert_accum.1464558423 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 4888603028 ps |
| CPU time | 151.22 seconds |
| Started | Oct 03 04:40:34 AM UTC 24 |
| Finished | Oct 03 04:43:09 AM UTC 24 |
| Peak memory | 266696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464558423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1464558423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/7.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg.964502634 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 43459099893 ps |
| CPU time | 2656.71 seconds |
| Started | Oct 03 04:40:42 AM UTC 24 |
| Finished | Oct 03 05:25:31 AM UTC 24 |
| Peak memory | 296164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964502634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.964502634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/7.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg_stub_clk.666389053 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 72493357872 ps |
| CPU time | 1497.28 seconds |
| Started | Oct 03 04:40:46 AM UTC 24 |
| Finished | Oct 03 05:06:02 AM UTC 24 |
| Peak memory | 278996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666389053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.666389053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/7.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/7.alert_handler_ping_timeout.3308908149 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 13233564156 ps |
| CPU time | 559.83 seconds |
| Started | Oct 03 04:40:39 AM UTC 24 |
| Finished | Oct 03 04:50:06 AM UTC 24 |
| Peak memory | 260640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308908149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3308908149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/7.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_alerts.3933534993 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1501975734 ps |
| CPU time | 16.91 seconds |
| Started | Oct 03 04:40:27 AM UTC 24 |
| Finished | Oct 03 04:40:45 AM UTC 24 |
| Peak memory | 260428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933534993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3933534993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/7.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_classes.3347533043 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 204961968 ps |
| CPU time | 7.74 seconds |
| Started | Oct 03 04:40:30 AM UTC 24 |
| Finished | Oct 03 04:40:39 AM UTC 24 |
| Peak memory | 250220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347533043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3347533043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/7.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/7.alert_handler_sig_int_fail.3607358790 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 114657349 ps |
| CPU time | 26.66 seconds |
| Started | Oct 03 04:40:34 AM UTC 24 |
| Finished | Oct 03 04:41:02 AM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607358790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3607358790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/7.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/7.alert_handler_smoke.2446617189 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 266235658 ps |
| CPU time | 8.88 seconds |
| Started | Oct 03 04:40:24 AM UTC 24 |
| Finished | Oct 03 04:40:35 AM UTC 24 |
| Peak memory | 266644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446617189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2446617189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/7.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/8.alert_handler_alert_accum_saturation.1854023685 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 37729709 ps |
| CPU time | 4.37 seconds |
| Started | Oct 03 04:42:06 AM UTC 24 |
| Finished | Oct 03 04:42:11 AM UTC 24 |
| Peak memory | 260700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854023685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1854023685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/8.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy.2785281188 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 39223608568 ps |
| CPU time | 2624.13 seconds |
| Started | Oct 03 04:41:21 AM UTC 24 |
| Finished | Oct 03 05:25:36 AM UTC 24 |
| Peak memory | 295908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785281188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2785281188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/8.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy_stress.2248216552 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 844480074 ps |
| CPU time | 16.74 seconds |
| Started | Oct 03 04:41:59 AM UTC 24 |
| Finished | Oct 03 04:42:17 AM UTC 24 |
| Peak memory | 260512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248216552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2248216552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/8.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_alert_accum.4262371093 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 8096003034 ps |
| CPU time | 205.37 seconds |
| Started | Oct 03 04:41:18 AM UTC 24 |
| Finished | Oct 03 04:44:47 AM UTC 24 |
| Peak memory | 262600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262371093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.4262371093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/8.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_intr_timeout.1010837610 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 520887083 ps |
| CPU time | 49.14 seconds |
| Started | Oct 03 04:41:17 AM UTC 24 |
| Finished | Oct 03 04:42:08 AM UTC 24 |
| Peak memory | 260436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010837610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1010837610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/8.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg.1913651919 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 71367845029 ps |
| CPU time | 1813.71 seconds |
| Started | Oct 03 04:41:30 AM UTC 24 |
| Finished | Oct 03 05:12:05 AM UTC 24 |
| Peak memory | 299476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913651919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1913651919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/8.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg_stub_clk.1964817889 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 88250215661 ps |
| CPU time | 2601.63 seconds |
| Started | Oct 03 04:41:33 AM UTC 24 |
| Finished | Oct 03 05:25:26 AM UTC 24 |
| Peak memory | 302052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964817889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1964817889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/8.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/8.alert_handler_ping_timeout.4111460936 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 18797753416 ps |
| CPU time | 164.87 seconds |
| Started | Oct 03 04:41:29 AM UTC 24 |
| Finished | Oct 03 04:44:16 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111460936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.4111460936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_alerts.2137899105 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3913859712 ps |
| CPU time | 85.8 seconds |
| Started | Oct 03 04:41:10 AM UTC 24 |
| Finished | Oct 03 04:42:38 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137899105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2137899105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/8.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_classes.2602132763 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 22527841 ps |
| CPU time | 4.32 seconds |
| Started | Oct 03 04:41:11 AM UTC 24 |
| Finished | Oct 03 04:41:16 AM UTC 24 |
| Peak memory | 250224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602132763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2602132763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/8.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/8.alert_handler_smoke.2852286372 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 630408796 ps |
| CPU time | 12.8 seconds |
| Started | Oct 03 04:41:04 AM UTC 24 |
| Finished | Oct 03 04:41:17 AM UTC 24 |
| Peak memory | 260500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852286372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2852286372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/8.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all.1010875163 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 252918845714 ps |
| CPU time | 1642.31 seconds |
| Started | Oct 03 04:42:00 AM UTC 24 |
| Finished | Oct 03 05:09:43 AM UTC 24 |
| Peak memory | 277012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010875163 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_stress_all.1010875163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/8.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all_with_rand_reset.1192019185 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 14471923292 ps |
| CPU time | 285.36 seconds |
| Started | Oct 03 04:42:06 AM UTC 24 |
| Finished | Oct 03 04:46:55 AM UTC 24 |
| Peak memory | 279188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1192019185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.al ert_handler_stress_all_with_rand_reset.1192019185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/9.alert_handler_alert_accum_saturation.282211510 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 48956183 ps |
| CPU time | 6.77 seconds |
| Started | Oct 03 04:43:23 AM UTC 24 |
| Finished | Oct 03 04:43:31 AM UTC 24 |
| Peak memory | 261032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282211510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.282211510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/9.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy.3358949609 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 59874411750 ps |
| CPU time | 1532.02 seconds |
| Started | Oct 03 04:42:39 AM UTC 24 |
| Finished | Oct 03 05:08:30 AM UTC 24 |
| Peak memory | 293336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358949609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3358949609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/9.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy_stress.3678540088 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 900412602 ps |
| CPU time | 44.67 seconds |
| Started | Oct 03 04:43:09 AM UTC 24 |
| Finished | Oct 03 04:43:55 AM UTC 24 |
| Peak memory | 260508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678540088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3678540088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/9.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_alert_accum.1652691944 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1457203161 ps |
| CPU time | 42.82 seconds |
| Started | Oct 03 04:42:37 AM UTC 24 |
| Finished | Oct 03 04:43:22 AM UTC 24 |
| Peak memory | 266568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652691944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1652691944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/9.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_intr_timeout.683103792 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 265148485 ps |
| CPU time | 30.99 seconds |
| Started | Oct 03 04:42:24 AM UTC 24 |
| Finished | Oct 03 04:42:57 AM UTC 24 |
| Peak memory | 266644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683103792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.683103792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/9.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg.3471473569 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 12894116054 ps |
| CPU time | 671.54 seconds |
| Started | Oct 03 04:42:58 AM UTC 24 |
| Finished | Oct 03 04:54:19 AM UTC 24 |
| Peak memory | 283092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471473569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3471473569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/9.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg_stub_clk.3576020157 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 15853432560 ps |
| CPU time | 1610.16 seconds |
| Started | Oct 03 04:43:07 AM UTC 24 |
| Finished | Oct 03 05:10:17 AM UTC 24 |
| Peak memory | 297696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576020157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3576020157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/9.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/9.alert_handler_ping_timeout.3937411006 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 49440836728 ps |
| CPU time | 406.87 seconds |
| Started | Oct 03 04:42:58 AM UTC 24 |
| Finished | Oct 03 04:49:50 AM UTC 24 |
| Peak memory | 266712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937411006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3937411006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/9.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_alerts.1508150071 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1256824743 ps |
| CPU time | 24.33 seconds |
| Started | Oct 03 04:42:12 AM UTC 24 |
| Finished | Oct 03 04:42:38 AM UTC 24 |
| Peak memory | 260428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508150071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1508150071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/9.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_classes.609416646 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 133226431 ps |
| CPU time | 17.31 seconds |
| Started | Oct 03 04:42:18 AM UTC 24 |
| Finished | Oct 03 04:42:37 AM UTC 24 |
| Peak memory | 260428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609416646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.609416646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/9.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/9.alert_handler_sig_int_fail.3810243930 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 653018212 ps |
| CPU time | 27.53 seconds |
| Started | Oct 03 04:42:39 AM UTC 24 |
| Finished | Oct 03 04:43:07 AM UTC 24 |
| Peak memory | 260432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810243930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3810243930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/9.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/9.alert_handler_smoke.336698183 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 2220247699 ps |
| CPU time | 46.11 seconds |
| Started | Oct 03 04:42:09 AM UTC 24 |
| Finished | Oct 03 04:42:57 AM UTC 24 |
| Peak memory | 266716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336698183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.336698183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/9.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all.2365707144 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 2867457270 ps |
| CPU time | 125.37 seconds |
| Started | Oct 03 04:43:10 AM UTC 24 |
| Finished | Oct 03 04:45:18 AM UTC 24 |
| Peak memory | 266636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365707144 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_stress_all.2365707144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/9.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all_with_rand_reset.4139020197 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 19170768595 ps |
| CPU time | 365.78 seconds |
| Started | Oct 03 04:43:31 AM UTC 24 |
| Finished | Oct 03 04:49:42 AM UTC 24 |
| Peak memory | 279116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4139020197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.al ert_handler_stress_all_with_rand_reset.4139020197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |