Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51641439	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24465345

1

T1

747

T2

2372

T3

107

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	12112853	1			T1	345		T2	1951		T3	45
values[0x0]	31949738	1			T1	895		T2	2396		T3	177
values[0x1]	32044193	1			T1	857		T2	2310		T3	156

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44961025	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

31145759

1

T1

924

T2

2932

T3

134

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	240092	1			T1	11		T11	22		T16	2
valid_sources[0x01]	454235	1			T1	9		T3	3		T10	5
valid_sources[0x02]	586026	1			T1	8		T10	27		T11	25
valid_sources[0x03]	270495	1			T1	15		T10	5		T11	29
valid_sources[0x04]	720191	1			T1	9		T10	6		T11	28
valid_sources[0x05]	242304	1			T1	5		T3	4		T10	42
valid_sources[0x06]	236342	1			T1	9		T10	29		T11	28
valid_sources[0x07]	457401	1			T1	5		T3	2		T10	9
valid_sources[0x08]	265559	1			T1	9		T10	19		T11	29
valid_sources[0x09]	239632	1			T1	7		T10	20		T11	29
valid_sources[0x0a]	669543	1			T1	5		T3	2		T10	4
valid_sources[0x0b]	243192	1			T1	7		T3	1		T10	15
valid_sources[0x0c]	253527	1			T1	5		T10	14		T11	34
valid_sources[0x0d]	239626	1			T1	5		T3	1		T10	8
valid_sources[0x0e]	240181	1			T1	5		T3	1		T10	16
valid_sources[0x0f]	244201	1			T1	4		T3	3		T10	6
valid_sources[0x10]	556452	1			T1	11		T10	16		T11	28
valid_sources[0x11]	247026	1			T1	10		T3	1		T10	6
valid_sources[0x12]	239693	1			T1	12		T3	1		T10	4
valid_sources[0x13]	240048	1			T1	12		T10	28		T11	17
valid_sources[0x14]	237630	1			T1	11		T3	1		T10	23
valid_sources[0x15]	251094	1			T1	8		T3	1		T10	14
valid_sources[0x16]	239938	1			T1	8		T10	26		T11	31
valid_sources[0x17]	240449	1			T1	7		T10	13		T11	28
valid_sources[0x18]	240674	1			T1	6		T3	3		T10	30
valid_sources[0x19]	267916	1			T1	6		T10	8		T11	34
valid_sources[0x1a]	237436	1			T1	5		T10	12		T11	28
valid_sources[0x1b]	536254	1			T1	5		T10	23		T11	22
valid_sources[0x1c]	237853	1			T1	6		T10	5		T11	33
valid_sources[0x1d]	236919	1			T1	5		T10	29		T11	21
valid_sources[0x1e]	239197	1			T1	7		T10	15		T11	34
valid_sources[0x1f]	535475	1			T1	3		T3	2		T10	19
valid_sources[0x20]	239666	1			T1	4		T10	14		T11	34
valid_sources[0x21]	239321	1			T1	11		T3	2		T10	18
valid_sources[0x22]	239187	1			T1	3		T3	1		T10	10
valid_sources[0x23]	238337	1			T1	6		T10	20		T11	45
valid_sources[0x24]	240153	1			T1	6		T3	2		T10	10
valid_sources[0x25]	241304	1			T1	6		T3	2		T10	5
valid_sources[0x26]	235795	1			T1	11		T3	1		T10	10
valid_sources[0x27]	239881	1			T1	6		T10	7		T11	22
valid_sources[0x28]	349355	1			T1	14		T3	6		T10	18
valid_sources[0x29]	564873	1			T1	11		T10	6		T11	31
valid_sources[0x2a]	239138	1			T1	11		T3	2		T10	9
valid_sources[0x2b]	266750	1			T1	5		T10	3		T11	25
valid_sources[0x2c]	240160	1			T1	9		T3	6		T10	30
valid_sources[0x2d]	239974	1			T1	13		T3	5		T10	10
valid_sources[0x2e]	247431	1			T1	12		T3	4		T10	4
valid_sources[0x2f]	249647	1			T1	7		T10	7		T11	18
valid_sources[0x30]	253396	1			T1	11		T10	7		T11	22
valid_sources[0x31]	240718	1			T1	6		T3	1		T10	4
valid_sources[0x32]	240063	1			T1	5		T3	4		T10	11
valid_sources[0x33]	251503	1			T1	4		T3	2		T10	7
valid_sources[0x34]	238881	1			T1	10		T10	32		T11	34
valid_sources[0x35]	269994	1			T1	8		T10	7		T11	26
valid_sources[0x36]	468990	1			T1	6		T10	10		T11	16
valid_sources[0x37]	239160	1			T1	11		T10	3		T11	21
valid_sources[0x38]	243361	1			T1	15		T3	1		T10	16
valid_sources[0x39]	240388	1			T1	10		T10	18		T11	37
valid_sources[0x3a]	240651	1			T1	9		T3	5		T10	47
valid_sources[0x3b]	614675	1			T1	9		T10	5		T11	22
valid_sources[0x3c]	243418	1			T1	4		T10	16		T11	29
valid_sources[0x3d]	241115	1			T1	7		T10	29		T11	27
valid_sources[0x3e]	244387	1			T1	14		T10	14		T11	23
valid_sources[0x3f]	242228	1			T1	6		T10	25		T11	25
valid_sources[0x40]	239820	1			T1	7		T3	12		T10	5
valid_sources[0x41]	237660	1			T1	5		T3	1		T10	32
valid_sources[0x42]	240240	1			T1	12		T10	10		T11	25
valid_sources[0x43]	239377	1			T1	9		T10	16		T11	24
valid_sources[0x44]	240538	1			T1	5		T3	1		T10	18
valid_sources[0x45]	240997	1			T1	5		T10	26		T11	24
valid_sources[0x46]	695875	1			T1	8		T10	1		T11	16
valid_sources[0x47]	246510	1			T1	8		T10	17		T11	27
valid_sources[0x48]	251220	1			T1	6		T10	6		T11	15
valid_sources[0x49]	240413	1			T1	8		T10	13		T11	29
valid_sources[0x4a]	237792	1			T1	12		T3	2		T10	26
valid_sources[0x4b]	237535	1			T1	9		T3	3		T10	39
valid_sources[0x4c]	243062	1			T1	10		T3	6		T10	15
valid_sources[0x4d]	240164	1			T1	5		T10	15		T11	36
valid_sources[0x4e]	241094	1			T1	12		T3	1		T10	27
valid_sources[0x4f]	237336	1			T1	6		T3	2		T10	9
valid_sources[0x50]	236519	1			T1	9		T3	2		T11	31
valid_sources[0x51]	580562	1			T1	5		T3	7		T10	3
valid_sources[0x52]	237073	1			T1	9		T10	20		T11	23
valid_sources[0x53]	237809	1			T1	3		T10	5		T11	27
valid_sources[0x54]	240718	1			T1	9		T3	3		T10	21
valid_sources[0x55]	242047	1			T1	8		T10	9		T11	30
valid_sources[0x56]	269435	1			T1	12		T10	13		T11	25
valid_sources[0x57]	253043	1			T1	4		T10	4		T11	36
valid_sources[0x58]	237931	1			T1	11		T10	12		T11	17
valid_sources[0x59]	242764	1			T1	8		T11	22		T16	4
valid_sources[0x5a]	238127	1			T1	10		T10	21		T11	37
valid_sources[0x5b]	238032	1			T1	2		T3	3		T10	38
valid_sources[0x5c]	237676	1			T1	9		T3	1		T10	16
valid_sources[0x5d]	661606	1			T1	5		T3	1		T10	10
valid_sources[0x5e]	242029	1			T1	13		T10	21		T11	33
valid_sources[0x5f]	675352	1			T1	14		T10	34		T11	22
valid_sources[0x60]	251188	1			T1	11		T10	7		T11	19
valid_sources[0x61]	240421	1			T1	11		T10	15		T11	27
valid_sources[0x62]	240019	1			T1	9		T3	3		T10	8
valid_sources[0x63]	238172	1			T1	5		T10	2		T11	31
valid_sources[0x64]	243561	1			T1	6		T3	11		T10	9
valid_sources[0x65]	243332	1			T1	7		T10	4		T11	28
valid_sources[0x66]	623532	1			T1	6		T3	4		T10	24
valid_sources[0x67]	239623	1			T1	6		T3	3		T10	2
valid_sources[0x68]	240341	1			T1	6		T10	23		T11	20
valid_sources[0x69]	246028	1			T1	4		T10	18		T11	28
valid_sources[0x6a]	240966	1			T1	5		T3	4		T10	19
valid_sources[0x6b]	274290	1			T1	6		T10	5		T11	37
valid_sources[0x6c]	246811	1			T1	11		T10	6		T11	24
valid_sources[0x6d]	261733	1			T1	7		T10	21		T11	29
valid_sources[0x6e]	238380	1			T1	6		T3	3		T10	9
valid_sources[0x6f]	250061	1			T1	10		T3	5		T10	15
valid_sources[0x70]	237731	1			T1	3		T10	16		T11	21
valid_sources[0x71]	239014	1			T1	5		T10	5		T11	31
valid_sources[0x72]	239820	1			T1	6		T10	43		T11	23
valid_sources[0x73]	238815	1			T1	7		T3	2		T10	25
valid_sources[0x74]	241890	1			T1	13		T3	3		T10	32
valid_sources[0x75]	237487	1			T1	11		T3	6		T10	30
valid_sources[0x76]	237820	1			T1	5		T3	2		T10	10
valid_sources[0x77]	242003	1			T1	8		T3	4		T10	3
valid_sources[0x78]	242043	1			T1	6		T10	11		T11	31
valid_sources[0x79]	248151	1			T1	5		T3	5		T10	13
valid_sources[0x7a]	238906	1			T1	10		T10	12		T11	43
valid_sources[0x7b]	241801	1			T1	5		T10	11		T11	42
valid_sources[0x7c]	242357	1			T1	8		T3	4		T10	3
valid_sources[0x7d]	247467	1			T1	6		T10	8		T11	41
valid_sources[0x7e]	247435	1			T1	1		T3	1		T10	20
valid_sources[0x7f]	267107	1			T1	12		T10	12		T11	23
valid_sources[0x80]	237631	1			T1	7		T3	3		T10	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5815679

1

T1

181

T2

960

T3

25

values[0x0]

all_enables

biggest_size

11910266

1

T1

364

T2

893

T3

48

values[0x1]

all_enables

biggest_size

6739400

1

T1

202

T2

519

T3

34