Unified Coverage Report :: Module :: prim_onehot_check

Module : prim_onehot_check

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_wrap.u_reg.u_prim_reg_we_check.u_prim_onehot_check	100.00			100.00

---

Module Instance : tb.dut.u_reg_wrap.u_reg.u_prim_reg_we_check.u_prim_onehot_check

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_reg_we_check

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : prim_onehot_check

	Total	Covered	Percent
Totals	5	5	100.00
Total Bits	684	684	100.00
Total Bits 0->1	342	342	100.00
Total Bits 1->0	342	342	100.00

Ports	5	5	100.00
Port Bits	684	684	100.00
Port Bits 0->1	342	342	100.00
Port Bits 1->0	342	342	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
oh_i[297:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
oh_i[298]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[305:299]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	INPUT
oh_i[307:306]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[311:308]	Yes	Yes	*T1,T2,*T10	Yes	T1,T2,T10	INPUT
oh_i[312]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[319:313]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	INPUT
oh_i[321:320]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[325:322]	Yes	Yes	*T1,T2,*T10	Yes	T1,T2,T10	INPUT
oh_i[326]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[333:327]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	INPUT
oh_i[335:334]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[339:336]	Yes	Yes	*T1,T2,T10	Yes	T1,T2,T10	INPUT
oh_i[340]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[347:341]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	INPUT
oh_i[349:348]	Unreachable	Unreachable		Unreachable		INPUT
addr_i[8:0]	Unreachable	Unreachable		Unreachable		INPUT
en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
err_o	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT

*Tests covering at least one bit in the range