dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_23.shadow_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_23


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_23.committed_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_23


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_24.staged_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_24


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_24.shadow_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_24


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_24.committed_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_24


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_25.staged_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_25


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_25.shadow_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_25


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_25.committed_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_25


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_26.staged_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_26


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_26.shadow_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_26


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_26.committed_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_26


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_27.staged_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_27


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_27.shadow_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_27


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_27.committed_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_27


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_28.staged_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_28


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_28.shadow_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_28


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_28.committed_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_28


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_29.staged_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_29


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_29.shadow_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_29


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_29.committed_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_29


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_30.staged_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_30


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_30.shadow_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_30


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_30.committed_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_30


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_31.staged_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_31


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_31.shadow_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_31


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_31.committed_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_31


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_32.staged_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_32


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_32.shadow_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_32


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_32.committed_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_32


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_33.staged_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_33


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_33.shadow_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_33


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_33.committed_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_33


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_34.staged_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_34


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_34.shadow_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_34


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_34.committed_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_34


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_35.staged_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_35


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_35.shadow_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_35


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_35.committed_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_35


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_36.staged_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_36


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_36.shadow_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_36


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_36.committed_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_36


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_37.staged_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_37


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_37.shadow_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_37


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_37.committed_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_37


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_38.staged_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_38


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_38.shadow_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_38


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_38.committed_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_38


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_39.staged_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_39


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_39.shadow_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_39


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_39.committed_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_alert_en_shadowed_39


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00

Go back
Module Instances:
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_23.shadow_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_23.committed_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_24.staged_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_24.shadow_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_24.committed_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_25.staged_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_25.shadow_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_25.committed_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_26.staged_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_26.shadow_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_26.committed_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_27.staged_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_27.shadow_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_27.committed_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_28.staged_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_28.shadow_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_28.committed_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_29.staged_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_29.shadow_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_29.committed_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_30.staged_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_30.shadow_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_30.committed_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_31.staged_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_31.shadow_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_31.committed_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_32.staged_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_32.shadow_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_32.committed_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_33.staged_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_33.shadow_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_33.committed_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_34.staged_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_34.shadow_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_34.committed_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_35.staged_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_35.shadow_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_35.committed_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_36.staged_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_36.shadow_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_36.committed_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_37.staged_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_37.shadow_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_37.committed_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_38.staged_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_38.shadow_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_38.committed_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_39.staged_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_39.shadow_reg
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_39.committed_reg
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_23.shadow_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_23.shadow_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_23.shadow_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_23.committed_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_23.committed_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_23.committed_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_24.staged_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_24.staged_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_24.staged_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_24.shadow_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_24.shadow_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_24.shadow_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_24.committed_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_24.committed_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_24.committed_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_25.staged_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_25.staged_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_25.staged_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_25.shadow_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_25.shadow_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_25.shadow_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_25.committed_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_25.committed_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_25.committed_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_26.staged_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_26.staged_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_26.staged_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_26.shadow_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_26.shadow_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_26.shadow_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_26.committed_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_26.committed_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_26.committed_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_27.staged_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_27.staged_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_27.staged_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_27.shadow_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_27.shadow_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_27.shadow_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_27.committed_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_27.committed_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_27.committed_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_28.staged_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_28.staged_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_28.staged_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_28.shadow_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_28.shadow_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_28.shadow_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_28.committed_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_28.committed_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_28.committed_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_29.staged_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_29.staged_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_29.staged_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_29.shadow_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_29.shadow_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_29.shadow_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_29.committed_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_29.committed_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_29.committed_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_30.staged_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_30.staged_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_30.staged_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_30.shadow_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_30.shadow_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_30.shadow_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_30.committed_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_30.committed_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_30.committed_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_31.staged_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_31.staged_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_31.staged_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_31.shadow_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_31.shadow_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_31.shadow_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_31.committed_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_31.committed_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_31.committed_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_32.staged_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_32.staged_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_32.staged_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_32.shadow_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_32.shadow_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_32.shadow_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_32.committed_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_32.committed_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_32.committed_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_33.staged_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_33.staged_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_33.staged_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_33.shadow_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_33.shadow_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_33.shadow_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_33.committed_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_33.committed_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_33.committed_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_34.staged_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_34.staged_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_34.staged_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_34.shadow_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_34.shadow_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_34.shadow_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_34.committed_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_34.committed_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_34.committed_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_35.staged_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_35.staged_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_35.staged_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_35.shadow_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_35.shadow_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_35.shadow_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_35.committed_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_35.committed_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_35.committed_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_36.staged_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_36.staged_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_36.staged_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_36.shadow_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_36.shadow_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_36.shadow_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_36.committed_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_36.committed_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_36.committed_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_37.staged_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_37.staged_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_37.staged_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_37.shadow_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_37.shadow_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_37.shadow_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_37.committed_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_37.committed_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_37.committed_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_38.staged_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_38.staged_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_38.staged_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_38.shadow_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_38.shadow_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_38.shadow_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_38.committed_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_38.committed_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_38.committed_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_39.staged_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_39.staged_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_39.staged_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_39.shadow_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_39.shadow_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_39.shadow_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_39.committed_reg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00

55 always_ff @(posedge clk_i or negedge rst_ni) begin 56 1/1 if (!rst_ni) begin Tests: T1 T2 T3  57 1/1 q <= RESVAL; Tests: T1 T2 T3  58 1/1 end else if (wr_en) begin Tests: T1 T2 T3  59 1/1 q <= wr_data; Tests: T1 T2 T3  60 end MISSING_ELSE 61 end 62 63 // feed back out for consolidation 64 1/1 assign ds = wr_en ? wr_data : qs; Tests: T1 T2 T3  65 1/1 assign qe = wr_en; Tests: T1 T2 T3  66 67 if (SwAccess == SwAccessRC) begin : gen_rc 68 // In case of a SW RC colliding with a HW write, SW gets the value written by HW 69 // but the register is cleared to 0. See #5416 for a discussion. 70 assign qs = de && we ? d : q; 71 end else begin : gen_no_rc 72 1/1 assign qs = q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_39.committed_reg
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_39.committed_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00


64 assign ds = wr_en ? wr_data : qs; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


56 if (!rst_ni) begin -1- 57 q <= RESVAL; ==> 58 end else if (wr_en) begin -2- 59 q <= wr_data; ==> 60 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%