Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T2 T3 T10 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T2 T3 T10 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T2 T3 T10 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T13 
159        1/1                    state_d = TimeoutSt;
           Tests:       T1 T2 T13 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T1 T2 T13 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T1 T2 T13 
172        1/1                    state_d    = Phase0St;
           Tests:       T1 T29 T14 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T1 T29 T14 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T1 T29 T14 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T1 T29 T14 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T1 T2 T13 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T13 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T1 T2 T13 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T13 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T1 T2 T3 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T1 T2 T3 
190        1/1                  esc_state_o = Phase0;
           Tests:       T1 T2 T3 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T1 T2 T3 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
194        1/1                    state_d = IdleSt;
           Tests:       T12 T30 T31 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T30 T31 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T12 T30 T31 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
198        1/1                    state_d = Phase1St;
           Tests:       T1 T2 T3 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T3 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T1 T2 T3 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T1 T2 T3 
207        1/1                  esc_state_o = Phase1;
           Tests:       T1 T2 T3 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T1 T2 T3 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
211        1/1                    state_d = IdleSt;
           Tests:       T32 T33 T34 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T33 T34 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T32 T33 T34 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
215        1/1                    state_d = Phase2St;
           Tests:       T1 T2 T3 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T3 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T1 T2 T3 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T1 T2 T3 
224        1/1                  esc_state_o = Phase2;
           Tests:       T1 T2 T3 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T1 T2 T3 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
229        1/1                    state_d = IdleSt;
           Tests:       T12 T35 T36 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T35 T36 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T12 T35 T36 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
233        1/1                    state_d = Phase3St;
           Tests:       T1 T2 T3 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T1 T2 T3 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T1 T2 T3 
241        1/1                  esc_state_o = Phase3;
           Tests:       T1 T2 T3 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T1 T2 T3 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
245        1/1                    state_d = IdleSt;
           Tests:       T37 T38 T39 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T37 T38 T39 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T37 T38 T39 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
249        1/1                    state_d = TerminalSt;
           Tests:       T1 T2 T3 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T1 T2 T3 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
259        1/1                  esc_state_o = Terminal;
           Tests:       T1 T2 T3 
260        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
261        1/1                    state_d = IdleSt;
           Tests:       T2 T13 T26 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T7 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T7 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T7 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T7 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T10

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T3,T10,T16
1	1	0	Covered	T1,T10,T13
1	1	1	Covered	T1,T2,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T13
0	1	Covered	T1,T14,T40
1	0	Covered	T29,T30,T39

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T13
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T29,T30,T39

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Covered	T37,T41,T42
1	1	Covered	T1,T14,T40

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T3,T10,T11

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T25

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T1,T2,T11

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T24,T25,T26

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T11

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T2,T13

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T2,T3,T10
IdleSt->TimeoutSt	159	Covered	T1,T2,T13
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T12,T30,T43
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T32,T43,T33
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T12,T35,T36
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T37,T38,T39
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T2,T13,T26
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T2,T13
TimeoutSt->Phase0St	172	Covered	T1,T29,T14

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T29,T14
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T13
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T12,T30,T31
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T10
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T32,T33,T34
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T10
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T12,T35,T36
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T37,T38,T39
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T10
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T13,T26
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1107	0	0
CheckAccumTrig0_A	2147483647	1998	0	0
CheckAccumTrig1_A	2147483647	86	0	0
CheckClr_A	2147483647	824	0	0
CheckEn_A	2147483647	906511070	0	0
CheckPhase0_A	2147483647	2226	0	0
CheckPhase1_A	2147483647	2181	0	0
CheckPhase2_A	2147483647	2142	0	0
CheckPhase3_A	2147483647	2100	0	0
CheckTimeout0_A	2147483647	2000	0	0
CheckTimeoutSt1_A	2147483647	258804	0	0
CheckTimeoutSt2_A	2147483647	1705	0	0
CheckTimeoutStTrig_A	2147483647	196	0	0
ErrorStAllEscAsserted_A	2147483647	5843	0	0
ErrorStIsTerminal_A	2147483647	4763	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1107	0	0
T7	421592	232	0	0
T8	186004	219	0	0
T9	519100	288	0	0
T20	85644	0	0	0
T44	84088	127	0	0
T45	0	241	0	0
T46	3880	0	0	0
T47	125892	0	0	0
T48	435072	0	0	0
T49	363760	0	0	0
T50	59940	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1998	0	0
T2	21393	2	0	0
T3	4070	1	0	0
T4	27627	0	0	0
T5	237036	0	0	0
T6	13145	0	0	0
T10	21118	2	0	0
T11	76842	3	0	0
T12	14185	3	0	0
T13	68212	4	0	0
T14	0	2	0	0
T15	17528	0	0	0
T16	55143	0	0	0
T19	0	1	0	0
T24	102796	1	0	0
T25	149212	2	0	0
T26	275154	2	0	0
T27	17238	1	0	0
T28	3406	1	0	0
T29	0	1	0	0
T30	0	2	0	0
T35	0	1	0	0
T37	0	6	0	0
T40	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	86	0	0
T23	22672	0	0	0
T29	10092	1	0	0
T30	76564	1	0	0
T35	19473	0	0	0
T38	91974	0	0	0
T39	0	1	0	0
T43	166364	0	0	0
T54	0	2	0	0
T55	231043	1	0	0
T56	0	1	0	0
T57	0	3	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	4	0	0
T63	0	1	0	0
T64	0	3	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	0	2	0	0
T70	0	3	0	0
T71	0	1	0	0
T72	82467	0	0	0
T73	67072	0	0	0
T74	1178	0	0	0
T75	26275	0	0	0
T76	19271	0	0	0
T77	111267	0	0	0
T78	159845	0	0	0
T79	57146	0	0	0
T80	4409	0	0	0
T81	28080	0	0	0
T82	29391	0	0	0
T83	81986	0	0	0
T84	29761	0	0	0
T85	594452	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	824	0	0
T2	21393	1	0	0
T3	4070	0	0	0
T4	9209	0	0	0
T5	355554	0	0	0
T6	39435	0	0	0
T10	10559	0	0	0
T11	25614	0	0	0
T12	42555	2	0	0
T13	68212	2	0	0
T14	0	1	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T17	517833	0	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T26	275154	1	0	0
T27	17238	0	0	0
T28	10218	0	0	0
T29	30276	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	2	0	0
T35	0	6	0	0
T37	0	6	0	0
T40	0	1	0	0
T43	0	1	0	0
T50	0	1	0	0
T54	0	8	0	0
T72	0	1	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	0	2	0	0
T89	0	2	0	0
T90	0	1	0	0
T91	283104	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	906511070	0	0
T1	101588	40002	0	0
T2	85572	62353	0	0
T3	16280	10879	0	0
T4	36836	3428	0	0
T10	42236	22500	0	0
T11	102456	28823	0	0
T15	17528	13061	0	0
T16	73524	53814	0	0
T24	102796	64879	0	0
T25	149212	78795	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2226	0	0
T1	50794	1	0	0
T2	42786	2	0	0
T3	8140	1	0	0
T4	36836	0	0	0
T5	118518	0	0	0
T10	31677	2	0	0
T11	102456	3	0	0
T12	0	2	0	0
T13	34106	4	0	0
T14	0	3	0	0
T15	17528	0	0	0
T16	73524	0	0	0
T24	102796	1	0	0
T25	149212	2	0	0
T26	183436	2	0	0
T27	11492	1	0	0
T28	0	1	0	0
T29	0	1	0	0
T30	0	1	0	0
T35	0	1	0	0
T37	0	7	0	0
T40	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2181	0	0
T1	50794	1	0	0
T2	42786	2	0	0
T3	8140	1	0	0
T4	36836	0	0	0
T5	118518	0	0	0
T10	31677	2	0	0
T11	102456	3	0	0
T12	0	2	0	0
T13	34106	4	0	0
T14	0	3	0	0
T15	17528	0	0	0
T16	73524	0	0	0
T24	102796	1	0	0
T25	149212	2	0	0
T26	183436	2	0	0
T27	11492	1	0	0
T28	0	1	0	0
T29	0	1	0	0
T30	0	3	0	0
T35	0	1	0	0
T37	0	7	0	0
T40	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2142	0	0
T1	50794	1	0	0
T2	42786	2	0	0
T3	8140	1	0	0
T4	36836	0	0	0
T5	118518	0	0	0
T10	31677	2	0	0
T11	102456	3	0	0
T12	0	1	0	0
T13	34106	4	0	0
T14	0	3	0	0
T15	17528	0	0	0
T16	73524	0	0	0
T24	102796	1	0	0
T25	149212	2	0	0
T26	183436	2	0	0
T27	11492	1	0	0
T28	0	1	0	0
T29	0	1	0	0
T30	0	3	0	0
T35	0	1	0	0
T37	0	7	0	0
T40	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2100	0	0
T1	50794	1	0	0
T2	42786	2	0	0
T3	8140	1	0	0
T4	36836	0	0	0
T5	118518	0	0	0
T10	31677	2	0	0
T11	102456	3	0	0
T12	0	1	0	0
T13	34106	4	0	0
T14	0	3	0	0
T15	17528	0	0	0
T16	73524	0	0	0
T24	102796	1	0	0
T25	149212	2	0	0
T26	183436	2	0	0
T27	11492	1	0	0
T28	0	1	0	0
T29	0	1	0	0
T30	0	3	0	0
T35	0	1	0	0
T37	0	6	0	0
T40	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2000	0	0
T1	76191	7	0	0
T2	64179	1	0	0
T3	12210	0	0	0
T4	27627	0	0	0
T7	105398	0	0	0
T8	46501	0	0	0
T9	129775	0	0	0
T10	31677	0	0	0
T11	76842	0	0	0
T13	0	1	0	0
T14	27002	1	0	0
T15	13146	0	0	0
T16	55143	0	0	0
T20	21411	0	0	0
T24	77097	0	0	0
T25	111909	0	0	0
T26	0	1	0	0
T29	0	2	0	0
T30	0	4	0	0
T33	0	2	0	0
T35	0	4	0	0
T37	0	4	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	4	0	0
T43	0	11	0	0
T44	21022	0	0	0
T46	970	0	0	0
T47	31473	10	0	0
T48	108768	0	0	0
T50	0	1	0	0
T54	0	5	0	0
T92	0	12	0	0
T93	41723	13	0	0
T94	0	8	0	0
T95	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	258804	0	0
T1	76191	1281	0	0
T2	64179	94	0	0
T3	12210	0	0	0
T4	27627	0	0	0
T7	105398	0	0	0
T8	46501	0	0	0
T9	129775	0	0	0
T10	31677	0	0	0
T11	76842	0	0	0
T13	0	3	0	0
T14	27002	743	0	0
T15	13146	0	0	0
T16	55143	0	0	0
T20	21411	0	0	0
T24	77097	0	0	0
T25	111909	0	0	0
T26	0	134	0	0
T29	0	63	0	0
T30	0	2148	0	0
T33	0	165	0	0
T35	0	156	0	0
T37	0	442	0	0
T39	0	119	0	0
T40	0	234	0	0
T41	0	211	0	0
T43	0	2094	0	0
T44	21022	0	0	0
T46	970	0	0	0
T47	31473	1012	0	0
T48	108768	0	0	0
T50	0	189	0	0
T54	0	414	0	0
T92	0	1520	0	0
T93	41723	801	0	0
T94	0	1378	0	0
T95	0	116	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1705	0	0
T1	76191	5	0	0
T2	64179	1	0	0
T3	12210	0	0	0
T4	27627	0	0	0
T10	31677	0	0	0
T11	76842	0	0	0
T13	0	1	0	0
T15	13146	0	0	0
T16	55143	0	0	0
T24	77097	0	0	0
T25	111909	0	0	0
T26	0	1	0	0
T29	0	1	0	0
T32	40474	0	0	0
T33	0	6	0	0
T35	0	4	0	0
T36	0	8	0	0
T37	127006	3	0	0
T40	48102	1	0	0
T41	0	4	0	0
T43	0	8	0	0
T44	21022	0	0	0
T47	31473	10	0	0
T48	108768	0	0	0
T49	90940	0	0	0
T50	14985	1	0	0
T51	27020	2	0	0
T54	0	3	0	0
T89	0	1	0	0
T92	0	11	0	0
T93	0	13	0	0
T94	0	8	0	0
T95	0	4	0	0
T96	31786	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	196	0	0
T1	25397	1	0	0
T2	21393	0	0	0
T3	4070	0	0	0
T4	9209	0	0	0
T7	105398	0	0	0
T8	46501	0	0	0
T9	129775	0	0	0
T10	10559	0	0	0
T11	25614	0	0	0
T14	27002	1	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T20	21411	0	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T30	76564	1	0	0
T33	0	1	0	0
T36	0	5	0	0
T38	0	8	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	2	0	0
T44	21022	0	0	0
T46	970	0	0	0
T47	31473	0	0	0
T48	108768	0	0	0
T54	0	3	0	0
T55	0	1	0	0
T56	0	1	0	0
T61	0	1	0	0
T73	0	2	0	0
T81	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T93	41723	0	0	0
T97	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5843	0	0
T7	421592	1325	0	0
T8	186004	1336	0	0
T9	519100	1315	0	0
T20	85644	0	0	0
T44	84088	683	0	0
T45	0	1184	0	0
T46	3880	0	0	0
T47	125892	0	0	0
T48	435072	0	0	0
T49	363760	0	0	0
T50	59940	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4763	0	0
T7	421592	1085	0	0
T8	186004	1096	0	0
T9	519100	1075	0	0
T20	85644	0	0	0
T44	84088	563	0	0
T45	0	944	0	0
T46	3880	0	0	0
T47	125892	0	0	0
T48	435072	0	0	0
T49	363760	0	0	0
T50	59940	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	101588	101300	0	0
T2	85572	85352	0	0
T3	16280	15884	0	0
T4	36836	36264	0	0
T10	42236	41916	0	0
T11	102456	102060	0	0
T15	17528	17328	0	0
T16	73524	73276	0	0
T24	102796	102584	0	0
T25	149212	148848	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	101588	101300	0	0
T2	85572	85352	0	0
T3	16280	15884	0	0
T4	36836	36264	0	0
T10	42236	41916	0	0
T11	102456	102060	0	0
T15	17528	17328	0	0
T16	73524	73276	0	0
T24	102796	102584	0	0
T25	149212	148848	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T15 T13 T29 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T15 T13 T29 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T15 T13 T29 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T13 T92 
159        1/1                    state_d = TimeoutSt;
           Tests:       T1 T13 T92 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T1 T13 T92 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T1 T13 T92 
172        1/1                    state_d    = Phase0St;
           Tests:       T1 T92 T51 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T1 T92 T51 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T1 T92 T51 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T1 T92 T51 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T1 T13 T92 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T13 T92 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T1 T13 T92 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T13 T92 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T15 T13 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T1 T15 T13 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T1 T15 T13 
190        1/1                  esc_state_o = Phase0;
           Tests:       T1 T15 T13 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T1 T15 T13 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T1 T15 T13 
194        1/1                    state_d = IdleSt;
           Tests:       T30 T69 T101 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T30 T69 T101 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T30 T69 T101 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T15 T13 
198        1/1                    state_d = Phase1St;
           Tests:       T1 T15 T13 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T15 T13 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T15 T13 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T15 T13 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T1 T15 T13 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T1 T15 T13 
207        1/1                  esc_state_o = Phase1;
           Tests:       T1 T15 T13 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T1 T15 T13 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T1 T15 T13 
211        1/1                    state_d = IdleSt;
           Tests:       T54 T102 T56 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T54 T102 T56 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T54 T102 T56 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T15 T13 
215        1/1                    state_d = Phase2St;
           Tests:       T1 T15 T13 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T15 T13 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T15 T13 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T15 T13 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T1 T15 T13 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T1 T15 T13 
224        1/1                  esc_state_o = Phase2;
           Tests:       T1 T15 T13 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T1 T15 T13 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T1 T15 T13 
229        1/1                    state_d = IdleSt;
           Tests:       T103 T104 T105 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T103 T104 T105 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T103 T104 T105 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T15 T13 
233        1/1                    state_d = Phase3St;
           Tests:       T1 T15 T13 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T15 T13 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T15 T13 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T1 T15 T13 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T1 T15 T13 
241        1/1                  esc_state_o = Phase3;
           Tests:       T1 T15 T13 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T1 T15 T13 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T1 T15 T13 
245        1/1                    state_d = IdleSt;
           Tests:       T35 T106 T107 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T106 T107 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T35 T106 T107 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T15 T13 
249        1/1                    state_d = TerminalSt;
           Tests:       T1 T15 T13 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T15 T13 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T1 T15 T13 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T15 T13 
259        1/1                  esc_state_o = Terminal;
           Tests:       T1 T15 T13 
260        1/1                  if (clr_i) begin
           Tests:       T1 T15 T13 
261        1/1                    state_d = IdleSt;
           Tests:       T13 T51 T54 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T7 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T7 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T7 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T7 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T15,T13
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T15,T13

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T16
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T13,T29

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T24,T13
1	0	1	Covered	T16,T15,T25
1	1	0	Covered	T1,T10,T13
1	1	1	Covered	T1,T13,T92

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T13,T92
0	1	Covered	T1,T92,T51
1	0	Covered	T54,T108,T56

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T13,T92
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T54,T108,T56

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T92
1	0	Not Covered
1	1	Covered	T1,T92,T51

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T29,T14,T48
1	Covered	T1,T15,T13

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T15,T13
1	Covered	T29,T40,T30

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T15,T13
1	Covered	T53,T43,T33

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T15,T13
1	Covered	T14,T48,T35

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T15,T13,T29

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T15,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T15,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T15,T13

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T15,T13
Phase1St	198	Covered	T1,T15,T13
Phase2St	215	Covered	T1,T15,T13
Phase3St	233	Covered	T1,T15,T13
TerminalSt	249	Covered	T1,T15,T13
TimeoutSt	159	Covered	T1,T13,T92

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T15,T13,T29
IdleSt->TimeoutSt	159	Covered	T1,T13,T92
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T30,T43,T33
Phase0St->Phase1St	198	Covered	T1,T15,T13
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T54,T102,T56
Phase1St->Phase2St	215	Covered	T1,T15,T13
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T103,T104,T105
Phase2St->Phase3St	233	Covered	T1,T15,T13
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T35,T106,T107
Phase3St->TerminalSt	249	Covered	T1,T15,T13
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T13,T51,T43
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T13,T92
TimeoutSt->Phase0St	172	Covered	T1,T92,T51

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T13,T29
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T13,T92
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T92,T51
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T13,T92
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T13,T92
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T69,T101
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T15,T13
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T13,T29
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T54,T102,T56
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T15,T13
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T13,T29
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T103,T104,T105
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T15,T13
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T13,T29
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T35,T106,T107
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T15,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T13,T29
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T13,T51,T54
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T15,T13
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	555259424	295	0	0
CheckAccumTrig0_A	555259424	463	0	0
CheckAccumTrig1_A	555259424	15	0	0
CheckClr_A	555259424	192	0	0
CheckEn_A	554926211	235456991	0	0
CheckPhase0_A	555259424	515	0	0
CheckPhase1_A	555259424	502	0	0
CheckPhase2_A	555259424	489	0	0
CheckPhase3_A	555259424	476	0	0
CheckTimeout0_A	555259424	366	0	0
CheckTimeoutSt1_A	555259424	54061	0	0
CheckTimeoutSt2_A	555259424	304	0	0
CheckTimeoutStTrig_A	555259424	44	0	0
ErrorStAllEscAsserted_A	555259424	1473	0	0
ErrorStIsTerminal_A	555259424	1203	0	0
EscStateOut_A	554924711	554857027	0	0
u_state_regs_A	555259424	555076380	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	295	0	0
T7	105398	75	0	0
T8	46501	70	0	0
T9	129775	69	0	0
T20	21411	0	0	0
T44	21022	33	0	0
T45	0	48	0	0
T46	970	0	0	0
T47	31473	0	0	0
T48	108768	0	0	0
T49	90940	0	0	0
T50	14985	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	463	0	0
T5	118518	0	0	0
T6	13145	0	0	0
T12	14185	0	0	0
T13	17053	3	0	0
T14	0	1	0	0
T15	4382	1	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T26	91718	0	0	0
T27	5746	0	0	0
T28	3406	0	0	0
T29	0	1	0	0
T40	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T109	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	15	0	0
T31	515037	0	0	0
T36	39117	0	0	0
T54	328050	1	0	0
T56	0	1	0	0
T66	0	1	0	0
T88	34277	0	0	0
T97	181686	0	0	0
T105	0	2	0	0
T108	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	44576	0	0	0
T116	857759	0	0	0
T117	400039	0	0	0
T118	3186	0	0	0
T119	16052	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	192	0	0
T5	118518	0	0	0
T6	13145	0	0	0
T12	14185	0	0	0
T13	17053	2	0	0
T17	172611	0	0	0
T26	91718	0	0	0
T27	5746	0	0	0
T28	3406	0	0	0
T29	10092	0	0	0
T30	0	1	0	0
T35	0	1	0	0
T51	0	2	0	0
T54	0	5	0	0
T88	0	1	0	0
T91	94368	0	0	0
T97	0	1	0	0
T103	0	1	0	0
T106	0	9	0	0
T120	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554926211	235456991	0	0
T1	25397	8578	0	0
T2	21393	21337	0	0
T3	4070	2743	0	0
T4	9209	863	0	0
T10	10559	10478	0	0
T11	25614	25514	0	0
T15	4382	3296	0	0
T16	18381	6180	0	0
T24	25699	20879	0	0
T25	37303	33792	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	515	0	0
T1	25397	1	0	0
T2	21393	0	0	0
T3	4070	0	0	0
T4	9209	0	0	0
T10	10559	0	0	0
T11	25614	0	0	0
T13	0	3	0	0
T14	0	1	0	0
T15	4382	1	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T29	0	1	0	0
T40	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T51	0	3	0	0
T92	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	502	0	0
T1	25397	1	0	0
T2	21393	0	0	0
T3	4070	0	0	0
T4	9209	0	0	0
T10	10559	0	0	0
T11	25614	0	0	0
T13	0	3	0	0
T14	0	1	0	0
T15	4382	1	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T29	0	1	0	0
T40	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T51	0	3	0	0
T92	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	489	0	0
T1	25397	1	0	0
T2	21393	0	0	0
T3	4070	0	0	0
T4	9209	0	0	0
T10	10559	0	0	0
T11	25614	0	0	0
T13	0	3	0	0
T14	0	1	0	0
T15	4382	1	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T29	0	1	0	0
T40	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T51	0	3	0	0
T92	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	476	0	0
T1	25397	1	0	0
T2	21393	0	0	0
T3	4070	0	0	0
T4	9209	0	0	0
T10	10559	0	0	0
T11	25614	0	0	0
T13	0	3	0	0
T14	0	1	0	0
T15	4382	1	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T29	0	1	0	0
T40	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T51	0	3	0	0
T92	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	366	0	0
T1	25397	2	0	0
T2	21393	0	0	0
T3	4070	0	0	0
T4	9209	0	0	0
T10	10559	0	0	0
T11	25614	0	0	0
T13	0	1	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T30	0	3	0	0
T35	0	1	0	0
T37	0	1	0	0
T43	0	3	0	0
T51	0	3	0	0
T76	0	1	0	0
T92	0	4	0	0
T121	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	54061	0	0
T1	25397	331	0	0
T2	21393	0	0	0
T3	4070	0	0	0
T4	9209	0	0	0
T10	10559	0	0	0
T11	25614	0	0	0
T13	0	3	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T30	0	1408	0	0
T35	0	47	0	0
T37	0	92	0	0
T43	0	420	0	0
T51	0	239	0	0
T76	0	145	0	0
T92	0	474	0	0
T121	0	420	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	304	0	0
T1	25397	1	0	0
T2	21393	0	0	0
T3	4070	0	0	0
T4	9209	0	0	0
T10	10559	0	0	0
T11	25614	0	0	0
T13	0	1	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T30	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T43	0	2	0	0
T51	0	2	0	0
T76	0	1	0	0
T92	0	3	0	0
T121	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	44	0	0
T1	25397	1	0	0
T2	21393	0	0	0
T3	4070	0	0	0
T4	9209	0	0	0
T10	10559	0	0	0
T11	25614	0	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T30	0	2	0	0
T43	0	1	0	0
T51	0	1	0	0
T81	0	1	0	0
T90	0	1	0	0
T92	0	1	0	0
T98	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	1473	0	0
T7	105398	350	0	0
T8	46501	341	0	0
T9	129775	335	0	0
T20	21411	0	0	0
T44	21022	162	0	0
T45	0	285	0	0
T46	970	0	0	0
T47	31473	0	0	0
T48	108768	0	0	0
T49	90940	0	0	0
T50	14985	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	1203	0	0
T7	105398	290	0	0
T8	46501	281	0	0
T9	129775	275	0	0
T20	21411	0	0	0
T44	21022	132	0	0
T45	0	225	0	0
T46	970	0	0	0
T47	31473	0	0	0
T48	108768	0	0	0
T49	90940	0	0	0
T50	14985	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554924711	554857027	0	0
T1	25397	25325	0	0
T2	21393	21338	0	0
T3	4070	3971	0	0
T4	9209	9066	0	0
T10	10559	10479	0	0
T11	25614	25515	0	0
T15	4382	4332	0	0
T16	18381	18319	0	0
T24	25699	25646	0	0
T25	37303	37212	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	555076380	0	0
T1	25397	25325	0	0
T2	21393	21338	0	0
T3	4070	3971	0	0
T4	9209	9066	0	0
T10	10559	10479	0	0
T11	25614	25515	0	0
T15	4382	4332	0	0
T16	18381	18319	0	0
T24	25699	25646	0	0
T25	37303	37212	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T2 T3 T10 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T2 T3 T10 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T2 T3 T10 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T26 
159        1/1                    state_d = TimeoutSt;
           Tests:       T1 T2 T26 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T1 T2 T26 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T1 T2 T26 
172        1/1                    state_d    = Phase0St;
           Tests:       T1 T30 T73 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T1 T30 T73 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T1 T30 T73 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T1 T30 T73 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T1 T2 T26 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T26 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T1 T2 T26 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T26 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T1 T2 T3 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T1 T2 T3 
190        1/1                  esc_state_o = Phase0;
           Tests:       T1 T2 T3 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T1 T2 T3 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
194        1/1                    state_d = IdleSt;
           Tests:       T12 T124 T65 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T124 T65 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T12 T124 T65 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
198        1/1                    state_d = Phase1St;
           Tests:       T1 T2 T3 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T3 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T1 T2 T3 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T1 T2 T3 
207        1/1                  esc_state_o = Phase1;
           Tests:       T1 T2 T3 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T1 T2 T3 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
211        1/1                    state_d = IdleSt;
           Tests:       T64 T125 T126 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T64 T125 T126 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T64 T125 T126 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
215        1/1                    state_d = Phase2St;
           Tests:       T1 T2 T3 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T3 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T1 T2 T3 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T1 T2 T3 
224        1/1                  esc_state_o = Phase2;
           Tests:       T1 T2 T3 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T1 T2 T3 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
229        1/1                    state_d = IdleSt;
           Tests:       T12 T127 T64 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T127 T64 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T12 T127 T64 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
233        1/1                    state_d = Phase3St;
           Tests:       T1 T2 T3 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T1 T2 T3 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T1 T2 T3 
241        1/1                  esc_state_o = Phase3;
           Tests:       T1 T2 T3 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T1 T2 T3 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
245        1/1                    state_d = IdleSt;
           Tests:       T38 T39 T58 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T38 T39 T58 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T38 T39 T58 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
249        1/1                    state_d = TerminalSt;
           Tests:       T1 T2 T3 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T1 T2 T3 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
259        1/1                  esc_state_o = Terminal;
           Tests:       T1 T2 T3 
260        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
261        1/1                    state_d = IdleSt;
           Tests:       T2 T26 T29 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T7 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T7 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T7 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T7 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T10

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T26
1	0	1	Covered	T3,T10,T25
1	1	0	Covered	T13,T91,T92
1	1	1	Covered	T1,T2,T26

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T26
0	1	Covered	T1,T73,T38
1	0	Covered	T30,T39,T54

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T26
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T30,T39,T54

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T26
1	0	Covered	T42
1	1	Covered	T1,T73,T38

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T3,T10,T86

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T27,T40

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T1,T2,T11

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T24,T25,T26

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T24

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T2,T26

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T2,T3,T10
IdleSt->TimeoutSt	159	Covered	T1,T2,T26
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T12,T33,T54
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T43,T89,T64
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T12,T127,T64
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T38,T39,T58
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T26,T29
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T2,T26
TimeoutSt->Phase0St	172	Covered	T1,T30,T73

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T26
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T30,T73
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T26
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T26
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T12,T124,T65
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T10
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T64,T125,T126
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T10
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T12,T127,T64
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T38,T39,T58
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T10
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T26,T29
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	555259424	276	0	0
CheckAccumTrig0_A	555259424	698	0	0
CheckAccumTrig1_A	555259424	33	0	0
CheckClr_A	555259424	299	0	0
CheckEn_A	554926211	195299963	0	0
CheckPhase0_A	555259424	770	0	0
CheckPhase1_A	555259424	758	0	0
CheckPhase2_A	555259424	745	0	0
CheckPhase3_A	555259424	730	0	0
CheckTimeout0_A	555259424	791	0	0
CheckTimeoutSt1_A	555259424	85763	0	0
CheckTimeoutSt2_A	555259424	693	0	0
CheckTimeoutStTrig_A	555259424	62	0	0
ErrorStAllEscAsserted_A	555259424	1466	0	0
ErrorStIsTerminal_A	555259424	1196	0	0
EscStateOut_A	554924711	554857027	0	0
u_state_regs_A	555259424	555076380	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	276	0	0
T7	105398	49	0	0
T8	46501	60	0	0
T9	129775	90	0	0
T20	21411	0	0	0
T44	21022	29	0	0
T45	0	48	0	0
T46	970	0	0	0
T47	31473	0	0	0
T48	108768	0	0	0
T49	90940	0	0	0
T50	14985	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	698	0	0
T2	21393	2	0	0
T3	4070	1	0	0
T4	9209	0	0	0
T10	10559	1	0	0
T11	25614	1	0	0
T12	0	3	0	0
T13	17053	0	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	1	0	0
T25	37303	1	0	0
T26	0	2	0	0
T27	0	1	0	0
T29	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	33	0	0
T23	22672	0	0	0
T30	76564	1	0	0
T35	19473	0	0	0
T38	91974	0	0	0
T39	0	1	0	0
T43	166364	0	0	0
T54	0	1	0	0
T57	0	3	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T64	0	3	0	0
T72	82467	0	0	0
T73	67072	0	0	0
T74	1178	0	0	0
T75	26275	0	0	0
T76	19271	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	299	0	0
T2	21393	1	0	0
T3	4070	0	0	0
T4	9209	0	0	0
T10	10559	0	0	0
T11	25614	0	0	0
T12	0	2	0	0
T13	17053	0	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T26	0	1	0	0
T29	0	1	0	0
T35	0	4	0	0
T43	0	1	0	0
T50	0	1	0	0
T72	0	1	0	0
T86	0	2	0	0
T87	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554926211	195299963	0	0
T1	25397	8519	0	0
T2	21393	582	0	0
T3	4070	2696	0	0
T4	9209	851	0	0
T10	10559	768	0	0
T11	25614	582	0	0
T15	4382	3230	0	0
T16	18381	14660	0	0
T24	25699	2119	0	0
T25	37303	2166	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	770	0	0
T1	25397	1	0	0
T2	21393	2	0	0
T3	4070	1	0	0
T4	9209	0	0	0
T10	10559	1	0	0
T11	25614	1	0	0
T12	0	2	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	1	0	0
T25	37303	1	0	0
T26	0	2	0	0
T27	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	758	0	0
T1	25397	1	0	0
T2	21393	2	0	0
T3	4070	1	0	0
T4	9209	0	0	0
T10	10559	1	0	0
T11	25614	1	0	0
T12	0	2	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	1	0	0
T25	37303	1	0	0
T26	0	2	0	0
T27	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	745	0	0
T1	25397	1	0	0
T2	21393	2	0	0
T3	4070	1	0	0
T4	9209	0	0	0
T10	10559	1	0	0
T11	25614	1	0	0
T12	0	1	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	1	0	0
T25	37303	1	0	0
T26	0	2	0	0
T27	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	730	0	0
T1	25397	1	0	0
T2	21393	2	0	0
T3	4070	1	0	0
T4	9209	0	0	0
T10	10559	1	0	0
T11	25614	1	0	0
T12	0	1	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	1	0	0
T25	37303	1	0	0
T26	0	2	0	0
T27	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	791	0	0
T1	25397	3	0	0
T2	21393	1	0	0
T3	4070	0	0	0
T4	9209	0	0	0
T10	10559	0	0	0
T11	25614	0	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T26	0	1	0	0
T29	0	1	0	0
T41	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T92	0	3	0	0
T93	0	12	0	0
T94	0	8	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	85763	0	0
T1	25397	490	0	0
T2	21393	94	0	0
T3	4070	0	0	0
T4	9209	0	0	0
T10	10559	0	0	0
T11	25614	0	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T26	0	134	0	0
T29	0	56	0	0
T41	0	56	0	0
T47	0	90	0	0
T50	0	189	0	0
T92	0	394	0	0
T93	0	751	0	0
T94	0	1378	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	693	0	0
T1	25397	2	0	0
T2	21393	1	0	0
T3	4070	0	0	0
T4	9209	0	0	0
T10	10559	0	0	0
T11	25614	0	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T26	0	1	0	0
T29	0	1	0	0
T41	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T92	0	3	0	0
T93	0	12	0	0
T94	0	8	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	62	0	0
T1	25397	1	0	0
T2	21393	0	0	0
T3	4070	0	0	0
T4	9209	0	0	0
T10	10559	0	0	0
T11	25614	0	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T33	0	1	0	0
T38	0	8	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T61	0	1	0	0
T73	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	1466	0	0
T7	105398	318	0	0
T8	46501	343	0	0
T9	129775	317	0	0
T20	21411	0	0	0
T44	21022	182	0	0
T45	0	306	0	0
T46	970	0	0	0
T47	31473	0	0	0
T48	108768	0	0	0
T49	90940	0	0	0
T50	14985	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	1196	0	0
T7	105398	258	0	0
T8	46501	283	0	0
T9	129775	257	0	0
T20	21411	0	0	0
T44	21022	152	0	0
T45	0	246	0	0
T46	970	0	0	0
T47	31473	0	0	0
T48	108768	0	0	0
T49	90940	0	0	0
T50	14985	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554924711	554857027	0	0
T1	25397	25325	0	0
T2	21393	21338	0	0
T3	4070	3971	0	0
T4	9209	9066	0	0
T10	10559	10479	0	0
T11	25614	25515	0	0
T15	4382	4332	0	0
T16	18381	18319	0	0
T24	25699	25646	0	0
T25	37303	37212	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	555076380	0	0
T1	25397	25325	0	0
T2	21393	21338	0	0
T3	4070	3971	0	0
T4	9209	9066	0	0
T10	10559	10479	0	0
T11	25614	25515	0	0
T15	4382	4332	0	0
T16	18381	18319	0	0
T24	25699	25646	0	0
T25	37303	37212	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T11 T4 T13 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T11 T4 T13 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T11 T4 T13 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T14 T47 T40 
159        1/1                    state_d = TimeoutSt;
           Tests:       T14 T47 T40 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T14 T47 T40 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T14 T47 T40 
172        1/1                    state_d    = Phase0St;
           Tests:       T14 T40 T43 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T14 T40 T43 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T14 T40 T43 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T14 T40 T43 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T14 T47 T40 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T14 T47 T40 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T47 T40 T37 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T47 T40 T37 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T11 T13 T14 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T11 T13 T14 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T11 T13 T14 
190        1/1                  esc_state_o = Phase0;
           Tests:       T11 T13 T14 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T11 T13 T14 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T11 T13 T14 
194        1/1                    state_d = IdleSt;
           Tests:       T31 T125 T69 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T31 T125 T69 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T31 T125 T69 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T11 T13 T14 
198        1/1                    state_d = Phase1St;
           Tests:       T11 T13 T14 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T13 T14 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T11 T13 T14 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T11 T13 T14 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T11 T13 T14 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T11 T13 T14 
207        1/1                  esc_state_o = Phase1;
           Tests:       T11 T13 T14 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T11 T13 T14 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T11 T13 T14 
211        1/1                    state_d = IdleSt;
           Tests:       T33 T128 T129 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T33 T128 T129 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T33 T128 T129 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T11 T13 T14 
215        1/1                    state_d = Phase2St;
           Tests:       T11 T13 T14 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T13 T14 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T11 T13 T14 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T11 T13 T14 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T11 T13 T14 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T11 T13 T14 
224        1/1                  esc_state_o = Phase2;
           Tests:       T11 T13 T14 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T11 T13 T14 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T11 T13 T14 
229        1/1                    state_d = IdleSt;
           Tests:       T130 T131 T132 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T130 T131 T132 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T130 T131 T132 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T11 T13 T14 
233        1/1                    state_d = Phase3St;
           Tests:       T11 T13 T14 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T13 T14 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T11 T13 T14 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T11 T13 T14 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T11 T13 T14 
241        1/1                  esc_state_o = Phase3;
           Tests:       T11 T13 T14 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T11 T13 T14 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T11 T13 T14 
245        1/1                    state_d = IdleSt;
           Tests:       T133 T134 T135 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T133 T134 T135 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T133 T134 T135 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T11 T13 T14 
249        1/1                    state_d = TerminalSt;
           Tests:       T11 T13 T14 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T13 T14 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T11 T13 T14 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T11 T13 T14 
259        1/1                  esc_state_o = Terminal;
           Tests:       T11 T13 T14 
260        1/1                  if (clr_i) begin
           Tests:       T11 T13 T14 
261        1/1                    state_d = IdleSt;
           Tests:       T13 T14 T40 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T7 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T7 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T7 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T7 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T11,T4,T13
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T4,T13

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T10
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T11,T4,T13

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T24,T13
1	0	1	Covered	T16,T40,T52
1	1	0	Covered	T1,T10,T92
1	1	1	Covered	T14,T47,T40

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T47,T40
0	1	Covered	T14,T40,T43
1	0	Covered	T55,T56,T63

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T14,T47,T40
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T55,T56,T63

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T47,T40
1	0	Covered	T41
1	1	Covered	T14,T40,T43

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T13,T14,T51
1	Covered	T11,T13,T40

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T11,T13,T14
1	Covered	T13,T14,T51

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T11,T13,T14
1	Covered	T52,T30,T136

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T11,T13,T14
1	Covered	T14,T35,T19

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T11,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T11,T13,T40

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T11,T13,T40

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T11,T14,T37

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T11,T13,T14
Phase1St	198	Covered	T11,T13,T14
Phase2St	215	Covered	T11,T13,T14
Phase3St	233	Covered	T11,T13,T14
TerminalSt	249	Covered	T11,T13,T14
TimeoutSt	159	Covered	T14,T47,T40

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T11,T13,T14
IdleSt->TimeoutSt	159	Covered	T14,T47,T40
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T54,T31,T137
Phase0St->Phase1St	198	Covered	T11,T13,T14
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T33,T128,T129
Phase1St->Phase2St	215	Covered	T11,T13,T14
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T130,T131,T132
Phase2St->Phase3St	233	Covered	T11,T13,T14
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T133,T134,T135
Phase3St->TerminalSt	249	Covered	T11,T13,T14
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T13,T14,T40
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T47,T40,T37
TimeoutSt->Phase0St	172	Covered	T14,T40,T43

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T4,T13
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T47,T40
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T14,T40,T43
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T14,T47,T40
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T47,T40,T37
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T31,T125,T69
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T11,T13,T14
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T11,T13,T14
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T33,T128,T129
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T11,T13,T14
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T11,T13,T14
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T130,T131,T132
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T11,T13,T14
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T11,T13,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T133,T134,T135
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T11,T13,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T11,T13,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T13,T14,T40
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T11,T13,T14
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	555259424	316	0	0
CheckAccumTrig0_A	555259424	439	0	0
CheckAccumTrig1_A	555259424	22	0	0
CheckClr_A	555259424	186	0	0
CheckEn_A	554926211	220013227	0	0
CheckPhase0_A	555259424	490	0	0
CheckPhase1_A	555259424	479	0	0
CheckPhase2_A	555259424	474	0	0
CheckPhase3_A	555259424	470	0	0
CheckTimeout0_A	555259424	404	0	0
CheckTimeoutSt1_A	555259424	57652	0	0
CheckTimeoutSt2_A	555259424	334	0	0
CheckTimeoutStTrig_A	555259424	43	0	0
ErrorStAllEscAsserted_A	555259424	1461	0	0
ErrorStIsTerminal_A	555259424	1191	0	0
EscStateOut_A	554924711	554857027	0	0
u_state_regs_A	555259424	555076380	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	316	0	0
T7	105398	56	0	0
T8	46501	62	0	0
T9	129775	62	0	0
T20	21411	0	0	0
T44	21022	40	0	0
T45	0	96	0	0
T46	970	0	0	0
T47	31473	0	0	0
T48	108768	0	0	0
T49	90940	0	0	0
T50	14985	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	439	0	0
T4	9209	0	0	0
T5	118518	0	0	0
T11	25614	1	0	0
T13	17053	2	0	0
T14	0	1	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T19	0	1	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T26	91718	0	0	0
T27	5746	0	0	0
T30	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	22	0	0
T55	231043	1	0	0
T56	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	1	0	0
T77	111267	0	0	0
T78	159845	0	0	0
T79	57146	0	0	0
T80	4409	0	0	0
T81	28080	0	0	0
T82	29391	0	0	0
T83	81986	0	0	0
T84	29761	0	0	0
T85	594452	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	186	0	0
T5	118518	0	0	0
T6	13145	0	0	0
T12	14185	0	0	0
T13	17053	1	0	0
T14	0	1	0	0
T17	172611	0	0	0
T26	91718	0	0	0
T27	5746	0	0	0
T28	3406	0	0	0
T29	10092	0	0	0
T31	0	2	0	0
T33	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T54	0	1	0	0
T88	0	1	0	0
T89	0	2	0	0
T90	0	1	0	0
T91	94368	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554926211	220013227	0	0
T1	25397	19839	0	0
T2	21393	21337	0	0
T3	4070	2711	0	0
T4	9209	855	0	0
T10	10559	9051	0	0
T11	25614	2137	0	0
T15	4382	3253	0	0
T16	18381	14656	0	0
T24	25699	21010	0	0
T25	37303	37211	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	490	0	0
T4	9209	0	0	0
T5	118518	0	0	0
T11	25614	1	0	0
T13	17053	2	0	0
T14	0	2	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T26	91718	0	0	0
T27	5746	0	0	0
T30	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	479	0	0
T4	9209	0	0	0
T5	118518	0	0	0
T11	25614	1	0	0
T13	17053	2	0	0
T14	0	2	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T26	91718	0	0	0
T27	5746	0	0	0
T30	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	474	0	0
T4	9209	0	0	0
T5	118518	0	0	0
T11	25614	1	0	0
T13	17053	2	0	0
T14	0	2	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T26	91718	0	0	0
T27	5746	0	0	0
T30	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	470	0	0
T4	9209	0	0	0
T5	118518	0	0	0
T11	25614	1	0	0
T13	17053	2	0	0
T14	0	2	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T26	91718	0	0	0
T27	5746	0	0	0
T30	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	404	0	0
T7	105398	0	0	0
T8	46501	0	0	0
T9	129775	0	0	0
T14	27002	1	0	0
T20	21411	0	0	0
T33	0	2	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T43	0	4	0	0
T44	21022	0	0	0
T46	970	0	0	0
T47	31473	6	0	0
T48	108768	0	0	0
T54	0	5	0	0
T93	41723	0	0	0
T95	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	57652	0	0
T7	105398	0	0	0
T8	46501	0	0	0
T9	129775	0	0	0
T14	27002	743	0	0
T20	21411	0	0	0
T33	0	165	0	0
T37	0	92	0	0
T39	0	119	0	0
T40	0	234	0	0
T41	0	93	0	0
T43	0	1022	0	0
T44	21022	0	0	0
T46	970	0	0	0
T47	31473	567	0	0
T48	108768	0	0	0
T54	0	414	0	0
T93	41723	0	0	0
T95	0	116	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	334	0	0
T32	40474	0	0	0
T33	0	2	0	0
T36	0	8	0	0
T37	127006	1	0	0
T40	48102	1	0	0
T41	0	2	0	0
T43	0	3	0	0
T44	21022	0	0	0
T47	31473	6	0	0
T48	108768	0	0	0
T49	90940	0	0	0
T50	14985	0	0	0
T51	27020	0	0	0
T54	0	3	0	0
T89	0	1	0	0
T95	0	1	0	0
T96	31786	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	43	0	0
T7	105398	0	0	0
T8	46501	0	0	0
T9	129775	0	0	0
T14	27002	1	0	0
T20	21411	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	21022	0	0	0
T46	970	0	0	0
T47	31473	0	0	0
T48	108768	0	0	0
T54	0	1	0	0
T81	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T93	41723	0	0	0
T97	0	1	0	0
T98	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	1461	0	0
T7	105398	337	0	0
T8	46501	332	0	0
T9	129775	319	0	0
T20	21411	0	0	0
T44	21022	160	0	0
T45	0	313	0	0
T46	970	0	0	0
T47	31473	0	0	0
T48	108768	0	0	0
T49	90940	0	0	0
T50	14985	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	1191	0	0
T7	105398	277	0	0
T8	46501	272	0	0
T9	129775	259	0	0
T20	21411	0	0	0
T44	21022	130	0	0
T45	0	253	0	0
T46	970	0	0	0
T47	31473	0	0	0
T48	108768	0	0	0
T49	90940	0	0	0
T50	14985	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554924711	554857027	0	0
T1	25397	25325	0	0
T2	21393	21338	0	0
T3	4070	3971	0	0
T4	9209	9066	0	0
T10	10559	10479	0	0
T11	25614	25515	0	0
T15	4382	4332	0	0
T16	18381	18319	0	0
T24	25699	25646	0	0
T25	37303	37212	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	555076380	0	0
T1	25397	25325	0	0
T2	21393	21338	0	0
T3	4070	3971	0	0
T4	9209	9066	0	0
T10	10559	10479	0	0
T11	25614	25515	0	0
T15	4382	4332	0	0
T16	18381	18319	0	0
T24	25699	25646	0	0
T25	37303	37212	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T10 T11 T25 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T10 T11 T25 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T10 T11 T25 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T29 T92 
159        1/1                    state_d = TimeoutSt;
           Tests:       T1 T29 T92 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T1 T29 T92 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T1 T29 T92 
172        1/1                    state_d    = Phase0St;
           Tests:       T29 T37 T30 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T29 T37 T30 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T29 T37 T30 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T29 T37 T30 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T1 T29 T92 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T29 T92 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T1 T92 T93 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T92 T93 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T11 T25 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T10 T11 T25 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T10 T11 T25 
190        1/1                  esc_state_o = Phase0;
           Tests:       T10 T11 T25 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T10 T11 T25 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T10 T11 T25 
194        1/1                    state_d = IdleSt;
           Tests:       T138 T139 T111 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T138 T139 T111 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T138 T139 T111 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T11 T25 
198        1/1                    state_d = Phase1St;
           Tests:       T10 T11 T25 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T11 T25 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T11 T25 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T11 T25 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T10 T11 T25 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T10 T11 T25 
207        1/1                  esc_state_o = Phase1;
           Tests:       T10 T11 T25 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T10 T11 T25 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T10 T11 T25 
211        1/1                    state_d = IdleSt;
           Tests:       T32 T34 T140 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T34 T140 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T32 T34 T140 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T11 T25 
215        1/1                    state_d = Phase2St;
           Tests:       T10 T11 T25 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T11 T25 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T11 T25 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T11 T25 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T10 T11 T25 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T10 T11 T25 
224        1/1                  esc_state_o = Phase2;
           Tests:       T10 T11 T25 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T10 T11 T25 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T10 T11 T25 
229        1/1                    state_d = IdleSt;
           Tests:       T35 T36 T141 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T36 T141 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T35 T36 T141 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T11 T25 
233        1/1                    state_d = Phase3St;
           Tests:       T10 T11 T25 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T11 T25 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T11 T25 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T10 T11 T25 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T10 T11 T25 
241        1/1                  esc_state_o = Phase3;
           Tests:       T10 T11 T25 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T10 T11 T25 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T10 T11 T25 
245        1/1                    state_d = IdleSt;
           Tests:       T37 T138 T107 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T37 T138 T107 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T37 T138 T107 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T11 T25 
249        1/1                    state_d = TerminalSt;
           Tests:       T10 T11 T25 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T11 T25 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T10 T11 T25 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T10 T11 T25 
259        1/1                  esc_state_o = Terminal;
           Tests:       T10 T11 T25 
260        1/1                  if (clr_i) begin
           Tests:       T10 T11 T25 
261        1/1                    state_d = IdleSt;
           Tests:       T13 T37 T30 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T7 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T7 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T7 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T7 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T10,T11
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T11

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T25

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T13,T28,T17
1	1	0	Covered	T13,T92,T93
1	1	1	Covered	T1,T29,T92

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T29,T92
0	1	Covered	T30,T43,T73
1	0	Covered	T29,T37,T54

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T29,T92
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T29,T37,T54

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T29,T92
1	0	Covered	T37
1	1	Covered	T30,T43,T73

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T11,T25
1	Covered	T13,T28,T32

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T11,T13,T28
1	Covered	T10,T25,T13

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T10,T25,T13
1	Covered	T11,T14,T40

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T10,T11,T25
1	Covered	T29,T37,T142

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T10,T11,T25

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T25,T13,T28

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T11,T13,T28

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T13,T28,T29

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T10,T11,T25
Phase1St	198	Covered	T10,T11,T25
Phase2St	215	Covered	T10,T11,T25
Phase3St	233	Covered	T10,T11,T25
TerminalSt	249	Covered	T10,T11,T25
TimeoutSt	159	Covered	T1,T29,T92

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T10,T11,T25
IdleSt->TimeoutSt	159	Covered	T1,T29,T92
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T43,T33,T54
Phase0St->Phase1St	198	Covered	T10,T11,T25
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T32,T34,T143
Phase1St->Phase2St	215	Covered	T10,T11,T25
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T35,T36,T141
Phase2St->Phase3St	233	Covered	T10,T11,T25
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T37,T138,T107
Phase3St->TerminalSt	249	Covered	T10,T11,T25
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T13,T37,T30
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T92,T93
TimeoutSt->Phase0St	172	Covered	T29,T37,T30

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T25
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T29,T92
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T29,T37,T30
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T29,T92
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T92,T93
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T138,T139,T111
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T10,T11,T25
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T10,T11,T25
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T32,T34,T140
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T10,T11,T25
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T10,T11,T25
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T35,T36,T141
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T10,T11,T25
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T10,T11,T25
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T37,T138,T107
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T10,T11,T25
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T10,T11,T25
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T13,T37,T30
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T10,T11,T25
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	555259424	220	0	0
CheckAccumTrig0_A	555259424	398	0	0
CheckAccumTrig1_A	555259424	16	0	0
CheckClr_A	555259424	147	0	0
CheckEn_A	554926211	255740889	0	0
CheckPhase0_A	555259424	451	0	0
CheckPhase1_A	555259424	442	0	0
CheckPhase2_A	555259424	434	0	0
CheckPhase3_A	555259424	424	0	0
CheckTimeout0_A	555259424	439	0	0
CheckTimeoutSt1_A	555259424	61328	0	0
CheckTimeoutSt2_A	555259424	374	0	0
CheckTimeoutStTrig_A	555259424	47	0	0
ErrorStAllEscAsserted_A	555259424	1443	0	0
ErrorStIsTerminal_A	555259424	1173	0	0
EscStateOut_A	554924711	554857027	0	0
u_state_regs_A	555259424	555076380	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	220	0	0
T7	105398	52	0	0
T8	46501	27	0	0
T9	129775	67	0	0
T20	21411	0	0	0
T44	21022	25	0	0
T45	0	49	0	0
T46	970	0	0	0
T47	31473	0	0	0
T48	108768	0	0	0
T49	90940	0	0	0
T50	14985	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	398	0	0
T4	9209	0	0	0
T10	10559	1	0	0
T11	25614	1	0	0
T13	17053	2	0	0
T14	0	1	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	1	0	0
T26	91718	0	0	0
T27	5746	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T37	0	5	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	16	0	0
T7	105398	0	0	0
T8	46501	0	0	0
T9	129775	0	0	0
T14	27002	0	0	0
T20	21411	0	0	0
T29	10092	1	0	0
T37	0	1	0	0
T42	0	1	0	0
T46	970	0	0	0
T54	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T70	0	2	0	0
T86	14970	0	0	0
T92	80062	0	0	0
T93	41723	0	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	147	0	0
T5	118518	0	0	0
T6	13145	0	0	0
T12	14185	0	0	0
T13	17053	1	0	0
T17	172611	0	0	0
T26	91718	0	0	0
T27	5746	0	0	0
T28	3406	0	0	0
T29	10092	0	0	0
T30	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	0	2	0	0
T36	0	4	0	0
T37	0	5	0	0
T54	0	7	0	0
T76	0	1	0	0
T88	0	1	0	0
T91	94368	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554926211	255740889	0	0
T1	25397	3066	0	0
T2	21393	19097	0	0
T3	4070	2729	0	0
T4	9209	859	0	0
T10	10559	2203	0	0
T11	25614	590	0	0
T15	4382	3282	0	0
T16	18381	18318	0	0
T24	25699	20871	0	0
T25	37303	5626	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	451	0	0
T4	9209	0	0	0
T10	10559	1	0	0
T11	25614	1	0	0
T13	17053	2	0	0
T14	0	1	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	1	0	0
T26	91718	0	0	0
T27	5746	0	0	0
T28	0	1	0	0
T29	0	1	0	0
T32	0	1	0	0
T37	0	6	0	0
T40	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	442	0	0
T4	9209	0	0	0
T10	10559	1	0	0
T11	25614	1	0	0
T13	17053	2	0	0
T14	0	1	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	1	0	0
T26	91718	0	0	0
T27	5746	0	0	0
T28	0	1	0	0
T29	0	1	0	0
T30	0	2	0	0
T37	0	6	0	0
T40	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	434	0	0
T4	9209	0	0	0
T10	10559	1	0	0
T11	25614	1	0	0
T13	17053	2	0	0
T14	0	1	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	1	0	0
T26	91718	0	0	0
T27	5746	0	0	0
T28	0	1	0	0
T29	0	1	0	0
T30	0	2	0	0
T37	0	6	0	0
T40	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	424	0	0
T4	9209	0	0	0
T10	10559	1	0	0
T11	25614	1	0	0
T13	17053	2	0	0
T14	0	1	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	1	0	0
T26	91718	0	0	0
T27	5746	0	0	0
T28	0	1	0	0
T29	0	1	0	0
T30	0	2	0	0
T37	0	5	0	0
T40	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	439	0	0
T1	25397	2	0	0
T2	21393	0	0	0
T3	4070	0	0	0
T4	9209	0	0	0
T10	10559	0	0	0
T11	25614	0	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T29	0	1	0	0
T30	0	1	0	0
T35	0	3	0	0
T37	0	2	0	0
T41	0	1	0	0
T43	0	4	0	0
T47	0	3	0	0
T92	0	5	0	0
T93	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	61328	0	0
T1	25397	460	0	0
T2	21393	0	0	0
T3	4070	0	0	0
T4	9209	0	0	0
T10	10559	0	0	0
T11	25614	0	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T29	0	7	0	0
T30	0	740	0	0
T35	0	109	0	0
T37	0	258	0	0
T41	0	62	0	0
T43	0	652	0	0
T47	0	355	0	0
T92	0	652	0	0
T93	0	50	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	374	0	0
T1	25397	2	0	0
T2	21393	0	0	0
T3	4070	0	0	0
T4	9209	0	0	0
T10	10559	0	0	0
T11	25614	0	0	0
T15	4382	0	0	0
T16	18381	0	0	0
T24	25699	0	0	0
T25	37303	0	0	0
T33	0	4	0	0
T35	0	3	0	0
T37	0	1	0	0
T41	0	1	0	0
T43	0	3	0	0
T47	0	3	0	0
T92	0	5	0	0
T93	0	1	0	0
T95	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	47	0	0
T23	22672	0	0	0
T30	76564	1	0	0
T34	0	1	0	0
T35	19473	0	0	0
T36	0	5	0	0
T38	91974	0	0	0
T43	166364	1	0	0
T54	0	1	0	0
T62	0	1	0	0
T72	82467	0	0	0
T73	67072	1	0	0
T74	1178	0	0	0
T75	26275	0	0	0
T76	19271	0	0	0
T144	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	1443	0	0
T7	105398	320	0	0
T8	46501	320	0	0
T9	129775	344	0	0
T20	21411	0	0	0
T44	21022	179	0	0
T45	0	280	0	0
T46	970	0	0	0
T47	31473	0	0	0
T48	108768	0	0	0
T49	90940	0	0	0
T50	14985	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	1173	0	0
T7	105398	260	0	0
T8	46501	260	0	0
T9	129775	284	0	0
T20	21411	0	0	0
T44	21022	149	0	0
T45	0	220	0	0
T46	970	0	0	0
T47	31473	0	0	0
T48	108768	0	0	0
T49	90940	0	0	0
T50	14985	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554924711	554857027	0	0
T1	25397	25325	0	0
T2	21393	21338	0	0
T3	4070	3971	0	0
T4	9209	9066	0	0
T10	10559	10479	0	0
T11	25614	25515	0	0
T15	4382	4332	0	0
T16	18381	18319	0	0
T24	25699	25646	0	0
T25	37303	37212	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555259424	555076380	0	0
T1	25397	25325	0	0
T2	21393	21338	0	0
T3	4070	3971	0	0
T4	9209	9066	0	0
T10	10559	10479	0	0
T11	25614	25515	0	0
T15	4382	4332	0	0
T16	18381	18319	0	0
T24	25699	25646	0	0
T25	37303	37212	0	0