Module Definition
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Module Instance : tb.dut.u_edn_req.u_prim_packer_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
74.32 100.00 97.30 100.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
74.32 100.00 97.30 100.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 84.62 100.00 100.00 u_edn_req


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_packer_fifo
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS8277100.00
CONT_ASSIGN9400
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00

81 always_ff @(posedge clk_i or negedge rst_ni) begin 82 1/1 if (!rst_ni) begin Tests: T1 T2 T3  83 1/1 depth_q <= '0; Tests: T1 T2 T3  84 1/1 data_q <= '0; Tests: T1 T2 T3  85 1/1 clr_q <= 1'b1; Tests: T1 T2 T3  86 end else begin 87 1/1 depth_q <= depth_d; Tests: T1 T2 T3  88 1/1 data_q <= data_d; Tests: T1 T2 T3  89 1/1 clr_q <= clr_d; Tests: T1 T2 T3  90 end 91 end 92 93 // flop for handling reset case for clr 94 unreachable assign clr_d = clr_i; 95 96 1/1 assign depth_o = depth_q; Tests: T1 T2 T3  97 98 if (InW < OutW) begin : gen_pack_mode 99 logic [MaxW-1:0] wdata_shifted; 100 101 assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW); 102 assign clear_status = (rready_i && rvalid_o) || clr_q; 103 assign clear_data = (ClearOnRead && clear_status) || clr_q; 104 assign load_data = wvalid_i && wready_o; 105 106 assign depth_d = clear_status ? '0 : 107 load_data ? (depth_q + DepthOne): 108 depth_q; 109 110 assign data_d = clear_data ? '0 : 111 load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) : 112 data_q; 113 114 // set outputs 115 assign wready_o = !(depth_q == FullDepth) && !clr_q; 116 assign rdata_o = data_q; 117 assign rvalid_o = (depth_q == FullDepth) && !clr_q; 118 119 end else begin : gen_unpack_mode 120 logic [MaxW-1:0] rdata_shifted; 121 logic pull_data; 122 logic [DepthW:0] ptr_q, ptr_d; 123 logic [DepthW:0] lsb_is_one; 124 logic [DepthW:0] max_value; 125 126 always_ff @(posedge clk_i or negedge rst_ni) begin 127 1/1 if (!rst_ni) begin Tests: T1 T2 T3  128 1/1 ptr_q <= '0; Tests: T1 T2 T3  129 end else begin 130 1/1 ptr_q <= ptr_d; Tests: T1 T2 T3  131 end 132 end 133 134 assign lsb_is_one = {{DepthW{1'b0}},1'b1}; 135 assign max_value = FullDepth; 136 1/1 assign rdata_shifted = data_q >> ptr_q*OutW; Tests: T1 T2 T3  137 1/1 assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q; Tests: T1 T2 T3  138 1/1 assign clear_data = (ClearOnRead && clear_status) || clr_q; Tests: T1 T2 T3  139 1/1 assign load_data = wvalid_i && wready_o; Tests: T1 T2 T3  140 1/1 assign pull_data = rvalid_o && rready_i; Tests: T1 T2 T3  141 142 1/1 assign depth_d = clear_status ? '0 : Tests: T1 T2 T3  143 load_data ? max_value : 144 pull_data ? (depth_q - DepthOne) : 145 depth_q; 146 147 1/1 assign ptr_d = clear_status ? '0 : Tests: T1 T2 T3  148 pull_data ? (ptr_q + DepthOne) : 149 ptr_q; 150 151 1/1 assign data_d = clear_data ? '0 : Tests: T1 T2 T3  152 load_data ? wdata_i : 153 data_q; 154 155 // set outputs 156 1/1 assign wready_o = (depth_q == '0) && !clr_q; Tests: T1 T2 T3  157 1/1 assign rdata_o = rdata_shifted[OutW-1:0]; Tests: T1 T2 T3  158 1/1 assign rvalid_o = !(depth_q == '0) && !clr_q; Tests: T1 T2 T3 

Cond Coverage for Module : prim_packer_fifo
TotalCoveredPercent
Conditions403690.00
Logical403690.00
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT1,T2,T3

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_packer_fifo
Line No.TotalCoveredPercent
Branches 14 12 85.71
TERNARY 142 4 3 75.00
TERNARY 147 3 2 66.67
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00


142 assign depth_d = clear_status ? '0 : -1- ==> 143 load_data ? max_value : -2- ==> 144 pull_data ? (depth_q - DepthOne) : -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


147 assign ptr_d = clear_status ? '0 : -1- ==> 148 pull_data ? (ptr_q + DepthOne) : -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


151 assign data_d = clear_data ? '0 : -1- ==> 152 load_data ? wdata_i : -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


82 if (!rst_ni) begin -1- 83 depth_q <= '0; ==> 84 data_q <= '0; 85 clr_q <= 1'b1; 86 end else begin 87 depth_q <= depth_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


127 if (!rst_ni) begin -1- 128 ptr_q <= '0; ==> 129 end else begin 130 ptr_q <= ptr_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_packer_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 0 0.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 0 0.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 555259424 0 0 617
ValidOPairedWithReadyI_A 555259424 0 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 555259424 0 0 617

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 555259424 0 0 0

Line Coverage for Instance : tb.dut.u_edn_req.u_prim_packer_fifo
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS8277100.00
CONT_ASSIGN9400
CONT_ASSIGN9611100.00
ALWAYS12733100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00

81 always_ff @(posedge clk_i or negedge rst_ni) begin 82 1/1 if (!rst_ni) begin Tests: T1 T2 T3  83 1/1 depth_q <= '0; Tests: T1 T2 T3  84 1/1 data_q <= '0; Tests: T1 T2 T3  85 1/1 clr_q <= 1'b1; Tests: T1 T2 T3  86 end else begin 87 1/1 depth_q <= depth_d; Tests: T1 T2 T3  88 1/1 data_q <= data_d; Tests: T1 T2 T3  89 1/1 clr_q <= clr_d; Tests: T1 T2 T3  90 end 91 end 92 93 // flop for handling reset case for clr 94 unreachable assign clr_d = clr_i; 95 96 1/1 assign depth_o = depth_q; Tests: T1 T2 T3  97 98 if (InW < OutW) begin : gen_pack_mode 99 logic [MaxW-1:0] wdata_shifted; 100 101 assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW); 102 assign clear_status = (rready_i && rvalid_o) || clr_q; 103 assign clear_data = (ClearOnRead && clear_status) || clr_q; 104 assign load_data = wvalid_i && wready_o; 105 106 assign depth_d = clear_status ? '0 : 107 load_data ? (depth_q + DepthOne): 108 depth_q; 109 110 assign data_d = clear_data ? '0 : 111 load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) : 112 data_q; 113 114 // set outputs 115 assign wready_o = !(depth_q == FullDepth) && !clr_q; 116 assign rdata_o = data_q; 117 assign rvalid_o = (depth_q == FullDepth) && !clr_q; 118 119 end else begin : gen_unpack_mode 120 logic [MaxW-1:0] rdata_shifted; 121 logic pull_data; 122 logic [DepthW:0] ptr_q, ptr_d; 123 logic [DepthW:0] lsb_is_one; 124 logic [DepthW:0] max_value; 125 126 always_ff @(posedge clk_i or negedge rst_ni) begin 127 1/1 if (!rst_ni) begin Tests: T1 T2 T3  128 1/1 ptr_q <= '0; Tests: T1 T2 T3  129 end else begin 130 1/1 ptr_q <= ptr_d; Tests: T1 T2 T3  131 end 132 end 133 134 assign lsb_is_one = {{DepthW{1'b0}},1'b1}; 135 assign max_value = FullDepth; 136 1/1 assign rdata_shifted = data_q >> ptr_q*OutW; Tests: T1 T2 T3  137 1/1 assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q; Tests: T1 T2 T3  138 1/1 assign clear_data = (ClearOnRead && clear_status) || clr_q; Tests: T1 T2 T3  139 1/1 assign load_data = wvalid_i && wready_o; Tests: T1 T2 T3  140 1/1 assign pull_data = rvalid_o && rready_i; Tests: T1 T2 T3  141 142 1/1 assign depth_d = clear_status ? '0 : Tests: T1 T2 T3  143 load_data ? max_value : 144 pull_data ? (depth_q - DepthOne) : 145 depth_q; 146 147 1/1 assign ptr_d = clear_status ? '0 : Tests: T1 T2 T3  148 pull_data ? (ptr_q + DepthOne) : 149 ptr_q; 150 151 1/1 assign data_d = clear_data ? '0 : Tests: T1 T2 T3  152 load_data ? wdata_i : 153 data_q; 154 155 // set outputs 156 1/1 assign wready_o = (depth_q == '0) && !clr_q; Tests: T1 T2 T3  157 1/1 assign rdata_o = rdata_shifted[OutW-1:0]; Tests: T1 T2 T3  158 1/1 assign rvalid_o = !(depth_q == '0) && !clr_q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_edn_req.u_prim_packer_fifo
TotalCoveredPercent
Conditions373697.30
Logical373697.30
Non-Logical00
Event00

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT1,T2,T3

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_edn_req.u_prim_packer_fifo
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 142 3 3 100.00
TERNARY 147 2 2 100.00
TERNARY 151 3 3 100.00
IF 82 2 2 100.00
IF 127 2 2 100.00


142 assign depth_d = clear_status ? '0 : -1- ==> 143 load_data ? max_value : -2- ==> 144 pull_data ? (depth_q - DepthOne) : -3- ==> (Excluded) ==>

Branches:
-1--2--3-StatusTestsExclude Annotation
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Excluded VC_COV_UNR
0 0 0 Covered T1,T2,T3


147 assign ptr_d = clear_status ? '0 : -1- ==> 148 pull_data ? (ptr_q + DepthOne) : -2- ==> (Excluded) ==>

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T1,T2,T3
0 1 Excluded VC_COV_UNR
0 0 Covered T1,T2,T3


151 assign data_d = clear_data ? '0 : -1- ==> 152 load_data ? wdata_i : -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


82 if (!rst_ni) begin -1- 83 depth_q <= '0; ==> 84 data_q <= '0; 85 clr_q <= 1'b1; 86 end else begin 87 depth_q <= depth_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


127 if (!rst_ni) begin -1- 128 ptr_q <= '0; ==> 129 end else begin 130 ptr_q <= ptr_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_req.u_prim_packer_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 0 0.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 0 0.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataOStableWhenPending_A 555259424 0 0 617
ValidOPairedWithReadyI_A 555259424 0 0 0


DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 555259424 0 0 617

ValidOPairedWithReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 555259424 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%