Group : tb.dut.u_reg_wrap.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_without_addr_fault_if_proxy::onehot_without_addr_fault_cg
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Group Instance : tb.dut.u_reg_wrap.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tb.dut.u_reg_wrap.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tb.dut.u_reg_wrap.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_onehot_enable_fault 1 0 1 100.00 100 1 1 0
cp_onehot_fault 1 0 1 100.00 100 1 1 0


Summary for Variable cp_onehot_enable_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_onehot_enable_fault

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
hit 39 1 T5 2 T8 6 T9 11



Summary for Variable cp_onehot_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_onehot_fault

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
hit 41 1 T5 8 T8 14 T9 9

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%