Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	50853814	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24100337

1

T1

107

T2

185

T3

91

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	12076341	1			T1	27		T2	65		T3	33
values[0x0]	31379987	1			T1	151		T2	221		T3	148
values[0x1]	31497823	1			T1	172		T2	233		T3	173

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44241117	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

30713034

1

T1

134

T2

232

T3

119

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	232537	1			T2	4		T10	6		T20	6
valid_sources[0x01]	231638	1			T2	1		T10	7		T20	10
valid_sources[0x02]	232750	1			T2	5		T10	6		T20	9
valid_sources[0x03]	235503	1			T2	4		T10	12		T11	15
valid_sources[0x04]	232868	1			T10	8		T20	5		T4	2
valid_sources[0x05]	230180	1			T10	5		T11	4		T20	5
valid_sources[0x06]	229834	1			T2	4		T10	13		T20	14
valid_sources[0x07]	231058	1			T2	6		T10	9		T20	12
valid_sources[0x08]	717443	1			T10	10		T20	10		T4	1
valid_sources[0x09]	235944	1			T10	6		T11	17		T20	10
valid_sources[0x0a]	228510	1			T2	1		T10	12		T11	3
valid_sources[0x0b]	231013	1			T10	10		T11	16		T20	7
valid_sources[0x0c]	231431	1			T2	1		T10	6		T11	19
valid_sources[0x0d]	237417	1			T2	2		T10	5		T20	11
valid_sources[0x0e]	235540	1			T10	8		T20	10		T4	2
valid_sources[0x0f]	248635	1			T2	6		T10	6		T11	8
valid_sources[0x10]	230529	1			T2	3		T10	12		T20	5
valid_sources[0x11]	239853	1			T2	4		T10	15		T20	10
valid_sources[0x12]	230496	1			T2	1		T10	10		T20	9
valid_sources[0x13]	229916	1			T2	4		T10	11		T20	12
valid_sources[0x14]	482332	1			T2	2		T10	9		T11	3
valid_sources[0x15]	273228	1			T2	5		T10	5		T11	1
valid_sources[0x16]	581554	1			T10	10		T20	8		T4	4
valid_sources[0x17]	235325	1			T2	3		T10	8		T20	13
valid_sources[0x18]	268803	1			T2	1		T10	7		T11	10
valid_sources[0x19]	235425	1			T2	2		T10	8		T20	12
valid_sources[0x1a]	489883	1			T10	8		T20	4		T4	8
valid_sources[0x1b]	238295	1			T2	5		T10	11		T11	2
valid_sources[0x1c]	521019	1			T2	4		T10	18		T20	5
valid_sources[0x1d]	532996	1			T2	2		T10	5		T20	13
valid_sources[0x1e]	231253	1			T2	1		T10	6		T11	1
valid_sources[0x1f]	244725	1			T10	8		T20	6		T4	4
valid_sources[0x20]	235975	1			T2	1		T10	4		T20	8
valid_sources[0x21]	242831	1			T2	2		T10	5		T20	3
valid_sources[0x22]	238077	1			T2	3		T10	8		T20	7
valid_sources[0x23]	232034	1			T2	4		T10	9		T20	10
valid_sources[0x24]	264182	1			T2	1		T10	10		T20	8
valid_sources[0x25]	231567	1			T2	1		T10	7		T20	8
valid_sources[0x26]	1220210	1			T2	2		T10	6		T11	6
valid_sources[0x27]	233605	1			T2	1		T10	3		T20	11
valid_sources[0x28]	231356	1			T10	5		T20	4		T4	2
valid_sources[0x29]	244251	1			T2	1		T10	14		T20	7
valid_sources[0x2a]	232081	1			T2	2		T10	11		T20	6
valid_sources[0x2b]	231333	1			T2	2		T10	8		T20	5
valid_sources[0x2c]	231137	1			T10	3		T20	13		T4	5
valid_sources[0x2d]	235277	1			T10	17		T20	7		T4	1
valid_sources[0x2e]	591986	1			T2	3		T10	12		T11	3
valid_sources[0x2f]	232838	1			T10	12		T20	7		T4	2
valid_sources[0x30]	235591	1			T2	5		T10	10		T20	8
valid_sources[0x31]	227946	1			T10	8		T20	7		T4	1
valid_sources[0x32]	230958	1			T2	1		T10	7		T20	7
valid_sources[0x33]	232333	1			T10	7		T20	10		T4	1
valid_sources[0x34]	240924	1			T2	2		T10	7		T11	8
valid_sources[0x35]	232357	1			T10	5		T20	13		T4	2
valid_sources[0x36]	232451	1			T2	1		T10	11		T20	8
valid_sources[0x37]	627148	1			T2	1		T10	12		T20	7
valid_sources[0x38]	236917	1			T10	4		T20	10		T4	2
valid_sources[0x39]	238196	1			T1	350		T2	2		T10	13
valid_sources[0x3a]	234259	1			T2	1		T10	12		T20	8
valid_sources[0x3b]	233527	1			T10	9		T11	7		T20	7
valid_sources[0x3c]	667539	1			T2	3		T10	5		T11	2
valid_sources[0x3d]	237856	1			T2	4		T10	5		T11	1
valid_sources[0x3e]	229978	1			T2	3		T10	10		T20	7
valid_sources[0x3f]	490823	1			T2	1		T10	12		T20	6
valid_sources[0x40]	230756	1			T2	4		T10	5		T20	9
valid_sources[0x41]	239446	1			T10	7		T20	2		T4	3
valid_sources[0x42]	256289	1			T2	1		T10	9		T20	11
valid_sources[0x43]	236429	1			T2	1		T10	13		T11	8
valid_sources[0x44]	235972	1			T10	10		T20	7		T4	1
valid_sources[0x45]	234276	1			T2	1		T10	11		T20	8
valid_sources[0x46]	231125	1			T10	9		T11	5		T20	10
valid_sources[0x47]	258767	1			T2	3		T10	9		T20	9
valid_sources[0x48]	230400	1			T2	3		T10	8		T11	1
valid_sources[0x49]	594876	1			T10	8		T20	7		T4	3
valid_sources[0x4a]	240567	1			T10	8		T20	9		T15	30
valid_sources[0x4b]	581354	1			T2	2		T10	8		T11	9
valid_sources[0x4c]	229481	1			T2	1		T10	3		T20	6
valid_sources[0x4d]	238514	1			T2	2		T10	10		T20	8
valid_sources[0x4e]	230124	1			T2	5		T10	8		T20	12
valid_sources[0x4f]	233881	1			T2	3		T10	10		T20	10
valid_sources[0x50]	235807	1			T2	1		T10	7		T11	8
valid_sources[0x51]	230800	1			T10	9		T11	5		T20	7
valid_sources[0x52]	236360	1			T10	6		T20	9		T4	2
valid_sources[0x53]	699096	1			T2	4		T10	10		T20	14
valid_sources[0x54]	552682	1			T2	1		T10	15		T11	1
valid_sources[0x55]	236586	1			T10	9		T20	7		T4	2
valid_sources[0x56]	236505	1			T2	1		T10	5		T11	5
valid_sources[0x57]	237833	1			T2	5		T10	6		T20	7
valid_sources[0x58]	230314	1			T10	14		T20	8		T4	2
valid_sources[0x59]	240539	1			T2	1		T10	12		T20	8
valid_sources[0x5a]	230780	1			T2	1		T10	7		T20	5
valid_sources[0x5b]	229576	1			T10	6		T20	7		T4	2
valid_sources[0x5c]	228232	1			T2	7		T10	6		T11	1
valid_sources[0x5d]	238272	1			T2	1		T10	10		T11	5
valid_sources[0x5e]	234554	1			T2	1		T10	9		T20	10
valid_sources[0x5f]	230017	1			T2	1		T10	11		T11	20
valid_sources[0x60]	232318	1			T2	1		T10	6		T20	4
valid_sources[0x61]	231946	1			T2	4		T10	11		T20	9
valid_sources[0x62]	458210	1			T2	8		T10	7		T20	13
valid_sources[0x63]	236406	1			T2	1		T10	2		T20	4
valid_sources[0x64]	233121	1			T10	5		T20	11		T4	2
valid_sources[0x65]	235603	1			T10	5		T20	12		T15	35
valid_sources[0x66]	242881	1			T2	3		T10	15		T20	10
valid_sources[0x67]	232101	1			T10	16		T11	8		T20	8
valid_sources[0x68]	233000	1			T2	3		T10	13		T20	5
valid_sources[0x69]	246687	1			T2	8		T10	9		T20	10
valid_sources[0x6a]	702934	1			T2	6		T10	8		T11	5
valid_sources[0x6b]	257565	1			T2	2		T10	10		T20	9
valid_sources[0x6c]	231014	1			T2	5		T10	7		T11	2
valid_sources[0x6d]	245572	1			T10	8		T11	10		T20	7
valid_sources[0x6e]	231823	1			T2	3		T10	10		T11	11
valid_sources[0x6f]	238325	1			T2	6		T10	8		T20	8
valid_sources[0x70]	232524	1			T10	8		T20	7		T4	3
valid_sources[0x71]	229560	1			T2	1		T10	5		T20	10
valid_sources[0x72]	236041	1			T10	7		T20	5		T4	1
valid_sources[0x73]	590631	1			T10	7		T11	4		T20	6
valid_sources[0x74]	240705	1			T3	354		T10	4		T20	10
valid_sources[0x75]	236166	1			T2	1		T10	11		T11	6
valid_sources[0x76]	231766	1			T10	7		T11	1		T20	10
valid_sources[0x77]	233548	1			T2	1		T10	10		T20	3
valid_sources[0x78]	230498	1			T2	3		T10	6		T20	9
valid_sources[0x79]	232435	1			T2	4		T10	14		T20	7
valid_sources[0x7a]	234473	1			T2	1		T10	8		T11	4
valid_sources[0x7b]	242223	1			T2	3		T10	7		T11	3
valid_sources[0x7c]	810605	1			T2	3		T10	13		T20	3
valid_sources[0x7d]	229374	1			T2	5		T10	6		T11	6
valid_sources[0x7e]	232010	1			T2	1		T10	8		T20	10
valid_sources[0x7f]	573396	1			T2	1		T10	6		T20	9
valid_sources[0x80]	233040	1			T2	2		T10	6		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5765776

1

T1

17

T2

33

T3

11

values[0x0]

all_enables

biggest_size

11706822

1

T1

51

T2

93

T3

56

values[0x1]

all_enables

biggest_size

6627739

1

T1

39

T2

59

T3

24