Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T13
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T14
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T10

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2146728508	15423	0	0
DisabledNoTrigBkwd_A	2146728508	575652	0	0
DisabledNoTrigFwd_A	2146728508	1197221589	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2146728508	15423	0	0
T1	1832	599	0	0
T2	4638	0	0	0
T3	1737	779	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T7	14728	0	0	0
T8	41275	0	0	0
T9	40062	0	0	0
T10	16916	0	0	0
T11	3660	0	0	0
T13	16089	0	0	0
T14	2924	569	0	0
T15	25445	0	0	0
T20	15700	0	0	0
T26	44861	0	0	0
T38	81327	0	0	0
T44	34155	0	0	0
T49	0	930	0	0
T51	0	464	0	0
T67	8696	0	0	0
T68	109253	0	0	0
T69	4032	853	0	0
T114	4716	1364	0	0
T140	0	287	0	0
T217	0	1014	0	0
T218	0	1151	0	0
T219	0	1678	0	0
T220	0	1096	0	0
T221	0	323	0	0
T222	0	314	0	0
T223	0	617	0	0
T224	0	893	0	0
T225	0	564	0	0
T226	0	943	0	0
T227	0	760	0	0
T228	0	225	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2146728508	575652	0	0
T1	1832	9	0	0
T2	4638	0	0	0
T3	3474	12	0	0
T4	58860	0	0	0
T5	218536	0	0	0
T6	200733	0	0	0
T10	67664	240	0	0
T11	14640	0	0	0
T12	20712	6	0	0
T13	64356	458	0	0
T14	0	12	0	0
T15	101780	5	0	0
T16	38656	3	0	0
T20	62800	22	0	0
T25	0	62	0	0
T26	0	72	0	0
T36	0	44	0	0
T38	0	19	0	0
T44	0	59	0	0
T45	0	5	0	0
T46	0	3	0	0
T47	0	13	0	0
T48	0	6	0	0
T50	0	9	0	0
T51	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2146728508	1197221589	0	0
T1	7328	4016	0	0
T2	18552	13235	0	0
T3	6948	3268	0	0
T4	58860	8975	0	0
T5	218536	166708	0	0
T10	67664	26937	0	0
T11	14640	11385	0	0
T13	64356	28876	0	0
T15	101780	67174	0	0
T20	62800	48850	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T10 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T13,T5
1	1	Covered	T1,T2,T10

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T69,T217
1	1	Covered	T1,T2,T10

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T20

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	536682127	4119	0	0
DisabledNoTrigBkwd_A	536682127	154282	0	0
DisabledNoTrigFwd_A	536682127	280486059	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	4119	0	0
T1	1832	599	0	0
T2	4638	0	0	0
T3	1737	0	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T10	16916	0	0	0
T11	3660	0	0	0
T13	16089	0	0	0
T15	25445	0	0	0
T20	15700	0	0	0
T69	0	853	0	0
T217	0	1014	0	0
T224	0	893	0	0
T227	0	760	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	154282	0	0
T1	1832	9	0	0
T2	4638	0	0	0
T3	1737	0	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T10	16916	3	0	0
T11	3660	0	0	0
T12	0	4	0	0
T13	16089	436	0	0
T15	25445	5	0	0
T16	0	3	0	0
T20	15700	22	0	0
T25	0	62	0	0
T26	0	4	0	0
T44	0	59	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	280486059	0	0
T1	1832	998	0	0
T2	4638	2046	0	0
T3	1737	811	0	0
T4	14715	2229	0	0
T5	54634	41677	0	0
T10	16916	9509	0	0
T11	3660	582	0	0
T13	16089	9180	0	0
T15	25445	582	0	0
T20	15700	1933	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T2 T10 T11 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T13,T12
1	1	Covered	T2,T10,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T49,T140
1	1	Covered	T2,T10,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T4,T13

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	536682127	4687	0	0
DisabledNoTrigBkwd_A	536682127	124599	0	0
DisabledNoTrigFwd_A	536682127	320372827	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	4687	0	0
T7	14728	0	0	0
T8	41275	0	0	0
T9	40062	0	0	0
T14	2924	569	0	0
T26	44861	0	0	0
T38	81327	0	0	0
T44	34155	0	0	0
T49	0	930	0	0
T67	8696	0	0	0
T68	109253	0	0	0
T69	4032	0	0	0
T140	0	287	0	0
T220	0	1096	0	0
T221	0	323	0	0
T222	0	314	0	0
T226	0	943	0	0
T228	0	225	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	124599	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T10	16916	2	0	0
T11	3660	0	0	0
T12	6904	0	0	0
T13	16089	6	0	0
T14	0	12	0	0
T15	25445	0	0	0
T16	19328	0	0	0
T20	15700	0	0	0
T26	0	21	0	0
T36	0	32	0	0
T38	0	18	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	5	0	0
T48	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	320372827	0	0
T1	1832	1002	0	0
T2	4638	2065	0	0
T3	1737	815	0	0
T4	14715	2240	0	0
T5	54634	41677	0	0
T10	16916	3960	0	0
T11	3660	3601	0	0
T13	16089	6905	0	0
T15	25445	20617	0	0
T20	15700	15639	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T2 T10 T11 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T2,T10,T13
1	1	Covered	T10,T13,T12

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T114
1	1	Covered	T10,T13,T12

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T13,T12,T26
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T13,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	536682127	1364	0	0
DisabledNoTrigBkwd_A	536682127	176940	0	0
DisabledNoTrigFwd_A	536682127	283515367	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	1364	0	0
T19	571652	0	0	0
T24	44739	0	0	0
T41	330660	0	0	0
T73	47777	0	0	0
T80	107966	0	0	0
T114	4716	1364	0	0
T121	343556	0	0	0
T122	107245	0	0	0
T123	143872	0	0	0
T124	451722	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	176940	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T10	16916	3	0	0
T11	3660	0	0	0
T12	6904	2	0	0
T13	16089	4	0	0
T15	25445	0	0	0
T16	19328	0	0	0
T20	15700	0	0	0
T26	0	14	0	0
T36	0	3	0	0
T38	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	5	0	0
T48	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	283515367	0	0
T1	1832	1006	0	0
T2	4638	4562	0	0
T3	1737	819	0	0
T4	14715	2246	0	0
T5	54634	41677	0	0
T10	16916	9508	0	0
T11	3660	3601	0	0
T13	16089	7860	0	0
T15	25445	25358	0	0
T20	15700	15639	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T2 T3 T10 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T2,T10,T13
1	1	Covered	T3,T10,T13

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T51,T218
1	1	Covered	T3,T10,T13

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T10,T13

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	536682127	5253	0	0
DisabledNoTrigBkwd_A	536682127	119831	0	0
DisabledNoTrigFwd_A	536682127	312847336	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	5253	0	0
T3	1737	779	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T10	16916	0	0	0
T11	3660	0	0	0
T12	6904	0	0	0
T13	16089	0	0	0
T15	25445	0	0	0
T20	15700	0	0	0
T51	0	464	0	0
T218	0	1151	0	0
T219	0	1678	0	0
T223	0	617	0	0
T225	0	564	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	119831	0	0
T3	1737	12	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T10	16916	232	0	0
T11	3660	0	0	0
T12	6904	0	0	0
T13	16089	12	0	0
T15	25445	0	0	0
T20	15700	0	0	0
T26	0	33	0	0
T36	0	9	0	0
T45	0	3	0	0
T47	0	3	0	0
T48	0	2	0	0
T50	0	9	0	0
T51	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	312847336	0	0
T1	1832	1010	0	0
T2	4638	4562	0	0
T3	1737	823	0	0
T4	14715	2260	0	0
T5	54634	41677	0	0
T10	16916	3960	0	0
T11	3660	3601	0	0
T13	16089	4931	0	0
T15	25445	20617	0	0
T20	15700	15639	0	0