Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.87	100.00	89.36		70.00	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T1 T3 T10 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T1 T3 T10 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T1 T3 T10 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T15 T13 
159        1/1                    state_d = TimeoutSt;
           Tests:       T2 T15 T13 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T2 T15 T13 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T2 T15 T13 
172        1/1                    state_d    = Phase0St;
           Tests:       T13 T26 T27 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T13 T26 T27 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T13 T26 T27 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T13 T26 T27 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T2 T15 T13 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T15 T13 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T2 T15 T16 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T15 T16 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T10 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T1 T3 T10 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T1 T3 T10 
190        1/1                  esc_state_o = Phase0;
           Tests:       T1 T3 T10 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T1 T3 T10 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T1 T3 T10 
194        1/1                    state_d = IdleSt;
           Tests:       T28 T29 T30 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T28 T29 T30 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T28 T29 T30 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T10 
198        1/1                    state_d = Phase1St;
           Tests:       T1 T3 T10 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T10 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T3 T10 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T10 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T1 T3 T10 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T1 T3 T10 
207        1/1                  esc_state_o = Phase1;
           Tests:       T1 T3 T10 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T1 T3 T10 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T1 T3 T10 
211        1/1                    state_d = IdleSt;
           Tests:       T27 T29 T31 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T27 T29 T31 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T27 T29 T31 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T10 
215        1/1                    state_d = Phase2St;
           Tests:       T1 T3 T10 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T10 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T3 T10 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T10 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T1 T3 T10 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T1 T3 T10 
224        1/1                  esc_state_o = Phase2;
           Tests:       T1 T3 T10 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T1 T3 T10 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T1 T3 T10 
229        1/1                    state_d = IdleSt;
           Tests:       T32 T33 T34 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T33 T34 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T32 T33 T34 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T10 
233        1/1                    state_d = Phase3St;
           Tests:       T1 T3 T10 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T10 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T10 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T1 T3 T10 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T1 T3 T10 
241        1/1                  esc_state_o = Phase3;
           Tests:       T1 T3 T10 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T1 T3 T10 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T1 T3 T10 
245        1/1                    state_d = IdleSt;
           Tests:       T15 T35 T28 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T15 T35 T28 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T15 T35 T28 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T10 
249        1/1                    state_d = TerminalSt;
           Tests:       T1 T3 T10 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T10 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T1 T3 T10 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T3 T10 
259        1/1                  esc_state_o = Terminal;
           Tests:       T1 T3 T10 
260        1/1                  if (clr_i) begin
           Tests:       T1 T3 T10 
261        1/1                    state_d = IdleSt;
           Tests:       T10 T15 T13 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T5 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T5 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T5 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T5 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	42	89.36
Logical	47	42	89.36
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T10

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T15,T13
1	0	1	Covered	T1,T3,T14
1	1	0	Covered	T13,T12,T26
1	1	1	Covered	T2,T15,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T15,T13
0	1	Covered	T13,T36,T37
1	0	Covered	T26,T27,T36

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T15,T13
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T26,T27,T36

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T13
1	0	Not Covered
1	1	Covered	T13,T36,T37

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T20,T15
1	Covered	T1,T10,T13

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T25,T26,T38

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T15,T13,T25

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T10,T15
1	Covered	T10,T20,T13

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T10,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T10,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T10,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T10,T20

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T10
Phase1St	198	Covered	T1,T3,T10
Phase2St	215	Covered	T1,T3,T10
Phase3St	233	Covered	T1,T3,T10
TerminalSt	249	Covered	T1,T3,T10
TimeoutSt	159	Covered	T2,T15,T13

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T5,T8,T9
IdleSt->Phase0St	152	Covered	T1,T3,T10
IdleSt->TimeoutSt	159	Covered	T2,T15,T13
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T39,T28,T29
Phase0St->Phase1St	198	Covered	T1,T3,T10
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T27,T40,T29
Phase1St->Phase2St	215	Covered	T1,T3,T10
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T32,T41,T33
Phase2St->Phase3St	233	Covered	T1,T3,T10
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T15,T35,T28
Phase3St->TerminalSt	249	Covered	T1,T3,T10
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T10,T15,T13
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T2,T15,T16
TimeoutSt->Phase0St	172	Covered	T13,T26,T27

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T10
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T15,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T13,T26,T27
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T15,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T15,T16
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T29,T30
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T10
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T10,T20,T15
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T27,T29,T31
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T10
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T10,T20,T15
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T32,T33,T34
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T10
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T10,T20,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T15,T35,T28
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T10,T20,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T15,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T10
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2146728508	989	0	0
CheckAccumTrig0_A	2146728508	2159	0	0
CheckAccumTrig1_A	2146728508	110	0	0
CheckClr_A	2146728508	997	0	0
CheckEn_A	2145940784	941156961	0	0
CheckPhase0_A	2146728508	2428	0	0
CheckPhase1_A	2146728508	2363	0	0
CheckPhase2_A	2146728508	2327	0	0
CheckPhase3_A	2146728508	2283	0	0
CheckTimeout0_A	2146728508	2228	0	0
CheckTimeoutSt1_A	2146728508	274421	0	0
CheckTimeoutSt2_A	2146728508	1880	0	0
CheckTimeoutStTrig_A	2146728508	228	0	0
ErrorStAllEscAsserted_A	2146728508	5144	0	0
ErrorStIsTerminal_A	2146728508	4184	0	0
EscStateOut_A	2145935536	2145662304	0	0
u_state_regs_A	2146728508	2146044560	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2146728508	989	0	0
T5	218536	88	0	0
T6	267644	0	0	0
T7	58912	0	0	0
T8	165100	281	0	0
T9	0	258	0	0
T12	27616	0	0	0
T14	11696	0	0	0
T16	77312	0	0	0
T25	189936	0	0	0
T26	179444	0	0	0
T42	0	249	0	0
T43	0	113	0	0
T44	136620	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2146728508	2159	0	0
T1	1832	1	0	0
T2	4638	0	0	0
T3	3474	1	0	0
T4	58860	0	0	0
T5	218536	0	0	0
T6	200733	0	0	0
T10	67664	5	0	0
T11	14640	0	0	0
T12	20712	2	0	0
T13	64356	6	0	0
T14	0	1	0	0
T15	101780	4	0	0
T16	38656	2	0	0
T20	62800	1	0	0
T25	0	2	0	0
T26	0	3	0	0
T36	0	3	0	0
T38	0	3	0	0
T44	0	1	0	0
T45	0	3	0	0
T46	0	2	0	0
T47	0	5	0	0
T48	0	3	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2146728508	110	0	0
T7	29456	0	0	0
T9	80124	0	0	0
T17	248991	0	0	0
T26	89722	2	0	0
T27	41094	1	0	0
T29	0	1	0	0
T31	0	2	0	0
T32	21848	1	0	0
T36	79607	1	0	0
T37	35823	0	0	0
T38	162654	0	0	0
T41	330660	0	0	0
T42	43652	0	0	0
T44	68310	0	0	0
T45	29212	0	0	0
T46	7013	0	0	0
T47	32265	0	0	0
T48	27485	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	17392	0	0	0
T68	218506	0	0	0
T69	8064	0	0	0
T70	193944	0	0	0
T71	43325	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2146728508	997	0	0
T4	58860	0	0	0
T5	218536	0	0	0
T6	267644	0	0	0
T10	67664	3	0	0
T11	14640	0	0	0
T12	27616	1	0	0
T13	64356	4	0	0
T15	101780	3	0	0
T16	77312	2	0	0
T20	62800	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	7	0	0
T32	0	2	0	0
T35	0	1	0	0
T36	0	4	0	0
T38	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T54	0	2	0	0
T72	0	1	0	0
T73	0	5	0	0
T74	0	3	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2145940784	941156961	0	0
T1	7328	4016	0	0
T2	18552	13233	0	0
T3	6948	3268	0	0
T4	58860	8971	0	0
T5	3476	3096	0	0
T10	67664	25021	0	0
T11	14640	11382	0	0
T13	64356	23063	0	0
T15	101780	67171	0	0
T20	62800	48847	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2146728508	2428	0	0
T1	1832	1	0	0
T2	4638	0	0	0
T3	3474	1	0	0
T4	58860	0	0	0
T5	218536	0	0	0
T6	200733	0	0	0
T10	67664	5	0	0
T11	14640	0	0	0
T12	20712	2	0	0
T13	64356	8	0	0
T14	0	1	0	0
T15	101780	4	0	0
T16	38656	2	0	0
T20	62800	1	0	0
T25	0	2	0	0
T26	0	5	0	0
T36	0	8	0	0
T37	0	1	0	0
T38	0	3	0	0
T44	0	1	0	0
T45	0	3	0	0
T46	0	2	0	0
T47	0	5	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2146728508	2363	0	0
T1	1832	1	0	0
T2	4638	0	0	0
T3	3474	1	0	0
T4	58860	0	0	0
T5	218536	0	0	0
T6	200733	0	0	0
T10	67664	5	0	0
T11	14640	0	0	0
T12	20712	2	0	0
T13	64356	8	0	0
T14	0	1	0	0
T15	101780	4	0	0
T16	38656	2	0	0
T20	62800	1	0	0
T25	0	2	0	0
T26	0	5	0	0
T36	0	8	0	0
T37	0	1	0	0
T38	0	3	0	0
T44	0	1	0	0
T45	0	3	0	0
T46	0	2	0	0
T47	0	5	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2146728508	2327	0	0
T1	1832	1	0	0
T2	4638	0	0	0
T3	3474	1	0	0
T4	58860	0	0	0
T5	218536	0	0	0
T6	200733	0	0	0
T10	67664	5	0	0
T11	14640	0	0	0
T12	20712	2	0	0
T13	64356	8	0	0
T14	0	1	0	0
T15	101780	4	0	0
T16	38656	2	0	0
T20	62800	1	0	0
T25	0	2	0	0
T26	0	5	0	0
T36	0	8	0	0
T37	0	1	0	0
T38	0	3	0	0
T44	0	1	0	0
T45	0	3	0	0
T46	0	2	0	0
T47	0	5	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2146728508	2283	0	0
T1	1832	1	0	0
T2	4638	0	0	0
T3	3474	1	0	0
T4	58860	0	0	0
T5	218536	0	0	0
T6	200733	0	0	0
T10	67664	5	0	0
T11	14640	0	0	0
T12	20712	2	0	0
T13	64356	8	0	0
T14	0	1	0	0
T15	101780	3	0	0
T16	38656	2	0	0
T20	62800	1	0	0
T25	0	2	0	0
T26	0	5	0	0
T36	0	8	0	0
T37	0	1	0	0
T38	0	3	0	0
T44	0	1	0	0
T45	0	3	0	0
T46	0	2	0	0
T47	0	5	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2146728508	2228	0	0
T2	4638	1	0	0
T3	1737	0	0	0
T4	14715	0	0	0
T5	109268	0	0	0
T6	66911	0	0	0
T7	44184	0	0	0
T9	80124	0	0	0
T10	16916	0	0	0
T11	3660	0	0	0
T12	13808	0	0	0
T13	32178	1	0	0
T15	25445	1	0	0
T16	0	3	0	0
T20	15700	0	0	0
T26	134583	2	0	0
T27	0	1	0	0
T32	0	1	0	0
T36	0	8	0	0
T37	0	1	0	0
T38	162654	3	0	0
T41	0	2	0	0
T44	68310	2	0	0
T45	29212	0	0	0
T48	0	1	0	0
T50	0	1	0	0
T67	17392	0	0	0
T68	218506	25	0	0
T69	8064	0	0	0
T70	193944	1	0	0
T71	0	15	0	0
T73	0	1	0	0
T78	0	2	0	0
T79	0	1	0	0
T80	0	9	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2146728508	274421	0	0
T2	4638	122	0	0
T3	1737	0	0	0
T4	14715	0	0	0
T5	109268	0	0	0
T6	66911	0	0	0
T7	44184	0	0	0
T9	80124	0	0	0
T10	16916	0	0	0
T11	3660	0	0	0
T12	13808	0	0	0
T13	32178	221	0	0
T15	25445	179	0	0
T16	0	131	0	0
T20	15700	0	0	0
T26	134583	18	0	0
T27	0	9	0	0
T36	0	3254	0	0
T37	0	705	0	0
T38	162654	359	0	0
T41	0	238	0	0
T44	68310	151	0	0
T45	29212	0	0	0
T48	0	48	0	0
T50	0	117	0	0
T67	17392	0	0	0
T68	218506	5277	0	0
T69	8064	0	0	0
T70	193944	128	0	0
T71	0	1332	0	0
T73	0	253	0	0
T78	0	299	0	0
T79	0	933	0	0
T80	0	1644	0	0
T81	0	815	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2146728508	1880	0	0
T2	4638	1	0	0
T3	1737	0	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T9	120186	0	0	0
T10	16916	0	0	0
T11	3660	0	0	0
T12	6904	0	0	0
T13	16089	0	0	0
T15	25445	1	0	0
T16	0	3	0	0
T20	15700	0	0	0
T27	123282	0	0	0
T36	238821	4	0	0
T37	0	8	0	0
T38	0	3	0	0
T41	0	8	0	0
T42	130956	0	0	0
T44	0	2	0	0
T45	43818	0	0	0
T46	21039	0	0	0
T48	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T68	327759	25	0	0
T69	12096	0	0	0
T70	290916	1	0	0
T71	129975	15	0	0
T73	0	1	0	0
T74	0	1	0	0
T78	0	2	0	0
T80	0	9	0	0
T81	0	6	0	0
T82	0	1	0	0
T83	0	8	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2146728508	228	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T7	14728	0	0	0
T8	41275	0	0	0
T12	6904	0	0	0
T13	16089	1	0	0
T14	2924	0	0	0
T16	19328	0	0	0
T17	248991	0	0	0
T25	47484	0	0	0
T26	44861	0	0	0
T28	0	1	0	0
T31	0	3	0	0
T32	21848	0	0	0
T36	79607	3	0	0
T37	35823	1	0	0
T40	0	3	0	0
T41	0	3	0	0
T42	43652	0	0	0
T47	32265	0	0	0
T48	27485	0	0	0
T49	3442	0	0	0
T53	0	1	0	0
T61	0	1	0	0
T71	43325	0	0	0
T72	29350	0	0	0
T77	0	2	0	0
T79	43777	1	0	0
T84	0	1	0	0
T85	0	2	0	0
T86	0	4	0	0
T87	0	2	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	2	0	0
T93	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2146728508	5144	0	0
T5	218536	583	0	0
T6	267644	0	0	0
T7	58912	0	0	0
T8	165100	1324	0	0
T9	0	1317	0	0
T12	27616	0	0	0
T14	11696	0	0	0
T16	77312	0	0	0
T25	189936	0	0	0
T26	179444	0	0	0
T42	0	1302	0	0
T43	0	618	0	0
T44	136620	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2146728508	4184	0	0
T5	218536	463	0	0
T6	267644	0	0	0
T7	58912	0	0	0
T8	165100	1084	0	0
T9	0	1077	0	0
T12	27616	0	0	0
T14	11696	0	0	0
T16	77312	0	0	0
T25	189936	0	0	0
T26	179444	0	0	0
T42	0	1062	0	0
T43	0	498	0	0
T44	136620	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2145935536	2145662304	0	0
T1	7328	6952	0	0
T2	18552	18248	0	0
T3	6948	6636	0	0
T4	58860	58164	0	0
T5	1544	1168	0	0
T10	67664	67340	0	0
T11	14640	14404	0	0
T13	64356	64032	0	0
T15	101780	101432	0	0
T20	62800	62556	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2146728508	2146044560	0	0
T1	7328	6952	0	0
T2	18552	18248	0	0
T3	6948	6636	0	0
T4	58860	58164	0	0
T5	218536	166708	0	0
T10	67664	67340	0	0
T11	14640	14404	0	0
T13	64356	64032	0	0
T15	101780	101432	0	0
T20	62800	62556	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T1 T10 T20 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T1 T10 T20 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T1 T10 T20 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T15 T13 
159        1/1                    state_d = TimeoutSt;
           Tests:       T2 T15 T13 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T2 T15 T13 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T2 T15 T13 
172        1/1                    state_d    = Phase0St;
           Tests:       T13 T27 T32 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T13 T27 T32 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T13 T27 T32 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T13 T27 T32 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T2 T15 T13 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T15 T13 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T2 T15 T16 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T15 T16 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T10 T20 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T1 T10 T20 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T1 T10 T20 
190        1/1                  esc_state_o = Phase0;
           Tests:       T1 T10 T20 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T1 T10 T20 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T1 T10 T20 
194        1/1                    state_d = IdleSt;
           Tests:       T29 T94 T95 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T29 T94 T95 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T29 T94 T95 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T10 T20 
198        1/1                    state_d = Phase1St;
           Tests:       T1 T10 T20 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T10 T20 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T10 T20 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T10 T20 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T1 T10 T20 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T1 T10 T20 
207        1/1                  esc_state_o = Phase1;
           Tests:       T1 T10 T20 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T1 T10 T20 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T1 T10 T20 
211        1/1                    state_d = IdleSt;
           Tests:       T27 T58 T96 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T27 T58 T96 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T27 T58 T96 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T10 T20 
215        1/1                    state_d = Phase2St;
           Tests:       T1 T10 T20 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T10 T20 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T10 T20 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T10 T20 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T1 T10 T20 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T1 T10 T20 
224        1/1                  esc_state_o = Phase2;
           Tests:       T1 T10 T20 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T1 T10 T20 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T1 T10 T20 
229        1/1                    state_d = IdleSt;
           Tests:       T32 T97 T98 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T97 T98 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T32 T97 T98 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T10 T20 
233        1/1                    state_d = Phase3St;
           Tests:       T1 T10 T20 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T10 T20 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T10 T20 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T1 T10 T20 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T1 T10 T20 
241        1/1                  esc_state_o = Phase3;
           Tests:       T1 T10 T20 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T1 T10 T20 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T1 T10 T20 
245        1/1                    state_d = IdleSt;
           Tests:       T15 T35 T99 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T15 T35 T99 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T15 T35 T99 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T10 T20 
249        1/1                    state_d = TerminalSt;
           Tests:       T1 T10 T20 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T10 T20 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T1 T10 T20 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T10 T20 
259        1/1                  esc_state_o = Terminal;
           Tests:       T1 T10 T20 
260        1/1                  if (clr_i) begin
           Tests:       T1 T10 T20 
261        1/1                    state_d = IdleSt;
           Tests:       T10 T15 T13 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T5 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T5 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T5 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T5 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T2,T10
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T10

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T10,T20

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T15,T13
1	0	1	Covered	T1,T69,T46
1	1	0	Covered	T13,T12,T68
1	1	1	Covered	T2,T15,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T15,T13
0	1	Covered	T13,T41,T53
1	0	Covered	T27,T32,T52

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T15,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T27,T32,T52

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T13
1	0	Not Covered
1	1	Covered	T13,T41,T53

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T20,T15
1	Covered	T1,T13,T12

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T10,T20
1	Covered	T25,T27,T39

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T10,T20
1	Covered	T15,T13,T25

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T15,T13
1	Covered	T10,T20,T38

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T10,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T10,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T10,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T10,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T10,T20
Phase1St	198	Covered	T1,T10,T20
Phase2St	215	Covered	T1,T10,T20
Phase3St	233	Covered	T1,T10,T20
TerminalSt	249	Covered	T1,T10,T20
TimeoutSt	159	Covered	T2,T15,T13

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T8,T9
IdleSt->Phase0St	152	Covered	T1,T10,T20
IdleSt->TimeoutSt	159	Covered	T2,T15,T13
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T39,T28,T29
Phase0St->Phase1St	198	Covered	T1,T10,T20
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T27,T77,T58
Phase1St->Phase2St	215	Covered	T1,T10,T20
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T32,T41,T97
Phase2St->Phase3St	233	Covered	T1,T10,T20
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T15,T35,T99
Phase3St->TerminalSt	249	Covered	T1,T10,T20
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T10,T15,T13
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T15,T16
TimeoutSt->Phase0St	172	Covered	T13,T27,T32

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T10,T20
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T15,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T13,T27,T32
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T15,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T15,T16
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T29,T94,T95
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T10,T20
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T10,T20,T15
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T27,T58,T96
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T10,T20
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T10,T20,T15
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T32,T97,T98
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T10,T20
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T10,T20,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T15,T35,T99
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T10,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T10,T20,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T15,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T10,T20
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	536682127	294	0	0
CheckAccumTrig0_A	536682127	757	0	0
CheckAccumTrig1_A	536682127	45	0	0
CheckClr_A	536682127	366	0	0
CheckEn_A	536485196	228968521	0	0
CheckPhase0_A	536682127	832	0	0
CheckPhase1_A	536682127	807	0	0
CheckPhase2_A	536682127	791	0	0
CheckPhase3_A	536682127	773	0	0
CheckTimeout0_A	536682127	587	0	0
CheckTimeoutSt1_A	536682127	73291	0	0
CheckTimeoutSt2_A	536682127	485	0	0
CheckTimeoutStTrig_A	536682127	53	0	0
ErrorStAllEscAsserted_A	536682127	1317	0	0
ErrorStIsTerminal_A	536682127	1077	0	0
EscStateOut_A	536483884	536415576	0	0
u_state_regs_A	536682127	536511140	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	294	0	0
T5	54634	21	0	0
T6	66911	0	0	0
T7	14728	0	0	0
T8	41275	67	0	0
T9	0	77	0	0
T12	6904	0	0	0
T14	2924	0	0	0
T16	19328	0	0	0
T25	47484	0	0	0
T26	44861	0	0	0
T42	0	96	0	0
T43	0	33	0	0
T44	34155	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	757	0	0
T1	1832	1	0	0
T2	4638	0	0	0
T3	1737	0	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T10	16916	1	0	0
T11	3660	0	0	0
T12	0	1	0	0
T13	16089	1	0	0
T15	25445	4	0	0
T16	0	2	0	0
T20	15700	1	0	0
T25	0	2	0	0
T26	0	1	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	45	0	0
T17	248991	0	0	0
T27	41094	1	0	0
T29	0	1	0	0
T32	21848	1	0	0
T36	79607	0	0	0
T37	35823	0	0	0
T42	43652	0	0	0
T46	7013	0	0	0
T47	32265	0	0	0
T48	27485	0	0	0
T52	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T71	43325	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	366	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T10	16916	1	0	0
T11	3660	0	0	0
T12	6904	1	0	0
T13	16089	1	0	0
T15	25445	3	0	0
T16	19328	2	0	0
T20	15700	0	0	0
T25	0	1	0	0
T27	0	7	0	0
T32	0	2	0	0
T35	0	1	0	0
T72	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536485196	228968521	0	0
T1	1832	998	0	0
T2	4638	2046	0	0
T3	1737	811	0	0
T4	14715	2228	0	0
T5	869	774	0	0
T10	16916	9508	0	0
T11	3660	582	0	0
T13	16089	9180	0	0
T15	25445	582	0	0
T20	15700	1933	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	832	0	0
T1	1832	1	0	0
T2	4638	0	0	0
T3	1737	0	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T10	16916	1	0	0
T11	3660	0	0	0
T12	0	1	0	0
T13	16089	2	0	0
T15	25445	4	0	0
T16	0	2	0	0
T20	15700	1	0	0
T25	0	2	0	0
T26	0	1	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	807	0	0
T1	1832	1	0	0
T2	4638	0	0	0
T3	1737	0	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T10	16916	1	0	0
T11	3660	0	0	0
T12	0	1	0	0
T13	16089	2	0	0
T15	25445	4	0	0
T16	0	2	0	0
T20	15700	1	0	0
T25	0	2	0	0
T26	0	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	791	0	0
T1	1832	1	0	0
T2	4638	0	0	0
T3	1737	0	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T10	16916	1	0	0
T11	3660	0	0	0
T12	0	1	0	0
T13	16089	2	0	0
T15	25445	4	0	0
T16	0	2	0	0
T20	15700	1	0	0
T25	0	2	0	0
T26	0	1	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	773	0	0
T1	1832	1	0	0
T2	4638	0	0	0
T3	1737	0	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T10	16916	1	0	0
T11	3660	0	0	0
T12	0	1	0	0
T13	16089	2	0	0
T15	25445	3	0	0
T16	0	2	0	0
T20	15700	1	0	0
T25	0	2	0	0
T26	0	1	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	587	0	0
T2	4638	1	0	0
T3	1737	0	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T10	16916	0	0	0
T11	3660	0	0	0
T12	6904	0	0	0
T13	16089	1	0	0
T15	25445	1	0	0
T16	0	3	0	0
T20	15700	0	0	0
T27	0	1	0	0
T32	0	1	0	0
T38	0	3	0	0
T44	0	2	0	0
T68	0	11	0	0
T71	0	7	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	73291	0	0
T2	4638	122	0	0
T3	1737	0	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T10	16916	0	0	0
T11	3660	0	0	0
T12	6904	0	0	0
T13	16089	221	0	0
T15	25445	179	0	0
T16	0	131	0	0
T20	15700	0	0	0
T27	0	9	0	0
T37	0	693	0	0
T38	0	359	0	0
T44	0	151	0	0
T68	0	2351	0	0
T71	0	575	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	485	0	0
T2	4638	1	0	0
T3	1737	0	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T10	16916	0	0	0
T11	3660	0	0	0
T12	6904	0	0	0
T13	16089	0	0	0
T15	25445	1	0	0
T16	0	3	0	0
T20	15700	0	0	0
T37	0	8	0	0
T38	0	3	0	0
T41	0	7	0	0
T44	0	2	0	0
T52	0	1	0	0
T68	0	11	0	0
T71	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	53	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T7	14728	0	0	0
T8	41275	0	0	0
T12	6904	0	0	0
T13	16089	1	0	0
T14	2924	0	0	0
T16	19328	0	0	0
T25	47484	0	0	0
T26	44861	0	0	0
T31	0	1	0	0
T41	0	2	0	0
T53	0	1	0	0
T61	0	1	0	0
T77	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0
T87	0	1	0	0
T93	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	1317	0	0
T5	54634	151	0	0
T6	66911	0	0	0
T7	14728	0	0	0
T8	41275	316	0	0
T9	0	319	0	0
T12	6904	0	0	0
T14	2924	0	0	0
T16	19328	0	0	0
T25	47484	0	0	0
T26	44861	0	0	0
T42	0	367	0	0
T43	0	164	0	0
T44	34155	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	1077	0	0
T5	54634	121	0	0
T6	66911	0	0	0
T7	14728	0	0	0
T8	41275	256	0	0
T9	0	259	0	0
T12	6904	0	0	0
T14	2924	0	0	0
T16	19328	0	0	0
T25	47484	0	0	0
T26	44861	0	0	0
T42	0	307	0	0
T43	0	134	0	0
T44	34155	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536483884	536415576	0	0
T1	1832	1738	0	0
T2	4638	4562	0	0
T3	1737	1659	0	0
T4	14715	14541	0	0
T5	386	292	0	0
T10	16916	16835	0	0
T11	3660	3601	0	0
T13	16089	16008	0	0
T15	25445	25358	0	0
T20	15700	15639	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	536511140	0	0
T1	1832	1738	0	0
T2	4638	4562	0	0
T3	1737	1659	0	0
T4	14715	14541	0	0
T5	54634	41677	0	0
T10	16916	16835	0	0
T11	3660	3601	0	0
T13	16089	16008	0	0
T15	25445	25358	0	0
T20	15700	15639	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T10 T4 T13 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T10 T4 T13 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T10 T4 T13 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T26 T68 T70 
159        1/1                    state_d = TimeoutSt;
           Tests:       T26 T68 T70 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T26 T68 T70 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T26 T68 T70 
172        1/1                    state_d    = Phase0St;
           Tests:       T26 T36 T37 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T26 T36 T37 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T26 T36 T37 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T26 T36 T37 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T26 T68 T70 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T26 T68 T70 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T68 T70 T36 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T68 T70 T36 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T13 T14 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T10 T13 T14 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T10 T13 T14 
190        1/1                  esc_state_o = Phase0;
           Tests:       T10 T13 T14 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T10 T13 T14 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T10 T13 T14 
194        1/1                    state_d = IdleSt;
           Tests:       T100 T101 T102 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T100 T101 T102 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T100 T101 T102 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T13 T14 
198        1/1                    state_d = Phase1St;
           Tests:       T10 T13 T14 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T13 T14 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T13 T14 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T13 T14 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T10 T13 T14 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T10 T13 T14 
207        1/1                  esc_state_o = Phase1;
           Tests:       T10 T13 T14 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T10 T13 T14 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T10 T13 T14 
211        1/1                    state_d = IdleSt;
           Tests:       T102 T103 T104 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T102 T103 T104 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T102 T103 T104 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T13 T14 
215        1/1                    state_d = Phase2St;
           Tests:       T10 T13 T14 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T13 T14 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T13 T14 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T13 T14 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T10 T13 T14 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T10 T13 T14 
224        1/1                  esc_state_o = Phase2;
           Tests:       T10 T13 T14 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T10 T13 T14 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T10 T13 T14 
229        1/1                    state_d = IdleSt;
           Tests:       T34 T61 T105 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T61 T105 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T34 T61 T105 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T13 T14 
233        1/1                    state_d = Phase3St;
           Tests:       T10 T13 T14 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T13 T14 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T13 T14 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T10 T13 T14 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T10 T13 T14 
241        1/1                  esc_state_o = Phase3;
           Tests:       T10 T13 T14 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T10 T13 T14 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T10 T13 T14 
245        1/1                    state_d = IdleSt;
           Tests:       T62 T106 T105 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T62 T106 T105 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T62 T106 T105 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T13 T14 
249        1/1                    state_d = TerminalSt;
           Tests:       T10 T13 T14 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T13 T14 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T10 T13 T14 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T10 T13 T14 
259        1/1                  esc_state_o = Terminal;
           Tests:       T10 T13 T14 
260        1/1                  if (clr_i) begin
           Tests:       T10 T13 T14 
261        1/1                    state_d = IdleSt;
           Tests:       T10 T13 T38 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T5 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T5 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T5 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T5 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T10,T4,T13
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T26
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T4,T13

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T10,T4,T13

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T15,T13
1	0	1	Covered	T14,T26,T17
1	1	0	Covered	T13,T38,T70
1	1	1	Covered	T26,T68,T70

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T68,T70
0	1	Covered	T36,T37,T40
1	0	Covered	T26,T36,T53

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T26,T68,T70
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T26,T36,T53

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T68,T70
1	0	Not Covered
1	1	Covered	T36,T37,T40

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T13,T26
1	Covered	T14,T47,T48

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T13,T14
1	Covered	T26,T38,T37

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T10,T13,T14
1	Covered	T13,T45,T46

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T13,T14,T26
1	Covered	T10,T13,T38

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T13,T14,T26

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T10,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T10,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T14,T38,T45

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T10,T13,T14
Phase1St	198	Covered	T10,T13,T14
Phase2St	215	Covered	T10,T13,T14
Phase3St	233	Covered	T10,T13,T14
TerminalSt	249	Covered	T10,T13,T14
TimeoutSt	159	Covered	T26,T68,T70

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T8,T9
IdleSt->Phase0St	152	Covered	T10,T13,T14
IdleSt->TimeoutSt	159	Covered	T26,T68,T70
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T77,T107,T100
Phase0St->Phase1St	198	Covered	T10,T13,T14
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T40,T77,T93
Phase1St->Phase2St	215	Covered	T10,T13,T14
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T41,T34,T61
Phase2St->Phase3St	233	Covered	T10,T13,T14
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T62,T106,T105
Phase3St->TerminalSt	249	Covered	T10,T13,T14
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T10,T13,T38
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T68,T70,T36
TimeoutSt->Phase0St	172	Covered	T26,T36,T37

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T4,T13
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T26,T68,T70
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T26,T36,T37
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T26,T68,T70
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T68,T70,T36
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T100,T101,T102
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T10,T13,T14
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T10,T13,T26
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T102,T103,T104
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T10,T13,T14
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T10,T13,T26
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T34,T61,T105
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T10,T13,T14
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T10,T13,T26
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T62,T106,T105
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T10,T13,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T10,T13,T26
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T13,T38
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T10,T13,T14
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	536682127	234	0	0
CheckAccumTrig0_A	536682127	423	0	0
CheckAccumTrig1_A	536682127	26	0	0
CheckClr_A	536682127	179	0	0
CheckEn_A	536485196	261059078	0	0
CheckPhase0_A	536682127	497	0	0
CheckPhase1_A	536682127	482	0	0
CheckPhase2_A	536682127	474	0	0
CheckPhase3_A	536682127	468	0	0
CheckTimeout0_A	536682127	510	0	0
CheckTimeoutSt1_A	536682127	64694	0	0
CheckTimeoutSt2_A	536682127	424	0	0
CheckTimeoutStTrig_A	536682127	58	0	0
ErrorStAllEscAsserted_A	536682127	1323	0	0
ErrorStIsTerminal_A	536682127	1083	0	0
EscStateOut_A	536483884	536415576	0	0
u_state_regs_A	536682127	536511140	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	234	0	0
T5	54634	28	0	0
T6	66911	0	0	0
T7	14728	0	0	0
T8	41275	67	0	0
T9	0	56	0	0
T12	6904	0	0	0
T14	2924	0	0	0
T16	19328	0	0	0
T25	47484	0	0	0
T26	44861	0	0	0
T42	0	60	0	0
T43	0	23	0	0
T44	34155	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	423	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T10	16916	1	0	0
T11	3660	0	0	0
T12	6904	0	0	0
T13	16089	3	0	0
T14	0	1	0	0
T15	25445	0	0	0
T16	19328	0	0	0
T20	15700	0	0	0
T38	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	26	0	0
T7	14728	0	0	0
T9	40062	0	0	0
T26	44861	1	0	0
T36	0	1	0	0
T38	81327	0	0	0
T44	34155	0	0	0
T45	14606	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T57	0	1	0	0
T60	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	8696	0	0	0
T68	109253	0	0	0
T69	4032	0	0	0
T70	96972	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	179	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T10	16916	1	0	0
T11	3660	0	0	0
T12	6904	0	0	0
T13	16089	2	0	0
T15	25445	0	0	0
T16	19328	0	0	0
T20	15700	0	0	0
T36	0	3	0	0
T38	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T54	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536485196	261059078	0	0
T1	1832	1002	0	0
T2	4638	2065	0	0
T3	1737	815	0	0
T4	14715	2239	0	0
T5	869	774	0	0
T10	16916	3959	0	0
T11	3660	3600	0	0
T13	16089	1803	0	0
T15	25445	20616	0	0
T20	15700	15638	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	497	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T10	16916	1	0	0
T11	3660	0	0	0
T12	6904	0	0	0
T13	16089	3	0	0
T14	0	1	0	0
T15	25445	0	0	0
T16	19328	0	0	0
T20	15700	0	0	0
T26	0	1	0	0
T36	0	4	0	0
T37	0	1	0	0
T38	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	482	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T10	16916	1	0	0
T11	3660	0	0	0
T12	6904	0	0	0
T13	16089	3	0	0
T14	0	1	0	0
T15	25445	0	0	0
T16	19328	0	0	0
T20	15700	0	0	0
T26	0	1	0	0
T36	0	4	0	0
T37	0	1	0	0
T38	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	474	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T10	16916	1	0	0
T11	3660	0	0	0
T12	6904	0	0	0
T13	16089	3	0	0
T14	0	1	0	0
T15	25445	0	0	0
T16	19328	0	0	0
T20	15700	0	0	0
T26	0	1	0	0
T36	0	4	0	0
T37	0	1	0	0
T38	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	468	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T10	16916	1	0	0
T11	3660	0	0	0
T12	6904	0	0	0
T13	16089	3	0	0
T14	0	1	0	0
T15	25445	0	0	0
T16	19328	0	0	0
T20	15700	0	0	0
T26	0	1	0	0
T36	0	4	0	0
T37	0	1	0	0
T38	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	510	0	0
T7	14728	0	0	0
T9	40062	0	0	0
T26	44861	1	0	0
T36	0	7	0	0
T37	0	1	0	0
T38	81327	0	0	0
T41	0	1	0	0
T44	34155	0	0	0
T45	14606	0	0	0
T48	0	1	0	0
T50	0	1	0	0
T67	8696	0	0	0
T68	109253	7	0	0
T69	4032	0	0	0
T70	96972	1	0	0
T71	0	7	0	0
T78	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	64694	0	0
T7	14728	0	0	0
T9	40062	0	0	0
T26	44861	6	0	0
T36	0	3225	0	0
T37	0	12	0	0
T38	81327	0	0	0
T41	0	190	0	0
T44	34155	0	0	0
T45	14606	0	0	0
T48	0	48	0	0
T50	0	117	0	0
T67	8696	0	0	0
T68	109253	1482	0	0
T69	4032	0	0	0
T70	96972	128	0	0
T71	0	656	0	0
T78	0	299	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	424	0	0
T9	40062	0	0	0
T27	41094	0	0	0
T36	79607	3	0	0
T41	0	1	0	0
T42	43652	0	0	0
T45	14606	0	0	0
T46	7013	0	0	0
T48	0	1	0	0
T50	0	1	0	0
T68	109253	7	0	0
T69	4032	0	0	0
T70	96972	1	0	0
T71	43325	7	0	0
T74	0	1	0	0
T78	0	2	0	0
T83	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	58	0	0
T17	248991	0	0	0
T31	0	1	0	0
T32	21848	0	0	0
T36	79607	3	0	0
T37	35823	1	0	0
T40	0	1	0	0
T42	43652	0	0	0
T47	32265	0	0	0
T48	27485	0	0	0
T49	3442	0	0	0
T71	43325	0	0	0
T72	29350	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T90	0	1	0	0
T92	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	1323	0	0
T5	54634	153	0	0
T6	66911	0	0	0
T7	14728	0	0	0
T8	41275	358	0	0
T9	0	333	0	0
T12	6904	0	0	0
T14	2924	0	0	0
T16	19328	0	0	0
T25	47484	0	0	0
T26	44861	0	0	0
T42	0	339	0	0
T43	0	140	0	0
T44	34155	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	1083	0	0
T5	54634	123	0	0
T6	66911	0	0	0
T7	14728	0	0	0
T8	41275	298	0	0
T9	0	273	0	0
T12	6904	0	0	0
T14	2924	0	0	0
T16	19328	0	0	0
T25	47484	0	0	0
T26	44861	0	0	0
T42	0	279	0	0
T43	0	110	0	0
T44	34155	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536483884	536415576	0	0
T1	1832	1738	0	0
T2	4638	4562	0	0
T3	1737	1659	0	0
T4	14715	14541	0	0
T5	386	292	0	0
T10	16916	16835	0	0
T11	3660	3601	0	0
T13	16089	16008	0	0
T15	25445	25358	0	0
T20	15700	15639	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	536511140	0	0
T1	1832	1738	0	0
T2	4638	4562	0	0
T3	1737	1659	0	0
T4	14715	14541	0	0
T5	54634	41677	0	0
T10	16916	16835	0	0
T11	3660	3601	0	0
T13	16089	16008	0	0
T15	25445	25358	0	0
T20	15700	15639	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T10 T13 T12 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T10 T13 T12 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T10 T13 T12 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T26 T68 T36 
159        1/1                    state_d = TimeoutSt;
           Tests:       T26 T68 T36 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T26 T68 T36 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T26 T68 T36 
172        1/1                    state_d    = Phase0St;
           Tests:       T26 T79 T41 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T26 T79 T41 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T26 T79 T41 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T26 T79 T41 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T26 T68 T36 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T26 T68 T36 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T68 T36 T71 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T68 T36 T71 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T13 T12 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T10 T13 T12 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T10 T13 T12 
190        1/1                  esc_state_o = Phase0;
           Tests:       T10 T13 T12 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T10 T13 T12 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T10 T13 T12 
194        1/1                    state_d = IdleSt;
           Tests:       T28 T30 T31 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T28 T30 T31 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T28 T30 T31 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T13 T12 
198        1/1                    state_d = Phase1St;
           Tests:       T10 T13 T12 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T13 T12 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T13 T12 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T13 T12 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T10 T13 T12 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T10 T13 T12 
207        1/1                  esc_state_o = Phase1;
           Tests:       T10 T13 T12 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T10 T13 T12 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T10 T13 T12 
211        1/1                    state_d = IdleSt;
           Tests:       T29 T31 T108 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T29 T31 T108 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T29 T31 T108 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T13 T12 
215        1/1                    state_d = Phase2St;
           Tests:       T10 T13 T12 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T13 T12 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T13 T12 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T13 T12 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T10 T13 T12 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T10 T13 T12 
224        1/1                  esc_state_o = Phase2;
           Tests:       T10 T13 T12 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T10 T13 T12 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T10 T13 T12 
229        1/1                    state_d = IdleSt;
           Tests:       T33 T109 T110 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T33 T109 T110 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T33 T109 T110 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T13 T12 
233        1/1                    state_d = Phase3St;
           Tests:       T10 T13 T12 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T13 T12 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T10 T13 T12 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T10 T13 T12 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T10 T13 T12 
241        1/1                  esc_state_o = Phase3;
           Tests:       T10 T13 T12 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T10 T13 T12 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T10 T13 T12 
245        1/1                    state_d = IdleSt;
           Tests:       T28 T30 T111 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T28 T30 T111 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T28 T30 T111 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T10 T13 T12 
249        1/1                    state_d = TerminalSt;
           Tests:       T10 T13 T12 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T13 T12 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T10 T13 T12 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T10 T13 T12 
259        1/1                  esc_state_o = Terminal;
           Tests:       T10 T13 T12 
260        1/1                  if (clr_i) begin
           Tests:       T10 T13 T12 
261        1/1                    state_d = IdleSt;
           Tests:       T10 T13 T26 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T5 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T5 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T5 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T5 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T10,T13,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T13,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T10
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T10,T13,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T16,T26
1	0	1	Covered	T112,T113,T114
1	1	0	Covered	T13,T26,T38
1	1	1	Covered	T26,T68,T36

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T26,T68,T36
0	1	Covered	T79,T41,T28
1	0	Covered	T26,T55,T31

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T26,T68,T36
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T26,T55,T31

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T68,T36
1	0	Not Covered
1	1	Covered	T79,T41,T28

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T26,T38,T45
1	Covered	T10,T13,T12

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T13,T12
1	Covered	T26,T38,T28

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T10,T13,T12
1	Covered	T45,T47,T48

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T10,T13,T12
1	Covered	T26,T46,T36

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T13,T26,T38

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T10,T13,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T10,T13,T26

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T10,T26,T38

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T10,T13,T12
Phase1St	198	Covered	T10,T13,T12
Phase2St	215	Covered	T10,T13,T12
Phase3St	233	Covered	T10,T13,T12
TerminalSt	249	Covered	T10,T13,T12
TimeoutSt	159	Covered	T26,T68,T36

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T8,T9
IdleSt->Phase0St	152	Covered	T10,T13,T12
IdleSt->TimeoutSt	159	Covered	T26,T68,T36
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T28,T29,T30
Phase0St->Phase1St	198	Covered	T10,T13,T12
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T40,T29,T31
Phase1St->Phase2St	215	Covered	T10,T13,T12
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T33,T61,T109
Phase2St->Phase3St	233	Covered	T10,T13,T12
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T28,T30,T111
Phase3St->TerminalSt	249	Covered	T10,T13,T12
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T10,T13,T26
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T68,T36,T71
TimeoutSt->Phase0St	172	Covered	T26,T79,T41

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T13,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T26,T68,T36
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T26,T79,T41
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T26,T68,T36
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T68,T36,T71
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T30,T31
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T10,T13,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T10,T13,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T29,T31,T108
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T10,T13,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T10,T13,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T33,T109,T110
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T10,T13,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T10,T13,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T28,T30,T111
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T10,T13,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T10,T13,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T13,T26
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T10,T13,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	536682127	232	0	0
CheckAccumTrig0_A	536682127	517	0	0
CheckAccumTrig1_A	536682127	16	0	0
CheckClr_A	536682127	259	0	0
CheckEn_A	536485196	227986287	0	0
CheckPhase0_A	536682127	576	0	0
CheckPhase1_A	536682127	562	0	0
CheckPhase2_A	536682127	555	0	0
CheckPhase3_A	536682127	544	0	0
CheckTimeout0_A	536682127	660	0	0
CheckTimeoutSt1_A	536682127	76169	0	0
CheckTimeoutSt2_A	536682127	575	0	0
CheckTimeoutStTrig_A	536682127	66	0	0
ErrorStAllEscAsserted_A	536682127	1276	0	0
ErrorStIsTerminal_A	536682127	1036	0	0
EscStateOut_A	536483884	536415576	0	0
u_state_regs_A	536682127	536511140	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	232	0	0
T5	54634	13	0	0
T6	66911	0	0	0
T7	14728	0	0	0
T8	41275	81	0	0
T9	0	61	0	0
T12	6904	0	0	0
T14	2924	0	0	0
T16	19328	0	0	0
T25	47484	0	0	0
T26	44861	0	0	0
T42	0	44	0	0
T43	0	33	0	0
T44	34155	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	517	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T10	16916	1	0	0
T11	3660	0	0	0
T12	6904	1	0	0
T13	16089	1	0	0
T15	25445	0	0	0
T16	19328	0	0	0
T20	15700	0	0	0
T26	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	16	0	0
T7	14728	0	0	0
T9	40062	0	0	0
T26	44861	1	0	0
T31	0	2	0	0
T38	81327	0	0	0
T44	34155	0	0	0
T45	14606	0	0	0
T55	0	1	0	0
T61	0	1	0	0
T67	8696	0	0	0
T68	109253	0	0	0
T69	4032	0	0	0
T70	96972	0	0	0
T95	0	1	0	0
T109	0	3	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0
T118	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	259	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T10	16916	1	0	0
T11	3660	0	0	0
T12	6904	0	0	0
T13	16089	1	0	0
T15	25445	0	0	0
T16	19328	0	0	0
T20	15700	0	0	0
T26	0	1	0	0
T33	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T73	0	5	0	0
T74	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536485196	227986287	0	0
T1	1832	1006	0	0
T2	4638	4561	0	0
T3	1737	819	0	0
T4	14715	2245	0	0
T5	869	774	0	0
T10	16916	9507	0	0
T11	3660	3600	0	0
T13	16089	7860	0	0
T15	25445	25357	0	0
T20	15700	15638	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	576	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T10	16916	1	0	0
T11	3660	0	0	0
T12	6904	1	0	0
T13	16089	1	0	0
T15	25445	0	0	0
T16	19328	0	0	0
T20	15700	0	0	0
T26	0	2	0	0
T36	0	1	0	0
T38	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	562	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T10	16916	1	0	0
T11	3660	0	0	0
T12	6904	1	0	0
T13	16089	1	0	0
T15	25445	0	0	0
T16	19328	0	0	0
T20	15700	0	0	0
T26	0	2	0	0
T36	0	1	0	0
T38	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	555	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T10	16916	1	0	0
T11	3660	0	0	0
T12	6904	1	0	0
T13	16089	1	0	0
T15	25445	0	0	0
T16	19328	0	0	0
T20	15700	0	0	0
T26	0	2	0	0
T36	0	1	0	0
T38	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	544	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T10	16916	1	0	0
T11	3660	0	0	0
T12	6904	1	0	0
T13	16089	1	0	0
T15	25445	0	0	0
T16	19328	0	0	0
T20	15700	0	0	0
T26	0	2	0	0
T36	0	1	0	0
T38	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	660	0	0
T7	14728	0	0	0
T9	40062	0	0	0
T26	44861	1	0	0
T36	0	1	0	0
T38	81327	0	0	0
T41	0	1	0	0
T44	34155	0	0	0
T45	14606	0	0	0
T67	8696	0	0	0
T68	109253	7	0	0
T69	4032	0	0	0
T70	96972	0	0	0
T71	0	1	0	0
T73	0	1	0	0
T79	0	1	0	0
T80	0	9	0	0
T81	0	6	0	0
T82	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	76169	0	0
T7	14728	0	0	0
T9	40062	0	0	0
T26	44861	12	0	0
T36	0	29	0	0
T38	81327	0	0	0
T41	0	48	0	0
T44	34155	0	0	0
T45	14606	0	0	0
T67	8696	0	0	0
T68	109253	1444	0	0
T69	4032	0	0	0
T70	96972	0	0	0
T71	0	101	0	0
T73	0	253	0	0
T79	0	933	0	0
T80	0	1644	0	0
T81	0	815	0	0
T82	0	111	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	575	0	0
T9	40062	0	0	0
T27	41094	0	0	0
T28	0	1	0	0
T36	79607	1	0	0
T42	43652	0	0	0
T45	14606	0	0	0
T46	7013	0	0	0
T68	109253	7	0	0
T69	4032	0	0	0
T70	96972	0	0	0
T71	43325	1	0	0
T73	0	1	0	0
T80	0	9	0	0
T81	0	6	0	0
T82	0	1	0	0
T83	0	1	0	0
T119	0	12	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	66	0	0
T19	571652	0	0	0
T24	44739	0	0	0
T28	0	1	0	0
T31	0	1	0	0
T40	0	2	0	0
T41	330660	1	0	0
T77	0	1	0	0
T79	43777	1	0	0
T80	107966	0	0	0
T86	0	2	0	0
T89	0	1	0	0
T91	0	1	0	0
T114	4716	0	0	0
T120	0	1	0	0
T121	343556	0	0	0
T122	107245	0	0	0
T123	143872	0	0	0
T124	451722	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	1276	0	0
T5	54634	141	0	0
T6	66911	0	0	0
T7	14728	0	0	0
T8	41275	324	0	0
T9	0	338	0	0
T12	6904	0	0	0
T14	2924	0	0	0
T16	19328	0	0	0
T25	47484	0	0	0
T26	44861	0	0	0
T42	0	300	0	0
T43	0	173	0	0
T44	34155	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	1036	0	0
T5	54634	111	0	0
T6	66911	0	0	0
T7	14728	0	0	0
T8	41275	264	0	0
T9	0	278	0	0
T12	6904	0	0	0
T14	2924	0	0	0
T16	19328	0	0	0
T25	47484	0	0	0
T26	44861	0	0	0
T42	0	240	0	0
T43	0	143	0	0
T44	34155	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536483884	536415576	0	0
T1	1832	1738	0	0
T2	4638	4562	0	0
T3	1737	1659	0	0
T4	14715	14541	0	0
T5	386	292	0	0
T10	16916	16835	0	0
T11	3660	3601	0	0
T13	16089	16008	0	0
T15	25445	25358	0	0
T20	15700	15639	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	536511140	0	0
T1	1832	1738	0	0
T2	4638	4562	0	0
T3	1737	1659	0	0
T4	14715	14541	0	0
T5	54634	41677	0	0
T10	16916	16835	0	0
T11	3660	3601	0	0
T13	16089	16008	0	0
T15	25445	25358	0	0
T20	15700	15639	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T3 T10 T13 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T3 T10 T13 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T3 T10 T13 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T13 T68 T36 
159        1/1                    state_d = TimeoutSt;
           Tests:       T13 T68 T36 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T13 T68 T36 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T13 T68 T36 
172        1/1                    state_d    = Phase0St;
           Tests:       T13 T36 T79 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T13 T36 T79 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T13 T36 T79 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T13 T36 T79 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T13 T68 T36 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T13 T68 T36 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T68 T36 T37 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T68 T36 T37 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T13 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T3 T10 T13 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T3 T10 T13 
190        1/1                  esc_state_o = Phase0;
           Tests:       T3 T10 T13 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T3 T10 T13 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T3 T10 T13 
194        1/1                    state_d = IdleSt;
           Tests:       T125 T126 T127 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T125 T126 T127 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T125 T126 T127 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T13 
198        1/1                    state_d = Phase1St;
           Tests:       T3 T10 T13 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T13 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T10 T13 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T13 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T3 T10 T13 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T3 T10 T13 
207        1/1                  esc_state_o = Phase1;
           Tests:       T3 T10 T13 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T3 T10 T13 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T3 T10 T13 
211        1/1                    state_d = IdleSt;
           Tests:       T128 T129 T105 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T128 T129 T105 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T128 T129 T105 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T13 
215        1/1                    state_d = Phase2St;
           Tests:       T3 T10 T13 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T13 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T10 T13 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T13 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T3 T10 T13 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T3 T10 T13 
224        1/1                  esc_state_o = Phase2;
           Tests:       T3 T10 T13 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T3 T10 T13 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T3 T10 T13 
229        1/1                    state_d = IdleSt;
           Tests:       T130 T131 T132 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T130 T131 T132 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T130 T131 T132 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T13 
233        1/1                    state_d = Phase3St;
           Tests:       T3 T10 T13 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T13 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T13 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T3 T10 T13 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T3 T10 T13 
241        1/1                  esc_state_o = Phase3;
           Tests:       T3 T10 T13 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T3 T10 T13 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T3 T10 T13 
245        1/1                    state_d = IdleSt;
           Tests:       T29 T77 T62 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T29 T77 T62 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T29 T77 T62 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T13 
249        1/1                    state_d = TerminalSt;
           Tests:       T3 T10 T13 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T13 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T3 T10 T13 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T3 T10 T13 
259        1/1                  esc_state_o = Terminal;
           Tests:       T3 T10 T13 
260        1/1                  if (clr_i) begin
           Tests:       T3 T10 T13 
261        1/1                    state_d = IdleSt;
           Tests:       T10 T13 T36 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T5 T8 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T5 T8 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T5 T8 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T5 T8 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T3,T10,T13
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T26
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T10,T13

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T10
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T13

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T15,T13,T16
1	0	1	Covered	T3,T10,T112
1	1	0	Covered	T38,T68,T70
1	1	1	Covered	T13,T68,T36

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T13,T68,T36
0	1	Covered	T13,T36,T79
1	0	Covered	T41,T133,T54

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T13,T68,T36
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T41,T133,T54

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T68,T36
1	0	Not Covered
1	1	Covered	T13,T36,T79

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T13,T36
1	Covered	T3,T10,T26

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T13
1	Covered	T36,T50,T41

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T26
1	Covered	T13,T36,T50

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T13
1	Covered	T10,T47,T48

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T3,T10,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T3,T10,T26

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T3,T13,T26

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T3,T10,T13

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T10,T13
Phase1St	198	Covered	T3,T10,T13
Phase2St	215	Covered	T3,T10,T13
Phase3St	233	Covered	T3,T10,T13
TerminalSt	249	Covered	T3,T10,T13
TimeoutSt	159	Covered	T13,T68,T36

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T8,T9
IdleSt->Phase0St	152	Covered	T3,T10,T13
IdleSt->TimeoutSt	159	Covered	T13,T68,T36
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T54,T77,T93
Phase0St->Phase1St	198	Covered	T3,T10,T13
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T40,T29,T77
Phase1St->Phase2St	215	Covered	T3,T10,T13
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T130,T131,T132
Phase2St->Phase3St	233	Covered	T3,T10,T13
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T29,T77,T62
Phase3St->TerminalSt	249	Covered	T3,T10,T13
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T10,T13,T36
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T68,T36,T37
TimeoutSt->Phase0St	172	Covered	T13,T36,T79

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T13
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T68,T36
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T13,T36,T79
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T13,T68,T36
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T68,T36,T37
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T125,T126,T127
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T10,T13
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T10,T13,T26
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T128,T129,T105
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T10,T13
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T10,T13,T26
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T130,T131,T132
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T10,T13
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T10,T13,T26
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T77,T62
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T10,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T10,T13,T26
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T13,T36
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T10,T13
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	536682127	229	0	0
CheckAccumTrig0_A	536682127	462	0	0
CheckAccumTrig1_A	536682127	23	0	0
CheckClr_A	536682127	193	0	0
CheckEn_A	536485196	223143075	0	0
CheckPhase0_A	536682127	523	0	0
CheckPhase1_A	536682127	512	0	0
CheckPhase2_A	536682127	507	0	0
CheckPhase3_A	536682127	498	0	0
CheckTimeout0_A	536682127	471	0	0
CheckTimeoutSt1_A	536682127	60267	0	0
CheckTimeoutSt2_A	536682127	396	0	0
CheckTimeoutStTrig_A	536682127	51	0	0
ErrorStAllEscAsserted_A	536682127	1228	0	0
ErrorStIsTerminal_A	536682127	988	0	0
EscStateOut_A	536483884	536415576	0	0
u_state_regs_A	536682127	536511140	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	229	0	0
T5	54634	26	0	0
T6	66911	0	0	0
T7	14728	0	0	0
T8	41275	66	0	0
T9	0	64	0	0
T12	6904	0	0	0
T14	2924	0	0	0
T16	19328	0	0	0
T25	47484	0	0	0
T26	44861	0	0	0
T42	0	49	0	0
T43	0	24	0	0
T44	34155	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	462	0	0
T3	1737	1	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T10	16916	2	0	0
T11	3660	0	0	0
T12	6904	0	0	0
T13	16089	1	0	0
T15	25445	0	0	0
T20	15700	0	0	0
T26	0	1	0	0
T36	0	2	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	23	0	0
T41	330660	1	0	0
T54	0	1	0	0
T57	0	1	0	0
T73	47777	0	0	0
T77	0	1	0	0
T80	107966	0	0	0
T81	46470	0	0	0
T82	5967	0	0	0
T124	451722	0	0	0
T129	0	6	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	31335	0	0	0
T139	91958	0	0	0
T140	2561	0	0	0
T141	10377	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	193	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T10	16916	1	0	0
T11	3660	0	0	0
T12	6904	0	0	0
T13	16089	1	0	0
T15	25445	0	0	0
T16	19328	0	0	0
T20	15700	0	0	0
T36	0	2	0	0
T47	0	1	0	0
T50	0	1	0	0
T54	0	3	0	0
T74	0	1	0	0
T75	0	2	0	0
T76	0	2	0	0
T122	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536485196	223143075	0	0
T1	1832	1010	0	0
T2	4638	4561	0	0
T3	1737	823	0	0
T4	14715	2259	0	0
T5	869	774	0	0
T10	16916	2047	0	0
T11	3660	3600	0	0
T13	16089	4220	0	0
T15	25445	20616	0	0
T20	15700	15638	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	523	0	0
T3	1737	1	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T10	16916	2	0	0
T11	3660	0	0	0
T12	6904	0	0	0
T13	16089	2	0	0
T15	25445	0	0	0
T20	15700	0	0	0
T26	0	1	0	0
T36	0	3	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	512	0	0
T3	1737	1	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T10	16916	2	0	0
T11	3660	0	0	0
T12	6904	0	0	0
T13	16089	2	0	0
T15	25445	0	0	0
T20	15700	0	0	0
T26	0	1	0	0
T36	0	3	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	507	0	0
T3	1737	1	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T10	16916	2	0	0
T11	3660	0	0	0
T12	6904	0	0	0
T13	16089	2	0	0
T15	25445	0	0	0
T20	15700	0	0	0
T26	0	1	0	0
T36	0	3	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	498	0	0
T3	1737	1	0	0
T4	14715	0	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T10	16916	2	0	0
T11	3660	0	0	0
T12	6904	0	0	0
T13	16089	2	0	0
T15	25445	0	0	0
T20	15700	0	0	0
T26	0	1	0	0
T36	0	3	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	471	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T7	14728	0	0	0
T8	41275	0	0	0
T12	6904	0	0	0
T13	16089	1	0	0
T14	2924	0	0	0
T16	19328	0	0	0
T25	47484	0	0	0
T26	44861	0	0	0
T36	0	3	0	0
T37	0	1	0	0
T41	0	2	0	0
T68	0	3	0	0
T79	0	1	0	0
T80	0	1	0	0
T82	0	2	0	0
T83	0	4	0	0
T133	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	60267	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T7	14728	0	0	0
T8	41275	0	0	0
T12	6904	0	0	0
T13	16089	4	0	0
T14	2924	0	0	0
T16	19328	0	0	0
T25	47484	0	0	0
T26	44861	0	0	0
T36	0	2164	0	0
T37	0	117	0	0
T41	0	332	0	0
T68	0	743	0	0
T79	0	350	0	0
T80	0	175	0	0
T82	0	161	0	0
T83	0	672	0	0
T133	0	13	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	396	0	0
T9	40062	0	0	0
T27	41094	0	0	0
T28	0	1	0	0
T36	79607	2	0	0
T37	0	1	0	0
T41	0	1	0	0
T42	43652	0	0	0
T45	14606	0	0	0
T46	7013	0	0	0
T54	0	4	0	0
T68	109253	3	0	0
T69	4032	0	0	0
T70	96972	0	0	0
T71	43325	0	0	0
T80	0	1	0	0
T82	0	2	0	0
T83	0	4	0	0
T142	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	51	0	0
T5	54634	0	0	0
T6	66911	0	0	0
T7	14728	0	0	0
T8	41275	0	0	0
T12	6904	0	0	0
T13	16089	1	0	0
T14	2924	0	0	0
T16	19328	0	0	0
T25	47484	0	0	0
T26	44861	0	0	0
T31	0	1	0	0
T36	0	1	0	0
T40	0	2	0	0
T77	0	1	0	0
T79	0	1	0	0
T87	0	2	0	0
T111	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	1228	0	0
T5	54634	138	0	0
T6	66911	0	0	0
T7	14728	0	0	0
T8	41275	326	0	0
T9	0	327	0	0
T12	6904	0	0	0
T14	2924	0	0	0
T16	19328	0	0	0
T25	47484	0	0	0
T26	44861	0	0	0
T42	0	296	0	0
T43	0	141	0	0
T44	34155	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	988	0	0
T5	54634	108	0	0
T6	66911	0	0	0
T7	14728	0	0	0
T8	41275	266	0	0
T9	0	267	0	0
T12	6904	0	0	0
T14	2924	0	0	0
T16	19328	0	0	0
T25	47484	0	0	0
T26	44861	0	0	0
T42	0	236	0	0
T43	0	111	0	0
T44	34155	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536483884	536415576	0	0
T1	1832	1738	0	0
T2	4638	4562	0	0
T3	1737	1659	0	0
T4	14715	14541	0	0
T5	386	292	0	0
T10	16916	16835	0	0
T11	3660	3601	0	0
T13	16089	16008	0	0
T15	25445	25358	0	0
T20	15700	15639	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	536682127	536511140	0	0
T1	1832	1738	0	0
T2	4638	4562	0	0
T3	1737	1659	0	0
T4	14715	14541	0	0
T5	54634	41677	0	0
T10	16916	16835	0	0
T11	3660	3601	0	0
T13	16089	16008	0	0
T15	25445	25358	0	0
T20	15700	15639	0	0