| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.22 | 99.99 | 98.64 | 97.06 | 100.00 | 100.00 | 99.38 | 99.44 |
| T784 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.781958088 | Oct 12 11:21:12 AM UTC 24 | Oct 12 11:21:27 AM UTC 24 | 2210549289 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_errors.1769299088 | Oct 12 11:21:04 AM UTC 24 | Oct 12 11:21:31 AM UTC 24 | 312308868 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2118100276 | Oct 12 11:20:52 AM UTC 24 | Oct 12 11:21:44 AM UTC 24 | 696606252 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.187090874 | Oct 12 11:18:11 AM UTC 24 | Oct 12 11:21:57 AM UTC 24 | 10612345347 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.1523250015 | Oct 12 11:22:27 AM UTC 24 | Oct 12 11:22:30 AM UTC 24 | 8991017 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3658117537 | Oct 12 11:11:25 AM UTC 24 | Oct 12 11:22:00 AM UTC 24 | 63457274655 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.979623270 | Oct 12 11:21:31 AM UTC 24 | Oct 12 11:22:01 AM UTC 24 | 4334240290 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.3701756881 | Oct 12 11:21:58 AM UTC 24 | Oct 12 11:22:01 AM UTC 24 | 9682555 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.4009534442 | Oct 12 11:21:11 AM UTC 24 | Oct 12 11:22:03 AM UTC 24 | 3812521927 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.2943730987 | Oct 12 11:22:01 AM UTC 24 | Oct 12 11:22:08 AM UTC 24 | 66885732 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1238468420 | Oct 12 11:22:01 AM UTC 24 | Oct 12 11:22:09 AM UTC 24 | 66621808 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.3136422720 | Oct 12 11:22:10 AM UTC 24 | Oct 12 11:22:26 AM UTC 24 | 757506470 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1407969019 | Oct 12 11:22:01 AM UTC 24 | Oct 12 11:22:26 AM UTC 24 | 1097654006 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2441477272 | Oct 12 11:21:07 AM UTC 24 | Oct 12 11:22:27 AM UTC 24 | 1835354465 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2713188931 | Oct 12 11:20:25 AM UTC 24 | Oct 12 11:22:29 AM UTC 24 | 1642022875 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.588520625 | Oct 12 11:22:25 AM UTC 24 | Oct 12 11:22:31 AM UTC 24 | 196933400 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.2458450796 | Oct 12 11:22:31 AM UTC 24 | Oct 12 11:22:34 AM UTC 24 | 18532723 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.2486440023 | Oct 12 11:22:27 AM UTC 24 | Oct 12 11:22:34 AM UTC 24 | 88989145 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.393565918 | Oct 12 11:22:31 AM UTC 24 | Oct 12 11:22:35 AM UTC 24 | 26670218 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.1971578781 | Oct 12 11:22:36 AM UTC 24 | Oct 12 11:22:39 AM UTC 24 | 16210345 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.57248135 | Oct 12 11:22:36 AM UTC 24 | Oct 12 11:22:39 AM UTC 24 | 10282024 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.964524743 | Oct 12 11:22:36 AM UTC 24 | Oct 12 11:22:39 AM UTC 24 | 11657445 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3343472214 | Oct 12 11:22:30 AM UTC 24 | Oct 12 11:22:43 AM UTC 24 | 919596585 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1928237139 | Oct 12 11:22:28 AM UTC 24 | Oct 12 11:22:43 AM UTC 24 | 347648264 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.462038815 | Oct 12 11:22:40 AM UTC 24 | Oct 12 11:22:43 AM UTC 24 | 14086702 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.2828821933 | Oct 12 11:22:40 AM UTC 24 | Oct 12 11:22:44 AM UTC 24 | 12791149 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.3980047554 | Oct 12 11:22:40 AM UTC 24 | Oct 12 11:22:44 AM UTC 24 | 22819680 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3934385478 | Oct 12 11:18:39 AM UTC 24 | Oct 12 11:22:46 AM UTC 24 | 6792264000 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2988196071 | Oct 12 11:20:01 AM UTC 24 | Oct 12 11:22:47 AM UTC 24 | 3998380207 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.2928806971 | Oct 12 11:22:43 AM UTC 24 | Oct 12 11:22:47 AM UTC 24 | 10745591 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.2798487709 | Oct 12 11:22:44 AM UTC 24 | Oct 12 11:22:48 AM UTC 24 | 15198027 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.996541636 | Oct 12 11:22:45 AM UTC 24 | Oct 12 11:22:48 AM UTC 24 | 10321731 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.2168904491 | Oct 12 11:22:45 AM UTC 24 | Oct 12 11:22:48 AM UTC 24 | 11412628 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.1547385749 | Oct 12 11:22:45 AM UTC 24 | Oct 12 11:22:48 AM UTC 24 | 7314711 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.3848332934 | Oct 12 11:22:47 AM UTC 24 | Oct 12 11:22:50 AM UTC 24 | 11300080 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.1737787319 | Oct 12 11:22:48 AM UTC 24 | Oct 12 11:22:51 AM UTC 24 | 7956149 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.3511950176 | Oct 12 11:22:48 AM UTC 24 | Oct 12 11:22:51 AM UTC 24 | 10654304 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.862836904 | Oct 12 11:22:49 AM UTC 24 | Oct 12 11:22:52 AM UTC 24 | 14658847 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.804794172 | Oct 12 11:22:49 AM UTC 24 | Oct 12 11:22:52 AM UTC 24 | 7635300 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.1204695379 | Oct 12 11:22:49 AM UTC 24 | Oct 12 11:22:52 AM UTC 24 | 23336852 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.2965334949 | Oct 12 11:22:49 AM UTC 24 | Oct 12 11:22:52 AM UTC 24 | 39444623 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3441070474 | Oct 12 11:16:39 AM UTC 24 | Oct 12 11:22:52 AM UTC 24 | 8218821564 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.2553269458 | Oct 12 11:22:50 AM UTC 24 | Oct 12 11:22:53 AM UTC 24 | 20985555 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.4256336645 | Oct 12 11:22:51 AM UTC 24 | Oct 12 11:22:54 AM UTC 24 | 7241460 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.2566098560 | Oct 12 11:22:52 AM UTC 24 | Oct 12 11:22:54 AM UTC 24 | 15099168 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.480019192 | Oct 12 11:22:53 AM UTC 24 | Oct 12 11:22:55 AM UTC 24 | 16303041 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.539467986 | Oct 12 11:22:53 AM UTC 24 | Oct 12 11:22:56 AM UTC 24 | 11020745 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.166813847 | Oct 12 11:22:53 AM UTC 24 | Oct 12 11:22:56 AM UTC 24 | 9002692 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.3695479867 | Oct 12 11:22:53 AM UTC 24 | Oct 12 11:22:56 AM UTC 24 | 8077285 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.314763591 | Oct 12 11:19:34 AM UTC 24 | Oct 12 11:22:57 AM UTC 24 | 1539613704 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1984720075 | Oct 12 11:19:02 AM UTC 24 | Oct 12 11:22:57 AM UTC 24 | 8372326475 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.4054818705 | Oct 12 11:22:54 AM UTC 24 | Oct 12 11:22:57 AM UTC 24 | 10486274 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.2360523423 | Oct 12 11:22:56 AM UTC 24 | Oct 12 11:22:59 AM UTC 24 | 49604081 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.967915905 | Oct 12 11:22:55 AM UTC 24 | Oct 12 11:22:59 AM UTC 24 | 48916050 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2277884213 | Oct 12 11:21:45 AM UTC 24 | Oct 12 11:23:01 AM UTC 24 | 898570058 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3627248865 | Oct 12 11:21:28 AM UTC 24 | Oct 12 11:23:22 AM UTC 24 | 1675321894 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3191143921 | Oct 12 11:17:16 AM UTC 24 | Oct 12 11:23:41 AM UTC 24 | 16584626146 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.4110714286 | Oct 12 11:20:44 AM UTC 24 | Oct 12 11:23:45 AM UTC 24 | 8112647642 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.925701285 | Oct 12 11:18:25 AM UTC 24 | Oct 12 11:23:52 AM UTC 24 | 16019271511 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3396669007 | Oct 12 11:17:43 AM UTC 24 | Oct 12 11:23:56 AM UTC 24 | 8987960897 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.4028319558 | Oct 12 11:20:12 AM UTC 24 | Oct 12 11:23:59 AM UTC 24 | 3255857913 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3975995961 | Oct 12 11:21:03 AM UTC 24 | Oct 12 11:27:53 AM UTC 24 | 19163047770 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3990254900 | Oct 12 11:22:10 AM UTC 24 | Oct 12 11:28:12 AM UTC 24 | 17363787350 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2634291870 | Oct 12 11:08:23 AM UTC 24 | Oct 12 11:28:29 AM UTC 24 | 15185450823 ps | ||
| T380 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2291687966 | Oct 12 11:19:31 AM UTC 24 | Oct 12 11:28:43 AM UTC 24 | 27539021794 ps | ||
| T382 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1631809081 | Oct 12 11:19:56 AM UTC 24 | Oct 12 11:28:57 AM UTC 24 | 24975136137 ps | ||
| T378 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.732262868 | Oct 12 11:16:11 AM UTC 24 | Oct 12 11:29:05 AM UTC 24 | 5720134401 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2276731729 | Oct 12 11:17:12 AM UTC 24 | Oct 12 11:29:43 AM UTC 24 | 11816950545 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.805169365 | Oct 12 11:18:24 AM UTC 24 | Oct 12 11:29:45 AM UTC 24 | 16703951186 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3362508107 | Oct 12 11:18:09 AM UTC 24 | Oct 12 11:30:03 AM UTC 24 | 4791041841 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2524867970 | Oct 12 11:19:01 AM UTC 24 | Oct 12 11:30:15 AM UTC 24 | 16074552496 ps | ||
| T379 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.434249717 | Oct 12 11:21:01 AM UTC 24 | Oct 12 11:33:18 AM UTC 24 | 8873628362 ps | ||
| T381 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1575479073 | Oct 12 11:18:39 AM UTC 24 | Oct 12 11:36:07 AM UTC 24 | 12249848030 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2871375627 | Oct 12 11:20:10 AM UTC 24 | Oct 12 11:38:23 AM UTC 24 | 25302369799 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2421227975 | Oct 12 11:20:20 AM UTC 24 | Oct 12 11:38:58 AM UTC 24 | 112573897641 ps | ||
| T383 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2290659521 | Oct 12 11:21:17 AM UTC 24 | Oct 12 11:39:01 AM UTC 24 | 50201833296 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2318762079 | Oct 12 11:20:42 AM UTC 24 | Oct 12 11:41:23 AM UTC 24 | 66194887792 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1469275655 | Oct 12 11:22:03 AM UTC 24 | Oct 12 11:41:32 AM UTC 24 | 30126135742 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/1.alert_handler_sig_int_fail.1952481196 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1072725602 ps |
| CPU time | 19.96 seconds |
| Started | Oct 12 09:03:07 AM UTC 24 |
| Finished | Oct 12 09:03:28 AM UTC 24 |
| Peak memory | 266944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952481196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1952481196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/0.alert_handler_sec_cm.3378399342 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 569149971 ps |
| CPU time | 24.07 seconds |
| Started | Oct 12 09:03:05 AM UTC 24 |
| Finished | Oct 12 09:03:30 AM UTC 24 |
| Peak memory | 293008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378399342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3378399342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all_with_rand_reset.1873172568 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 10333213569 ps |
| CPU time | 203.38 seconds |
| Started | Oct 12 09:03:38 AM UTC 24 |
| Finished | Oct 12 09:07:05 AM UTC 24 |
| Peak memory | 283808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1873172568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.al ert_handler_stress_all_with_rand_reset.1873172568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy_stress.3035178310 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1338254728 ps |
| CPU time | 32.22 seconds |
| Started | Oct 12 09:03:02 AM UTC 24 |
| Finished | Oct 12 09:03:36 AM UTC 24 |
| Peak memory | 260840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035178310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3035178310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_intg_err.4041274834 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 256586058 ps |
| CPU time | 26.56 seconds |
| Started | Oct 12 11:04:26 AM UTC 24 |
| Finished | Oct 12 11:04:54 AM UTC 24 |
| Peak memory | 260352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041274834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.4041274834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all_with_rand_reset.1093610640 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 4608808981 ps |
| CPU time | 373.37 seconds |
| Started | Oct 12 09:10:38 AM UTC 24 |
| Finished | Oct 12 09:16:57 AM UTC 24 |
| Peak memory | 283744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1093610640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.al ert_handler_stress_all_with_rand_reset.1093610640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all_with_rand_reset.258229095 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 18655577850 ps |
| CPU time | 465.91 seconds |
| Started | Oct 12 09:04:49 AM UTC 24 |
| Finished | Oct 12 09:12:42 AM UTC 24 |
| Peak memory | 293720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=258229095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.ale rt_handler_stress_all_with_rand_reset.258229095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/2.alert_handler_sig_int_fail.1627836000 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 796103614 ps |
| CPU time | 55.76 seconds |
| Started | Oct 12 09:03:24 AM UTC 24 |
| Finished | Oct 12 09:04:22 AM UTC 24 |
| Peak memory | 266908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627836000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1627836000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.925701285 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 16019271511 ps |
| CPU time | 321.34 seconds |
| Started | Oct 12 11:18:25 AM UTC 24 |
| Finished | Oct 12 11:23:52 AM UTC 24 |
| Peak memory | 283276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925701285 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors.925701285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg.1601119755 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 67094105159 ps |
| CPU time | 1644.27 seconds |
| Started | Oct 12 09:11:40 AM UTC 24 |
| Finished | Oct 12 09:39:23 AM UTC 24 |
| Peak memory | 300064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601119755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1601119755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/10.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all_with_rand_reset.1296390170 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 27553592292 ps |
| CPU time | 553.8 seconds |
| Started | Oct 12 10:04:30 AM UTC 24 |
| Finished | Oct 12 10:13:51 AM UTC 24 |
| Peak memory | 283548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1296390170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.a lert_handler_stress_all_with_rand_reset.1296390170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/35.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_alerts.2562721626 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1978609679 ps |
| CPU time | 39.87 seconds |
| Started | Oct 12 09:03:00 AM UTC 24 |
| Finished | Oct 12 09:03:41 AM UTC 24 |
| Peak memory | 267012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562721626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2562721626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy.1574368427 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 31144527944 ps |
| CPU time | 2124.44 seconds |
| Started | Oct 12 09:03:51 AM UTC 24 |
| Finished | Oct 12 09:39:39 AM UTC 24 |
| Peak memory | 300072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574368427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1574368427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1492865049 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 4844700407 ps |
| CPU time | 733.06 seconds |
| Started | Oct 12 11:03:37 AM UTC 24 |
| Finished | Oct 12 11:16:00 AM UTC 24 |
| Peak memory | 277128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492865049 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shado w_reg_errors_with_csr_rw.1492865049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy.2117915554 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 33485085537 ps |
| CPU time | 964.47 seconds |
| Started | Oct 12 09:16:03 AM UTC 24 |
| Finished | Oct 12 09:32:18 AM UTC 24 |
| Peak memory | 277552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117915554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2117915554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/12.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3934385478 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 6792264000 ps |
| CPU time | 242.89 seconds |
| Started | Oct 12 11:18:39 AM UTC 24 |
| Finished | Oct 12 11:22:46 AM UTC 24 |
| Peak memory | 283268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934385478 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_errors.3934385478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/2.alert_handler_ping_timeout.1055035965 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 20844598919 ps |
| CPU time | 598.25 seconds |
| Started | Oct 12 09:03:25 AM UTC 24 |
| Finished | Oct 12 09:13:31 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055035965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1055035965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2276731729 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 11816950545 ps |
| CPU time | 740.06 seconds |
| Started | Oct 12 11:17:12 AM UTC 24 |
| Finished | Oct 12 11:29:43 AM UTC 24 |
| Peak memory | 277128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276731729 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shado w_reg_errors_with_csr_rw.2276731729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy.1886388549 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 13550696307 ps |
| CPU time | 1396.83 seconds |
| Started | Oct 12 09:05:13 AM UTC 24 |
| Finished | Oct 12 09:28:46 AM UTC 24 |
| Peak memory | 299812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886388549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1886388549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/5.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg.2948868737 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 135259156386 ps |
| CPU time | 2165.79 seconds |
| Started | Oct 12 09:03:29 AM UTC 24 |
| Finished | Oct 12 09:39:59 AM UTC 24 |
| Peak memory | 293744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948868737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2948868737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all_with_rand_reset.2469272163 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 9309888742 ps |
| CPU time | 487.64 seconds |
| Started | Oct 12 09:03:02 AM UTC 24 |
| Finished | Oct 12 09:11:16 AM UTC 24 |
| Peak memory | 283744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2469272163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.al ert_handler_stress_all_with_rand_reset.2469272163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_intr_test.3477645405 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 18111391 ps |
| CPU time | 1.72 seconds |
| Started | Oct 12 11:15:47 AM UTC 24 |
| Finished | Oct 12 11:15:50 AM UTC 24 |
| Peak memory | 246792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477645405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3477645405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1568832643 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 6646544719 ps |
| CPU time | 223.02 seconds |
| Started | Oct 12 11:03:48 AM UTC 24 |
| Finished | Oct 12 11:07:35 AM UTC 24 |
| Peak memory | 277204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568832643 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors.1568832643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_intr_timeout.1904613485 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 460914567 ps |
| CPU time | 38.01 seconds |
| Started | Oct 12 09:03:48 AM UTC 24 |
| Finished | Oct 12 09:04:27 AM UTC 24 |
| Peak memory | 260752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904613485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1904613485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg.2868959150 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 102034403396 ps |
| CPU time | 2626.8 seconds |
| Started | Oct 12 09:16:32 AM UTC 24 |
| Finished | Oct 12 10:00:48 AM UTC 24 |
| Peak memory | 299820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868959150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2868959150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/12.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2871375627 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 25302369799 ps |
| CPU time | 1078.35 seconds |
| Started | Oct 12 11:20:10 AM UTC 24 |
| Finished | Oct 12 11:38:23 AM UTC 24 |
| Peak memory | 279952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871375627 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shad ow_reg_errors_with_csr_rw.2871375627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/12.alert_handler_ping_timeout.2144786645 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 198611190556 ps |
| CPU time | 568.2 seconds |
| Started | Oct 12 09:16:13 AM UTC 24 |
| Finished | Oct 12 09:25:48 AM UTC 24 |
| Peak memory | 260904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144786645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2144786645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/12.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg.1578187556 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 133935077583 ps |
| CPU time | 2103.71 seconds |
| Started | Oct 12 10:07:31 AM UTC 24 |
| Finished | Oct 12 10:43:00 AM UTC 24 |
| Peak memory | 283508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578187556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1578187556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/37.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy.4294964548 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 19791951088 ps |
| CPU time | 1018.32 seconds |
| Started | Oct 12 09:03:07 AM UTC 24 |
| Finished | Oct 12 09:20:17 AM UTC 24 |
| Peak memory | 283700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294964548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.4294964548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_alert_accum.3889334084 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 2177674877 ps |
| CPU time | 116.22 seconds |
| Started | Oct 12 09:03:49 AM UTC 24 |
| Finished | Oct 12 09:05:48 AM UTC 24 |
| Peak memory | 266960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889334084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3889334084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg.708249811 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 72007900922 ps |
| CPU time | 1153.12 seconds |
| Started | Oct 12 09:29:19 AM UTC 24 |
| Finished | Oct 12 09:48:46 AM UTC 24 |
| Peak memory | 283620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708249811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.708249811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/18.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2524867970 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 16074552496 ps |
| CPU time | 664.62 seconds |
| Started | Oct 12 11:19:01 AM UTC 24 |
| Finished | Oct 12 11:30:15 AM UTC 24 |
| Peak memory | 283276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524867970 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shad ow_reg_errors_with_csr_rw.2524867970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/10.alert_handler_stress_all.891891222 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 188114459417 ps |
| CPU time | 2724.83 seconds |
| Started | Oct 12 09:12:43 AM UTC 24 |
| Finished | Oct 12 09:58:38 AM UTC 24 |
| Peak memory | 300144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891891222 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_stress_all.891891222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/10.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/13.alert_handler_ping_timeout.3432590690 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 21210410488 ps |
| CPU time | 399.01 seconds |
| Started | Oct 12 09:18:20 AM UTC 24 |
| Finished | Oct 12 09:25:04 AM UTC 24 |
| Peak memory | 260904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432590690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3432590690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/13.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/43.alert_handler_ping_timeout.636344512 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 50428959127 ps |
| CPU time | 540.76 seconds |
| Started | Oct 12 10:20:09 AM UTC 24 |
| Finished | Oct 12 10:29:17 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636344512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.636344512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/43.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2318762079 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 66194887792 ps |
| CPU time | 1224.6 seconds |
| Started | Oct 12 11:20:42 AM UTC 24 |
| Finished | Oct 12 11:41:23 AM UTC 24 |
| Peak memory | 285832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318762079 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shad ow_reg_errors_with_csr_rw.2318762079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all.1766449468 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 41172206603 ps |
| CPU time | 2933.56 seconds |
| Started | Oct 12 09:03:07 AM UTC 24 |
| Finished | Oct 12 09:52:34 AM UTC 24 |
| Peak memory | 310260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766449468 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_stress_all.1766449468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_intg_err.352085803 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 893563448 ps |
| CPU time | 76.89 seconds |
| Started | Oct 12 11:16:47 AM UTC 24 |
| Finished | Oct 12 11:18:06 AM UTC 24 |
| Peak memory | 250376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352085803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.352085803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/5.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/3.alert_handler_ping_timeout.3159201279 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 18058529650 ps |
| CPU time | 302.4 seconds |
| Started | Oct 12 09:03:55 AM UTC 24 |
| Finished | Oct 12 09:09:02 AM UTC 24 |
| Peak memory | 267244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159201279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3159201279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg.3558494996 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 142056229388 ps |
| CPU time | 2161.66 seconds |
| Started | Oct 12 09:23:23 AM UTC 24 |
| Finished | Oct 12 09:59:49 AM UTC 24 |
| Peak memory | 283760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558494996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3558494996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/15.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/6.alert_handler_ping_timeout.3538419474 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 38053122568 ps |
| CPU time | 554.63 seconds |
| Started | Oct 12 09:05:52 AM UTC 24 |
| Finished | Oct 12 09:15:13 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538419474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3538419474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/6.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/37.alert_handler_stress_all_with_rand_reset.2176722445 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 11670280834 ps |
| CPU time | 393.94 seconds |
| Started | Oct 12 10:08:05 AM UTC 24 |
| Finished | Oct 12 10:14:44 AM UTC 24 |
| Peak memory | 279456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2176722445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.a lert_handler_stress_all_with_rand_reset.2176722445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/37.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.757418345 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 1632626225 ps |
| CPU time | 104.76 seconds |
| Started | Oct 12 11:17:45 AM UTC 24 |
| Finished | Oct 12 11:19:33 AM UTC 24 |
| Peak memory | 266816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757418345 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors.757418345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_alert_accum.246878881 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 15142686344 ps |
| CPU time | 139.83 seconds |
| Started | Oct 12 09:03:07 AM UTC 24 |
| Finished | Oct 12 09:05:29 AM UTC 24 |
| Peak memory | 266968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246878881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.246878881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all_with_rand_reset.4027083059 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 2560330453 ps |
| CPU time | 185.51 seconds |
| Started | Oct 12 09:41:46 AM UTC 24 |
| Finished | Oct 12 09:44:55 AM UTC 24 |
| Peak memory | 277408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4027083059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.a lert_handler_stress_all_with_rand_reset.4027083059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/23.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_intr_test.4081778985 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 9257881 ps |
| CPU time | 2.25 seconds |
| Started | Oct 12 11:18:32 AM UTC 24 |
| Finished | Oct 12 11:18:36 AM UTC 24 |
| Peak memory | 248204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081778985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.4081778985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/9.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all_with_rand_reset.2886321402 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 14425755393 ps |
| CPU time | 510.26 seconds |
| Started | Oct 12 09:25:28 AM UTC 24 |
| Finished | Oct 12 09:34:05 AM UTC 24 |
| Peak memory | 283472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2886321402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.a lert_handler_stress_all_with_rand_reset.2886321402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/16.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/6.alert_handler_sig_int_fail.1335344067 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 875578856 ps |
| CPU time | 33.8 seconds |
| Started | Oct 12 09:05:49 AM UTC 24 |
| Finished | Oct 12 09:06:24 AM UTC 24 |
| Peak memory | 260864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335344067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1335344067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/6.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/1.alert_handler_smoke.4201351931 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3221702709 ps |
| CPU time | 29.03 seconds |
| Started | Oct 12 09:03:06 AM UTC 24 |
| Finished | Oct 12 09:03:37 AM UTC 24 |
| Peak memory | 260824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201351931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.4201351931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1469275655 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 30126135742 ps |
| CPU time | 1152.8 seconds |
| Started | Oct 12 11:22:03 AM UTC 24 |
| Finished | Oct 12 11:41:32 AM UTC 24 |
| Peak memory | 279760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469275655 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shad ow_reg_errors_with_csr_rw.1469275655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all.2865709068 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 162032013437 ps |
| CPU time | 2559.57 seconds |
| Started | Oct 12 09:25:23 AM UTC 24 |
| Finished | Oct 12 10:08:32 AM UTC 24 |
| Peak memory | 301428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865709068 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_stress_all.2865709068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/16.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all.2440494609 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 82320145287 ps |
| CPU time | 4429.76 seconds |
| Started | Oct 12 09:39:45 AM UTC 24 |
| Finished | Oct 12 10:54:26 AM UTC 24 |
| Peak memory | 312544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440494609 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_stress_all.2440494609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/22.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg.3659956152 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 164708073348 ps |
| CPU time | 2389.87 seconds |
| Started | Oct 12 09:03:55 AM UTC 24 |
| Finished | Oct 12 09:44:11 AM UTC 24 |
| Peak memory | 299740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659956152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3659956152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all.2261848790 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 72163578855 ps |
| CPU time | 2389.72 seconds |
| Started | Oct 12 09:04:02 AM UTC 24 |
| Finished | Oct 12 09:44:19 AM UTC 24 |
| Peak memory | 299756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261848790 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_stress_all.2261848790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.4074533382 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 4303658106 ps |
| CPU time | 344.89 seconds |
| Started | Oct 12 11:12:25 AM UTC 24 |
| Finished | Oct 12 11:18:16 AM UTC 24 |
| Peak memory | 277332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074533382 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors.4074533382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/24.alert_handler_ping_timeout.1314535249 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 13090670645 ps |
| CPU time | 340.12 seconds |
| Started | Oct 12 09:43:19 AM UTC 24 |
| Finished | Oct 12 09:49:04 AM UTC 24 |
| Peak memory | 261096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314535249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1314535249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/24.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all.2037957974 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 51073321938 ps |
| CPU time | 504.86 seconds |
| Started | Oct 12 09:04:48 AM UTC 24 |
| Finished | Oct 12 09:13:20 AM UTC 24 |
| Peak memory | 266968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037957974 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_stress_all.2037957974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg.373431179 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 162814981824 ps |
| CPU time | 2878.8 seconds |
| Started | Oct 12 10:14:49 AM UTC 24 |
| Finished | Oct 12 11:03:25 AM UTC 24 |
| Peak memory | 286176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373431179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.373431179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/40.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all_with_rand_reset.575458472 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 4120295774 ps |
| CPU time | 374.22 seconds |
| Started | Oct 12 09:34:17 AM UTC 24 |
| Finished | Oct 12 09:40:36 AM UTC 24 |
| Peak memory | 277340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=575458472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.al ert_handler_stress_all_with_rand_reset.575458472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/20.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all.1035314767 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 210696058645 ps |
| CPU time | 3323.82 seconds |
| Started | Oct 12 09:54:43 AM UTC 24 |
| Finished | Oct 12 10:50:47 AM UTC 24 |
| Peak memory | 302380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035314767 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_stress_all.1035314767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/29.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/39.alert_handler_entropy.423632790 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 31781723710 ps |
| CPU time | 741.04 seconds |
| Started | Oct 12 10:12:03 AM UTC 24 |
| Finished | Oct 12 10:24:33 AM UTC 24 |
| Peak memory | 283376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423632790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.423632790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/39.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/0.alert_handler_alert_accum_saturation.3575505562 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 20852991 ps |
| CPU time | 2.54 seconds |
| Started | Oct 12 09:03:02 AM UTC 24 |
| Finished | Oct 12 09:03:06 AM UTC 24 |
| Peak memory | 261024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575505562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3575505562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/1.alert_handler_alert_accum_saturation.714493889 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 18129641 ps |
| CPU time | 4.23 seconds |
| Started | Oct 12 09:03:07 AM UTC 24 |
| Finished | Oct 12 09:03:12 AM UTC 24 |
| Peak memory | 260968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714493889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.714493889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/11.alert_handler_alert_accum_saturation.3443375919 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 49231778 ps |
| CPU time | 5.81 seconds |
| Started | Oct 12 09:14:41 AM UTC 24 |
| Finished | Oct 12 09:14:48 AM UTC 24 |
| Peak memory | 261296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443375919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3443375919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/11.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/6.alert_handler_alert_accum_saturation.771742618 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 49154989 ps |
| CPU time | 6.05 seconds |
| Started | Oct 12 09:06:25 AM UTC 24 |
| Finished | Oct 12 09:06:32 AM UTC 24 |
| Peak memory | 267108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771742618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.771742618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/6.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg.1833601409 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 53414733284 ps |
| CPU time | 2851.82 seconds |
| Started | Oct 12 09:46:38 AM UTC 24 |
| Finished | Oct 12 10:34:44 AM UTC 24 |
| Peak memory | 302232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833601409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1833601409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/26.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all_with_rand_reset.190842407 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 4619154286 ps |
| CPU time | 351 seconds |
| Started | Oct 12 09:46:55 AM UTC 24 |
| Finished | Oct 12 09:52:51 AM UTC 24 |
| Peak memory | 283556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=190842407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.al ert_handler_stress_all_with_rand_reset.190842407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/26.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_intr_timeout.494640679 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 4313255276 ps |
| CPU time | 82.66 seconds |
| Started | Oct 12 09:48:07 AM UTC 24 |
| Finished | Oct 12 09:49:31 AM UTC 24 |
| Peak memory | 261124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494640679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.494640679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/27.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all_with_rand_reset.574372058 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 15521508681 ps |
| CPU time | 544.78 seconds |
| Started | Oct 12 09:04:04 AM UTC 24 |
| Finished | Oct 12 09:13:16 AM UTC 24 |
| Peak memory | 281504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=574372058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.ale rt_handler_stress_all_with_rand_reset.574372058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2685248199 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 125282087 ps |
| CPU time | 3.55 seconds |
| Started | Oct 12 11:20:45 AM UTC 24 |
| Finished | Oct 12 11:20:50 AM UTC 24 |
| Peak memory | 248260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685248199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2685248199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/16.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.4028319558 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 3255857913 ps |
| CPU time | 222.5 seconds |
| Started | Oct 12 11:20:12 AM UTC 24 |
| Finished | Oct 12 11:23:59 AM UTC 24 |
| Peak memory | 277196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028319558 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_errors.4028319558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.434249717 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 8873628362 ps |
| CPU time | 725.63 seconds |
| Started | Oct 12 11:21:01 AM UTC 24 |
| Finished | Oct 12 11:33:18 AM UTC 24 |
| Peak memory | 277120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434249717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shado w_reg_errors_with_csr_rw.434249717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3191143921 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 16584626146 ps |
| CPU time | 379.07 seconds |
| Started | Oct 12 11:17:16 AM UTC 24 |
| Finished | Oct 12 11:23:41 AM UTC 24 |
| Peak memory | 277128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191143921 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors.3191143921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_rw.2016806054 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 126209274 ps |
| CPU time | 6.56 seconds |
| Started | Oct 12 11:05:08 AM UTC 24 |
| Finished | Oct 12 11:05:15 AM UTC 24 |
| Peak memory | 250108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016806054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2016806054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_intr_test.555831045 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 8518010 ps |
| CPU time | 1.7 seconds |
| Started | Oct 12 11:10:42 AM UTC 24 |
| Finished | Oct 12 11:10:45 AM UTC 24 |
| Peak memory | 244736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555831045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.555831045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg_stub_clk.2072721180 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 55256732292 ps |
| CPU time | 2775.58 seconds |
| Started | Oct 12 09:03:02 AM UTC 24 |
| Finished | Oct 12 09:49:47 AM UTC 24 |
| Peak memory | 300004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072721180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2072721180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all.283872421 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 11981966991 ps |
| CPU time | 271.26 seconds |
| Started | Oct 12 09:19:16 AM UTC 24 |
| Finished | Oct 12 09:23:51 AM UTC 24 |
| Peak memory | 267236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283872421 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_stress_all.283872421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/13.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy.3841120279 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 75660036429 ps |
| CPU time | 2098.56 seconds |
| Started | Oct 12 09:20:48 AM UTC 24 |
| Finished | Oct 12 09:56:10 AM UTC 24 |
| Peak memory | 283680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841120279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3841120279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/14.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg_stub_clk.3833758029 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 19560387931 ps |
| CPU time | 1126.92 seconds |
| Started | Oct 12 09:25:06 AM UTC 24 |
| Finished | Oct 12 09:44:06 AM UTC 24 |
| Peak memory | 277288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833758029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3833758029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/16.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/16.alert_handler_ping_timeout.2547302863 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 54749437573 ps |
| CPU time | 212.78 seconds |
| Started | Oct 12 09:24:49 AM UTC 24 |
| Finished | Oct 12 09:28:25 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547302863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2547302863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/16.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/22.alert_handler_sig_int_fail.642566515 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 826197301 ps |
| CPU time | 59.89 seconds |
| Started | Oct 12 09:38:51 AM UTC 24 |
| Finished | Oct 12 09:39:53 AM UTC 24 |
| Peak memory | 260864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642566515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.642566515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/22.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/24.alert_handler_sig_int_fail.3949426693 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 439277743 ps |
| CPU time | 37.6 seconds |
| Started | Oct 12 09:42:39 AM UTC 24 |
| Finished | Oct 12 09:43:18 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949426693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3949426693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/24.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/30.alert_handler_sig_int_fail.765949534 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 773280800 ps |
| CPU time | 71.93 seconds |
| Started | Oct 12 09:55:40 AM UTC 24 |
| Finished | Oct 12 09:56:54 AM UTC 24 |
| Peak memory | 260764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765949534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.765949534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/30.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all.3875804389 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 15277381557 ps |
| CPU time | 445.7 seconds |
| Started | Oct 12 09:56:19 AM UTC 24 |
| Finished | Oct 12 10:03:51 AM UTC 24 |
| Peak memory | 277284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875804389 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_stress_all.3875804389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/30.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg.3828096727 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 900481538366 ps |
| CPU time | 3172.76 seconds |
| Started | Oct 12 10:01:51 AM UTC 24 |
| Finished | Oct 12 10:55:22 AM UTC 24 |
| Peak memory | 302232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828096727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3828096727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/33.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/35.alert_handler_sig_int_fail.3587566218 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 419177540 ps |
| CPU time | 15.98 seconds |
| Started | Oct 12 10:04:12 AM UTC 24 |
| Finished | Oct 12 10:04:29 AM UTC 24 |
| Peak memory | 267168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587566218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3587566218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/35.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg.3070802600 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 51833553111 ps |
| CPU time | 3221.88 seconds |
| Started | Oct 12 10:23:04 AM UTC 24 |
| Finished | Oct 12 11:17:29 AM UTC 24 |
| Peak memory | 302556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070802600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3070802600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/45.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy.3051928689 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 188580118737 ps |
| CPU time | 1199.45 seconds |
| Started | Oct 12 09:05:50 AM UTC 24 |
| Finished | Oct 12 09:26:03 AM UTC 24 |
| Peak memory | 283360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051928689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3051928689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/6.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/0.alert_handler_smoke.18051519 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 530117447 ps |
| CPU time | 22.92 seconds |
| Started | Oct 12 09:03:00 AM UTC 24 |
| Finished | Oct 12 09:03:24 AM UTC 24 |
| Peak memory | 266908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18051519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smo ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.18051519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3459589969 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1835232640 ps |
| CPU time | 97.09 seconds |
| Started | Oct 12 11:19:05 AM UTC 24 |
| Finished | Oct 12 11:20:45 AM UTC 24 |
| Peak memory | 248320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459589969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3459589969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/11.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2277884213 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 898570058 ps |
| CPU time | 74.53 seconds |
| Started | Oct 12 11:21:45 AM UTC 24 |
| Finished | Oct 12 11:23:01 AM UTC 24 |
| Peak memory | 250100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277884213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2277884213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/18.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1920163098 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 4376923174 ps |
| CPU time | 87.09 seconds |
| Started | Oct 12 11:17:31 AM UTC 24 |
| Finished | Oct 12 11:19:00 AM UTC 24 |
| Peak memory | 250176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920163098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1920163098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/6.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.314763591 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 1539613704 ps |
| CPU time | 199.39 seconds |
| Started | Oct 12 11:19:34 AM UTC 24 |
| Finished | Oct 12 11:22:57 AM UTC 24 |
| Peak memory | 277072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314763591 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors.314763591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1431709957 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 155343776 ps |
| CPU time | 30.6 seconds |
| Started | Oct 12 11:19:39 AM UTC 24 |
| Finished | Oct 12 11:20:11 AM UTC 24 |
| Peak memory | 250308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431709957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1431709957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/12.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2988196071 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 3998380207 ps |
| CPU time | 162.99 seconds |
| Started | Oct 12 11:20:01 AM UTC 24 |
| Finished | Oct 12 11:22:47 AM UTC 24 |
| Peak memory | 277324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988196071 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_errors.2988196071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2441477272 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1835354465 ps |
| CPU time | 77.77 seconds |
| Started | Oct 12 11:21:07 AM UTC 24 |
| Finished | Oct 12 11:22:27 AM UTC 24 |
| Peak memory | 260344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441477272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2441477272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/17.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_intg_err.606702903 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 181141534 ps |
| CPU time | 5.03 seconds |
| Started | Oct 12 11:18:31 AM UTC 24 |
| Finished | Oct 12 11:18:37 AM UTC 24 |
| Peak memory | 250108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606702903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.606702903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/9.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1439311835 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 23868299 ps |
| CPU time | 2.78 seconds |
| Started | Oct 12 11:10:38 AM UTC 24 |
| Finished | Oct 12 11:10:42 AM UTC 24 |
| Peak memory | 248144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439311835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1439311835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3418301426 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 101649014 ps |
| CPU time | 4.53 seconds |
| Started | Oct 12 11:18:44 AM UTC 24 |
| Finished | Oct 12 11:18:50 AM UTC 24 |
| Peak memory | 248060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418301426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3418301426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/10.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_intg_err.531345780 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 3445203698 ps |
| CPU time | 38.33 seconds |
| Started | Oct 12 11:20:26 AM UTC 24 |
| Finished | Oct 12 11:21:06 AM UTC 24 |
| Peak memory | 250248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531345780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.531345780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/15.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3880281273 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1175031014 ps |
| CPU time | 42.75 seconds |
| Started | Oct 12 11:12:44 AM UTC 24 |
| Finished | Oct 12 11:13:28 AM UTC 24 |
| Peak memory | 250184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880281273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3880281273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_intg_err.452998240 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 58730679 ps |
| CPU time | 4.36 seconds |
| Started | Oct 12 11:15:41 AM UTC 24 |
| Finished | Oct 12 11:15:46 AM UTC 24 |
| Peak memory | 248060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452998240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.452998240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3291373964 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 2156407104 ps |
| CPU time | 153.23 seconds |
| Started | Oct 12 11:07:36 AM UTC 24 |
| Finished | Oct 12 11:10:12 AM UTC 24 |
| Peak memory | 250180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291373964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3291373964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3880302716 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 57085950655 ps |
| CPU time | 615.56 seconds |
| Started | Oct 12 11:05:16 AM UTC 24 |
| Finished | Oct 12 11:15:40 AM UTC 24 |
| Peak memory | 250248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880302716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3880302716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3324369982 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 353927642 ps |
| CPU time | 6.3 seconds |
| Started | Oct 12 11:04:59 AM UTC 24 |
| Finished | Oct 12 11:05:07 AM UTC 24 |
| Peak memory | 260552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324369982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3324369982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3854477510 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 76283425 ps |
| CPU time | 7.85 seconds |
| Started | Oct 12 11:08:13 AM UTC 24 |
| Finished | Oct 12 11:08:22 AM UTC 24 |
| Peak memory | 262468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854477510 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_mem_ rw_with_rand_reset.3854477510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_intr_test.2594832596 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 8244041 ps |
| CPU time | 1.82 seconds |
| Started | Oct 12 11:04:55 AM UTC 24 |
| Finished | Oct 12 11:04:58 AM UTC 24 |
| Peak memory | 246856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594832596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2594832596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2986603281 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 269194432 ps |
| CPU time | 20.55 seconds |
| Started | Oct 12 11:08:07 AM UTC 24 |
| Finished | Oct 12 11:08:28 AM UTC 24 |
| Peak memory | 250308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986603281 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outstanding.2986603281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_errors.2312399252 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 84168754 ps |
| CPU time | 12.3 seconds |
| Started | Oct 12 11:04:12 AM UTC 24 |
| Finished | Oct 12 11:04:26 AM UTC 24 |
| Peak memory | 266568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312399252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2312399252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_aliasing.89273991 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 9010823038 ps |
| CPU time | 311.57 seconds |
| Started | Oct 12 11:10:55 AM UTC 24 |
| Finished | Oct 12 11:16:11 AM UTC 24 |
| Peak memory | 250172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89273991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test + UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.89273991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.728827521 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1574402595 ps |
| CPU time | 100.65 seconds |
| Started | Oct 12 11:10:53 AM UTC 24 |
| Finished | Oct 12 11:12:36 AM UTC 24 |
| Peak memory | 248072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728827521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/al ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.728827521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.683629291 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 397776726 ps |
| CPU time | 9.48 seconds |
| Started | Oct 12 11:10:43 AM UTC 24 |
| Finished | Oct 12 11:10:54 AM UTC 24 |
| Peak memory | 260424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683629291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/al ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.683629291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.260244297 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 72043687 ps |
| CPU time | 10.4 seconds |
| Started | Oct 12 11:11:13 AM UTC 24 |
| Finished | Oct 12 11:11:25 AM UTC 24 |
| Peak memory | 262536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260244297 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_mem_r w_with_rand_reset.260244297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_rw.425839323 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 253920643 ps |
| CPU time | 10.23 seconds |
| Started | Oct 12 11:10:45 AM UTC 24 |
| Finished | Oct 12 11:10:57 AM UTC 24 |
| Peak memory | 248132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425839323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.425839323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2402602977 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 328640928 ps |
| CPU time | 13.26 seconds |
| Started | Oct 12 11:10:58 AM UTC 24 |
| Finished | Oct 12 11:11:13 AM UTC 24 |
| Peak memory | 258296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402602977 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outstanding.2402602977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1191576625 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 11347372633 ps |
| CPU time | 231.03 seconds |
| Started | Oct 12 11:08:29 AM UTC 24 |
| Finished | Oct 12 11:12:24 AM UTC 24 |
| Peak memory | 277200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191576625 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors.1191576625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2634291870 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 15185450823 ps |
| CPU time | 1187.51 seconds |
| Started | Oct 12 11:08:23 AM UTC 24 |
| Finished | Oct 12 11:28:29 AM UTC 24 |
| Peak memory | 283268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634291870 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shado w_reg_errors_with_csr_rw.2634291870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_errors.2664308793 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 311425622 ps |
| CPU time | 26.57 seconds |
| Started | Oct 12 11:10:13 AM UTC 24 |
| Finished | Oct 12 11:10:41 AM UTC 24 |
| Peak memory | 260356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664308793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2664308793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.4198926940 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 75733541 ps |
| CPU time | 7.98 seconds |
| Started | Oct 12 11:18:54 AM UTC 24 |
| Finished | Oct 12 11:19:03 AM UTC 24 |
| Peak memory | 250072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198926940 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_mem _rw_with_rand_reset.4198926940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/10.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_rw.3103456590 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 127776852 ps |
| CPU time | 10.37 seconds |
| Started | Oct 12 11:18:52 AM UTC 24 |
| Finished | Oct 12 11:19:04 AM UTC 24 |
| Peak memory | 250308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103456590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3103456590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/10.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_intr_test.1272434432 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 12155802 ps |
| CPU time | 1.75 seconds |
| Started | Oct 12 11:18:50 AM UTC 24 |
| Finished | Oct 12 11:18:53 AM UTC 24 |
| Peak memory | 246792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272434432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1272434432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/10.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3456940706 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 5375497518 ps |
| CPU time | 41.2 seconds |
| Started | Oct 12 11:18:53 AM UTC 24 |
| Finished | Oct 12 11:19:36 AM UTC 24 |
| Peak memory | 260288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456940706 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_outstanding.3456940706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/10.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1575479073 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 12249848030 ps |
| CPU time | 1033.97 seconds |
| Started | Oct 12 11:18:39 AM UTC 24 |
| Finished | Oct 12 11:36:07 AM UTC 24 |
| Peak memory | 285904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575479073 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shad ow_reg_errors_with_csr_rw.1575479073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_errors.2713392147 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 49843178 ps |
| CPU time | 8.2 seconds |
| Started | Oct 12 11:18:42 AM UTC 24 |
| Finished | Oct 12 11:18:51 AM UTC 24 |
| Peak memory | 260560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713392147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2713392147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/10.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2723204154 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 95240064 ps |
| CPU time | 9.58 seconds |
| Started | Oct 12 11:19:28 AM UTC 24 |
| Finished | Oct 12 11:19:38 AM UTC 24 |
| Peak memory | 248204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723204154 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_mem _rw_with_rand_reset.2723204154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/11.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_rw.2918112334 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 487204469 ps |
| CPU time | 5.42 seconds |
| Started | Oct 12 11:19:09 AM UTC 24 |
| Finished | Oct 12 11:19:16 AM UTC 24 |
| Peak memory | 248260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918112334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2918112334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/11.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_intr_test.3389009741 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 10675720 ps |
| CPU time | 2.33 seconds |
| Started | Oct 12 11:19:05 AM UTC 24 |
| Finished | Oct 12 11:19:09 AM UTC 24 |
| Peak memory | 248208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389009741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3389009741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/11.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.279169881 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 646853010 ps |
| CPU time | 28.05 seconds |
| Started | Oct 12 11:19:16 AM UTC 24 |
| Finished | Oct 12 11:19:46 AM UTC 24 |
| Peak memory | 258376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279169881 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_outstanding.279169881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/11.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1984720075 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 8372326475 ps |
| CPU time | 230.89 seconds |
| Started | Oct 12 11:19:02 AM UTC 24 |
| Finished | Oct 12 11:22:57 AM UTC 24 |
| Peak memory | 277124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984720075 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_errors.1984720075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_errors.3457251637 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 283883459 ps |
| CPU time | 22.47 seconds |
| Started | Oct 12 11:19:03 AM UTC 24 |
| Finished | Oct 12 11:19:27 AM UTC 24 |
| Peak memory | 260364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457251637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3457251637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/11.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.631664696 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 215836530 ps |
| CPU time | 12.5 seconds |
| Started | Oct 12 11:19:48 AM UTC 24 |
| Finished | Oct 12 11:20:02 AM UTC 24 |
| Peak memory | 264512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631664696 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_mem_ rw_with_rand_reset.631664696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/12.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_rw.875529574 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 185613014 ps |
| CPU time | 7.26 seconds |
| Started | Oct 12 11:19:47 AM UTC 24 |
| Finished | Oct 12 11:19:56 AM UTC 24 |
| Peak memory | 248060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875529574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.875529574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/12.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_intr_test.3742943068 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 21739739 ps |
| CPU time | 3.02 seconds |
| Started | Oct 12 11:19:42 AM UTC 24 |
| Finished | Oct 12 11:19:46 AM UTC 24 |
| Peak memory | 248272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742943068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3742943068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/12.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2935112952 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 2618149815 ps |
| CPU time | 52.36 seconds |
| Started | Oct 12 11:19:47 AM UTC 24 |
| Finished | Oct 12 11:20:41 AM UTC 24 |
| Peak memory | 260488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935112952 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_outstanding.2935112952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/12.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2291687966 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 27539021794 ps |
| CPU time | 544.31 seconds |
| Started | Oct 12 11:19:31 AM UTC 24 |
| Finished | Oct 12 11:28:43 AM UTC 24 |
| Peak memory | 281224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291687966 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shad ow_reg_errors_with_csr_rw.2291687966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_errors.1029107698 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 1387086145 ps |
| CPU time | 24.61 seconds |
| Started | Oct 12 11:19:37 AM UTC 24 |
| Finished | Oct 12 11:20:03 AM UTC 24 |
| Peak memory | 266576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029107698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1029107698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/12.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3809512272 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 373845135 ps |
| CPU time | 8.82 seconds |
| Started | Oct 12 11:20:08 AM UTC 24 |
| Finished | Oct 12 11:20:18 AM UTC 24 |
| Peak memory | 250248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809512272 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_mem _rw_with_rand_reset.3809512272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/13.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_rw.2760045550 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 183298813 ps |
| CPU time | 5.65 seconds |
| Started | Oct 12 11:20:06 AM UTC 24 |
| Finished | Oct 12 11:20:13 AM UTC 24 |
| Peak memory | 248132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760045550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2760045550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/13.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_intr_test.843248101 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 21475322 ps |
| CPU time | 1.96 seconds |
| Started | Oct 12 11:20:05 AM UTC 24 |
| Finished | Oct 12 11:20:08 AM UTC 24 |
| Peak memory | 246792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843248101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.843248101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/13.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2442964933 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 99761793 ps |
| CPU time | 16.36 seconds |
| Started | Oct 12 11:20:06 AM UTC 24 |
| Finished | Oct 12 11:20:24 AM UTC 24 |
| Peak memory | 260352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442964933 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_outstanding.2442964933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/13.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1631809081 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 24975136137 ps |
| CPU time | 532.62 seconds |
| Started | Oct 12 11:19:56 AM UTC 24 |
| Finished | Oct 12 11:28:57 AM UTC 24 |
| Peak memory | 277128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631809081 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shad ow_reg_errors_with_csr_rw.1631809081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_errors.864649352 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 605885070 ps |
| CPU time | 14.66 seconds |
| Started | Oct 12 11:20:03 AM UTC 24 |
| Finished | Oct 12 11:20:18 AM UTC 24 |
| Peak memory | 260360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864649352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.864649352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/13.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_intg_err.742872835 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 156844701 ps |
| CPU time | 3.2 seconds |
| Started | Oct 12 11:20:04 AM UTC 24 |
| Finished | Oct 12 11:20:08 AM UTC 24 |
| Peak memory | 248136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742872835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.742872835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/13.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2545646098 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 100343018 ps |
| CPU time | 10.06 seconds |
| Started | Oct 12 11:20:20 AM UTC 24 |
| Finished | Oct 12 11:20:31 AM UTC 24 |
| Peak memory | 250376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545646098 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_mem _rw_with_rand_reset.2545646098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/14.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_rw.3925390605 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 103837585 ps |
| CPU time | 6.35 seconds |
| Started | Oct 12 11:20:18 AM UTC 24 |
| Finished | Oct 12 11:20:25 AM UTC 24 |
| Peak memory | 250108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925390605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3925390605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/14.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_intr_test.3619732699 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 10445563 ps |
| CPU time | 2.08 seconds |
| Started | Oct 12 11:20:13 AM UTC 24 |
| Finished | Oct 12 11:20:17 AM UTC 24 |
| Peak memory | 248080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619732699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3619732699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/14.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1086873770 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 657591915 ps |
| CPU time | 50.68 seconds |
| Started | Oct 12 11:20:19 AM UTC 24 |
| Finished | Oct 12 11:21:11 AM UTC 24 |
| Peak memory | 258504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086873770 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_outstanding.1086873770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/14.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_errors.2502504849 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 4343161798 ps |
| CPU time | 28.93 seconds |
| Started | Oct 12 11:20:12 AM UTC 24 |
| Finished | Oct 12 11:20:43 AM UTC 24 |
| Peak memory | 260424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502504849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2502504849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/14.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1935198814 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 35495053 ps |
| CPU time | 3.61 seconds |
| Started | Oct 12 11:20:13 AM UTC 24 |
| Finished | Oct 12 11:20:18 AM UTC 24 |
| Peak memory | 248256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935198814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1935198814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/14.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3437258298 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 64010017 ps |
| CPU time | 6 seconds |
| Started | Oct 12 11:20:41 AM UTC 24 |
| Finished | Oct 12 11:20:48 AM UTC 24 |
| Peak memory | 266764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437258298 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_mem _rw_with_rand_reset.3437258298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/15.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_rw.1006422835 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 117932337 ps |
| CPU time | 6.23 seconds |
| Started | Oct 12 11:20:35 AM UTC 24 |
| Finished | Oct 12 11:20:43 AM UTC 24 |
| Peak memory | 250108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006422835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1006422835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/15.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_intr_test.922812327 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 30731854 ps |
| CPU time | 2.04 seconds |
| Started | Oct 12 11:20:32 AM UTC 24 |
| Finished | Oct 12 11:20:35 AM UTC 24 |
| Peak memory | 248208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922812327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.922812327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/15.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.4092143990 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 169280920 ps |
| CPU time | 28.21 seconds |
| Started | Oct 12 11:20:37 AM UTC 24 |
| Finished | Oct 12 11:21:06 AM UTC 24 |
| Peak memory | 258308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092143990 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_outstanding.4092143990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/15.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2713188931 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 1642022875 ps |
| CPU time | 121.55 seconds |
| Started | Oct 12 11:20:25 AM UTC 24 |
| Finished | Oct 12 11:22:29 AM UTC 24 |
| Peak memory | 277040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713188931 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors.2713188931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2421227975 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 112573897641 ps |
| CPU time | 1102.53 seconds |
| Started | Oct 12 11:20:20 AM UTC 24 |
| Finished | Oct 12 11:38:58 AM UTC 24 |
| Peak memory | 279688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421227975 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shad ow_reg_errors_with_csr_rw.2421227975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_errors.3946271618 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 567617751 ps |
| CPU time | 12.92 seconds |
| Started | Oct 12 11:20:26 AM UTC 24 |
| Finished | Oct 12 11:20:40 AM UTC 24 |
| Peak memory | 266504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946271618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3946271618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/15.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1183961654 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 1032820631 ps |
| CPU time | 9.95 seconds |
| Started | Oct 12 11:20:52 AM UTC 24 |
| Finished | Oct 12 11:21:03 AM UTC 24 |
| Peak memory | 250176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183961654 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_mem _rw_with_rand_reset.1183961654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/16.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_rw.1192048493 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 128248878 ps |
| CPU time | 11.69 seconds |
| Started | Oct 12 11:20:50 AM UTC 24 |
| Finished | Oct 12 11:21:03 AM UTC 24 |
| Peak memory | 248060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192048493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1192048493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/16.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_intr_test.2116703842 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 7366593 ps |
| CPU time | 1.86 seconds |
| Started | Oct 12 11:20:48 AM UTC 24 |
| Finished | Oct 12 11:20:51 AM UTC 24 |
| Peak memory | 246792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116703842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2116703842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/16.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2118100276 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 696606252 ps |
| CPU time | 50.37 seconds |
| Started | Oct 12 11:20:52 AM UTC 24 |
| Finished | Oct 12 11:21:44 AM UTC 24 |
| Peak memory | 258504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118100276 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_outstanding.2118100276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/16.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.4110714286 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 8112647642 ps |
| CPU time | 178.15 seconds |
| Started | Oct 12 11:20:44 AM UTC 24 |
| Finished | Oct 12 11:23:45 AM UTC 24 |
| Peak memory | 277124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110714286 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_errors.4110714286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_errors.3858513520 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 1154864057 ps |
| CPU time | 24.15 seconds |
| Started | Oct 12 11:20:44 AM UTC 24 |
| Finished | Oct 12 11:21:09 AM UTC 24 |
| Peak memory | 260356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858513520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3858513520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/16.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.781958088 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 2210549289 ps |
| CPU time | 13.81 seconds |
| Started | Oct 12 11:21:12 AM UTC 24 |
| Finished | Oct 12 11:21:27 AM UTC 24 |
| Peak memory | 262732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781958088 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_mem_ rw_with_rand_reset.781958088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/17.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_rw.2553029150 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 181226102 ps |
| CPU time | 5.35 seconds |
| Started | Oct 12 11:21:10 AM UTC 24 |
| Finished | Oct 12 11:21:16 AM UTC 24 |
| Peak memory | 250108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553029150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2553029150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/17.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_intr_test.2616961036 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 15646555 ps |
| CPU time | 1.98 seconds |
| Started | Oct 12 11:21:07 AM UTC 24 |
| Finished | Oct 12 11:21:10 AM UTC 24 |
| Peak memory | 246728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616961036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2616961036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/17.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.4009534442 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 3812521927 ps |
| CPU time | 50.22 seconds |
| Started | Oct 12 11:21:11 AM UTC 24 |
| Finished | Oct 12 11:22:03 AM UTC 24 |
| Peak memory | 260616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009534442 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_outstanding.4009534442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/17.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3975995961 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 19163047770 ps |
| CPU time | 403.37 seconds |
| Started | Oct 12 11:21:03 AM UTC 24 |
| Finished | Oct 12 11:27:53 AM UTC 24 |
| Peak memory | 277196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975995961 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_errors.3975995961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_errors.1769299088 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 312308868 ps |
| CPU time | 24.96 seconds |
| Started | Oct 12 11:21:04 AM UTC 24 |
| Finished | Oct 12 11:21:31 AM UTC 24 |
| Peak memory | 266764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769299088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1769299088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/17.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1238468420 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 66621808 ps |
| CPU time | 6.41 seconds |
| Started | Oct 12 11:22:01 AM UTC 24 |
| Finished | Oct 12 11:22:09 AM UTC 24 |
| Peak memory | 248204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238468420 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_mem _rw_with_rand_reset.1238468420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/18.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.2943730987 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 66885732 ps |
| CPU time | 5.95 seconds |
| Started | Oct 12 11:22:01 AM UTC 24 |
| Finished | Oct 12 11:22:08 AM UTC 24 |
| Peak memory | 248132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943730987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2943730987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/18.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.3701756881 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 9682555 ps |
| CPU time | 1.93 seconds |
| Started | Oct 12 11:21:58 AM UTC 24 |
| Finished | Oct 12 11:22:01 AM UTC 24 |
| Peak memory | 246792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701756881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3701756881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/18.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1407969019 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 1097654006 ps |
| CPU time | 23.33 seconds |
| Started | Oct 12 11:22:01 AM UTC 24 |
| Finished | Oct 12 11:22:26 AM UTC 24 |
| Peak memory | 258300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407969019 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_outstanding.1407969019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/18.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3627248865 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 1675321894 ps |
| CPU time | 111.53 seconds |
| Started | Oct 12 11:21:28 AM UTC 24 |
| Finished | Oct 12 11:23:22 AM UTC 24 |
| Peak memory | 267020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627248865 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors.3627248865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2290659521 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 50201833296 ps |
| CPU time | 1049.41 seconds |
| Started | Oct 12 11:21:17 AM UTC 24 |
| Finished | Oct 12 11:39:01 AM UTC 24 |
| Peak memory | 279952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290659521 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shad ow_reg_errors_with_csr_rw.2290659521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.979623270 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 4334240290 ps |
| CPU time | 27.7 seconds |
| Started | Oct 12 11:21:31 AM UTC 24 |
| Finished | Oct 12 11:22:01 AM UTC 24 |
| Peak memory | 260424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979623270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.979623270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/18.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3343472214 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 919596585 ps |
| CPU time | 11.47 seconds |
| Started | Oct 12 11:22:30 AM UTC 24 |
| Finished | Oct 12 11:22:43 AM UTC 24 |
| Peak memory | 250180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343472214 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_mem _rw_with_rand_reset.3343472214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/19.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.2486440023 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 88989145 ps |
| CPU time | 6.36 seconds |
| Started | Oct 12 11:22:27 AM UTC 24 |
| Finished | Oct 12 11:22:34 AM UTC 24 |
| Peak memory | 250108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486440023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2486440023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/19.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.1523250015 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 8991017 ps |
| CPU time | 2.03 seconds |
| Started | Oct 12 11:22:27 AM UTC 24 |
| Finished | Oct 12 11:22:30 AM UTC 24 |
| Peak memory | 248080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523250015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1523250015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/19.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1928237139 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 347648264 ps |
| CPU time | 13.78 seconds |
| Started | Oct 12 11:22:28 AM UTC 24 |
| Finished | Oct 12 11:22:43 AM UTC 24 |
| Peak memory | 258308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928237139 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_outstanding.1928237139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/19.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3990254900 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 17363787350 ps |
| CPU time | 357.17 seconds |
| Started | Oct 12 11:22:10 AM UTC 24 |
| Finished | Oct 12 11:28:12 AM UTC 24 |
| Peak memory | 283468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990254900 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors.3990254900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.3136422720 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 757506470 ps |
| CPU time | 14.83 seconds |
| Started | Oct 12 11:22:10 AM UTC 24 |
| Finished | Oct 12 11:22:26 AM UTC 24 |
| Peak memory | 260432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136422720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3136422720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/19.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.588520625 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 196933400 ps |
| CPU time | 4.77 seconds |
| Started | Oct 12 11:22:25 AM UTC 24 |
| Finished | Oct 12 11:22:31 AM UTC 24 |
| Peak memory | 248060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588520625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.588520625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/19.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_aliasing.836238455 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 7313073382 ps |
| CPU time | 140.55 seconds |
| Started | Oct 12 11:14:17 AM UTC 24 |
| Finished | Oct 12 11:16:41 AM UTC 24 |
| Peak memory | 250368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836238455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/al ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.836238455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2033921652 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 22799635816 ps |
| CPU time | 414.81 seconds |
| Started | Oct 12 11:13:49 AM UTC 24 |
| Finished | Oct 12 11:20:50 AM UTC 24 |
| Peak memory | 248136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033921652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2033921652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2286917360 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 72090103 ps |
| CPU time | 6.3 seconds |
| Started | Oct 12 11:13:33 AM UTC 24 |
| Finished | Oct 12 11:13:40 AM UTC 24 |
| Peak memory | 260356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286917360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2286917360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1828727429 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 61311412 ps |
| CPU time | 5.76 seconds |
| Started | Oct 12 11:15:24 AM UTC 24 |
| Finished | Oct 12 11:15:31 AM UTC 24 |
| Peak memory | 250444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828727429 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_mem_ rw_with_rand_reset.1828727429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_rw.2165280850 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 36038797 ps |
| CPU time | 6.36 seconds |
| Started | Oct 12 11:13:41 AM UTC 24 |
| Finished | Oct 12 11:13:48 AM UTC 24 |
| Peak memory | 250108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165280850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2165280850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_intr_test.4227376413 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 10238812 ps |
| CPU time | 1.98 seconds |
| Started | Oct 12 11:13:29 AM UTC 24 |
| Finished | Oct 12 11:13:32 AM UTC 24 |
| Peak memory | 246856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227376413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.4227376413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.825786383 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 504818177 ps |
| CPU time | 40.44 seconds |
| Started | Oct 12 11:15:16 AM UTC 24 |
| Finished | Oct 12 11:15:58 AM UTC 24 |
| Peak memory | 258500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825786383 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outstanding.825786383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3658117537 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 63457274655 ps |
| CPU time | 624.81 seconds |
| Started | Oct 12 11:11:25 AM UTC 24 |
| Finished | Oct 12 11:22:00 AM UTC 24 |
| Peak memory | 283268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658117537 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shado w_reg_errors_with_csr_rw.3658117537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_errors.3213546708 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 70837905 ps |
| CPU time | 5.53 seconds |
| Started | Oct 12 11:12:36 AM UTC 24 |
| Finished | Oct 12 11:12:43 AM UTC 24 |
| Peak memory | 264656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213546708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3213546708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.393565918 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 26670218 ps |
| CPU time | 2.05 seconds |
| Started | Oct 12 11:22:31 AM UTC 24 |
| Finished | Oct 12 11:22:35 AM UTC 24 |
| Peak memory | 248272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393565918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.393565918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/20.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.2458450796 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 18532723 ps |
| CPU time | 1.75 seconds |
| Started | Oct 12 11:22:31 AM UTC 24 |
| Finished | Oct 12 11:22:34 AM UTC 24 |
| Peak memory | 246856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458450796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2458450796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/21.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.1971578781 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 16210345 ps |
| CPU time | 1.83 seconds |
| Started | Oct 12 11:22:36 AM UTC 24 |
| Finished | Oct 12 11:22:39 AM UTC 24 |
| Peak memory | 246792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971578781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1971578781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/22.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.964524743 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 11657445 ps |
| CPU time | 2.1 seconds |
| Started | Oct 12 11:22:36 AM UTC 24 |
| Finished | Oct 12 11:22:39 AM UTC 24 |
| Peak memory | 248208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964524743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.964524743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/23.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.57248135 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 10282024 ps |
| CPU time | 1.93 seconds |
| Started | Oct 12 11:22:36 AM UTC 24 |
| Finished | Oct 12 11:22:39 AM UTC 24 |
| Peak memory | 244804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57248135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_ SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handle r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.57248135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/24.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.2828821933 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 12791149 ps |
| CPU time | 2.2 seconds |
| Started | Oct 12 11:22:40 AM UTC 24 |
| Finished | Oct 12 11:22:44 AM UTC 24 |
| Peak memory | 248208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828821933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.2828821933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/25.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.3980047554 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 22819680 ps |
| CPU time | 2.47 seconds |
| Started | Oct 12 11:22:40 AM UTC 24 |
| Finished | Oct 12 11:22:44 AM UTC 24 |
| Peak memory | 248008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980047554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3980047554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/26.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.462038815 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 14086702 ps |
| CPU time | 1.72 seconds |
| Started | Oct 12 11:22:40 AM UTC 24 |
| Finished | Oct 12 11:22:43 AM UTC 24 |
| Peak memory | 246856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462038815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.462038815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/27.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.2928806971 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 10745591 ps |
| CPU time | 2.39 seconds |
| Started | Oct 12 11:22:43 AM UTC 24 |
| Finished | Oct 12 11:22:47 AM UTC 24 |
| Peak memory | 246160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928806971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2928806971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/28.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.2798487709 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 15198027 ps |
| CPU time | 1.78 seconds |
| Started | Oct 12 11:22:44 AM UTC 24 |
| Finished | Oct 12 11:22:48 AM UTC 24 |
| Peak memory | 246792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798487709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2798487709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/29.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_aliasing.4215356628 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 1699691988 ps |
| CPU time | 121.24 seconds |
| Started | Oct 12 11:16:02 AM UTC 24 |
| Finished | Oct 12 11:18:06 AM UTC 24 |
| Peak memory | 250188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215356628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.4215356628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2250217039 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 3870679687 ps |
| CPU time | 246.22 seconds |
| Started | Oct 12 11:15:59 AM UTC 24 |
| Finished | Oct 12 11:20:10 AM UTC 24 |
| Peak memory | 248128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250217039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2250217039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1837505681 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 503651720 ps |
| CPU time | 10.64 seconds |
| Started | Oct 12 11:15:51 AM UTC 24 |
| Finished | Oct 12 11:16:04 AM UTC 24 |
| Peak memory | 260420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837505681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1837505681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1024073781 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 31780686 ps |
| CPU time | 6.18 seconds |
| Started | Oct 12 11:16:04 AM UTC 24 |
| Finished | Oct 12 11:16:12 AM UTC 24 |
| Peak memory | 266560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024073781 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_mem_ rw_with_rand_reset.1024073781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_rw.3594845581 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 95017277 ps |
| CPU time | 8.76 seconds |
| Started | Oct 12 11:15:51 AM UTC 24 |
| Finished | Oct 12 11:16:02 AM UTC 24 |
| Peak memory | 248060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594845581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3594845581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3478162535 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 136841222 ps |
| CPU time | 15.73 seconds |
| Started | Oct 12 11:16:02 AM UTC 24 |
| Finished | Oct 12 11:16:19 AM UTC 24 |
| Peak memory | 258300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478162535 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outstanding.3478162535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2535090017 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 4547497875 ps |
| CPU time | 155.64 seconds |
| Started | Oct 12 11:15:33 AM UTC 24 |
| Finished | Oct 12 11:18:11 AM UTC 24 |
| Peak memory | 277128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535090017 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_errors.2535090017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.855364708 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 8339561670 ps |
| CPU time | 325.24 seconds |
| Started | Oct 12 11:15:30 AM UTC 24 |
| Finished | Oct 12 11:21:00 AM UTC 24 |
| Peak memory | 277132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855364708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow _reg_errors_with_csr_rw.855364708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_errors.2909031847 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 95587203 ps |
| CPU time | 7.87 seconds |
| Started | Oct 12 11:15:41 AM UTC 24 |
| Finished | Oct 12 11:15:50 AM UTC 24 |
| Peak memory | 266704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909031847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2909031847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.996541636 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 10321731 ps |
| CPU time | 2 seconds |
| Started | Oct 12 11:22:45 AM UTC 24 |
| Finished | Oct 12 11:22:48 AM UTC 24 |
| Peak memory | 246856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996541636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.996541636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/30.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.2168904491 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 11412628 ps |
| CPU time | 1.68 seconds |
| Started | Oct 12 11:22:45 AM UTC 24 |
| Finished | Oct 12 11:22:48 AM UTC 24 |
| Peak memory | 246856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168904491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2168904491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/31.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.1547385749 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 7314711 ps |
| CPU time | 1.86 seconds |
| Started | Oct 12 11:22:45 AM UTC 24 |
| Finished | Oct 12 11:22:48 AM UTC 24 |
| Peak memory | 246856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547385749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1547385749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/32.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.3848332934 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 11300080 ps |
| CPU time | 1.78 seconds |
| Started | Oct 12 11:22:47 AM UTC 24 |
| Finished | Oct 12 11:22:50 AM UTC 24 |
| Peak memory | 244744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848332934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3848332934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/33.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.3511950176 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 10654304 ps |
| CPU time | 1.76 seconds |
| Started | Oct 12 11:22:48 AM UTC 24 |
| Finished | Oct 12 11:22:51 AM UTC 24 |
| Peak memory | 246856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511950176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3511950176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/34.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.1737787319 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 7956149 ps |
| CPU time | 1.66 seconds |
| Started | Oct 12 11:22:48 AM UTC 24 |
| Finished | Oct 12 11:22:51 AM UTC 24 |
| Peak memory | 246856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737787319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1737787319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/35.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.804794172 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 7635300 ps |
| CPU time | 1.77 seconds |
| Started | Oct 12 11:22:49 AM UTC 24 |
| Finished | Oct 12 11:22:52 AM UTC 24 |
| Peak memory | 246856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804794172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.804794172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/36.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.2965334949 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 39444623 ps |
| CPU time | 1.85 seconds |
| Started | Oct 12 11:22:49 AM UTC 24 |
| Finished | Oct 12 11:22:52 AM UTC 24 |
| Peak memory | 246856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965334949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2965334949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/37.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.1204695379 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 23336852 ps |
| CPU time | 1.83 seconds |
| Started | Oct 12 11:22:49 AM UTC 24 |
| Finished | Oct 12 11:22:52 AM UTC 24 |
| Peak memory | 246856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204695379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1204695379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/38.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.862836904 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 14658847 ps |
| CPU time | 1.68 seconds |
| Started | Oct 12 11:22:49 AM UTC 24 |
| Finished | Oct 12 11:22:52 AM UTC 24 |
| Peak memory | 246856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862836904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.862836904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/39.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_aliasing.718586058 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 1192751078 ps |
| CPU time | 187 seconds |
| Started | Oct 12 11:16:31 AM UTC 24 |
| Finished | Oct 12 11:19:41 AM UTC 24 |
| Peak memory | 250108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718586058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/al ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.718586058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.906772259 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 11925182516 ps |
| CPU time | 212.69 seconds |
| Started | Oct 12 11:16:29 AM UTC 24 |
| Finished | Oct 12 11:20:05 AM UTC 24 |
| Peak memory | 250440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906772259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/al ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.906772259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.4245488468 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 242815586 ps |
| CPU time | 6.47 seconds |
| Started | Oct 12 11:16:27 AM UTC 24 |
| Finished | Oct 12 11:16:34 AM UTC 24 |
| Peak memory | 260344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245488468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.4245488468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1614821880 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 93338142 ps |
| CPU time | 8.38 seconds |
| Started | Oct 12 11:16:35 AM UTC 24 |
| Finished | Oct 12 11:16:45 AM UTC 24 |
| Peak memory | 250256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614821880 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_mem_ rw_with_rand_reset.1614821880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_rw.4092001148 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 59643954 ps |
| CPU time | 5.54 seconds |
| Started | Oct 12 11:16:28 AM UTC 24 |
| Finished | Oct 12 11:16:35 AM UTC 24 |
| Peak memory | 248136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092001148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.4092001148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_intr_test.1529157726 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 9026116 ps |
| CPU time | 1.86 seconds |
| Started | Oct 12 11:16:27 AM UTC 24 |
| Finished | Oct 12 11:16:30 AM UTC 24 |
| Peak memory | 244744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529157726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1529157726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2998563177 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 1047338026 ps |
| CPU time | 22.21 seconds |
| Started | Oct 12 11:16:35 AM UTC 24 |
| Finished | Oct 12 11:16:59 AM UTC 24 |
| Peak memory | 250104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998563177 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outstanding.2998563177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3615103588 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 3335274141 ps |
| CPU time | 224.02 seconds |
| Started | Oct 12 11:16:12 AM UTC 24 |
| Finished | Oct 12 11:20:00 AM UTC 24 |
| Peak memory | 277136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615103588 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors.3615103588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.732262868 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 5720134401 ps |
| CPU time | 763 seconds |
| Started | Oct 12 11:16:11 AM UTC 24 |
| Finished | Oct 12 11:29:05 AM UTC 24 |
| Peak memory | 277124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732262868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow _reg_errors_with_csr_rw.732262868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_errors.576832212 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 700942807 ps |
| CPU time | 10.94 seconds |
| Started | Oct 12 11:16:13 AM UTC 24 |
| Finished | Oct 12 11:16:25 AM UTC 24 |
| Peak memory | 264656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576832212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.576832212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1378894344 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 56865036 ps |
| CPU time | 3.06 seconds |
| Started | Oct 12 11:16:20 AM UTC 24 |
| Finished | Oct 12 11:16:24 AM UTC 24 |
| Peak memory | 248268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378894344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 1/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1378894344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.2553269458 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 20985555 ps |
| CPU time | 1.85 seconds |
| Started | Oct 12 11:22:50 AM UTC 24 |
| Finished | Oct 12 11:22:53 AM UTC 24 |
| Peak memory | 246856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553269458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2553269458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/40.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.4256336645 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 7241460 ps |
| CPU time | 1.88 seconds |
| Started | Oct 12 11:22:51 AM UTC 24 |
| Finished | Oct 12 11:22:54 AM UTC 24 |
| Peak memory | 246728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256336645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.4256336645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/41.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.2566098560 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 15099168 ps |
| CPU time | 1.96 seconds |
| Started | Oct 12 11:22:52 AM UTC 24 |
| Finished | Oct 12 11:22:54 AM UTC 24 |
| Peak memory | 244744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566098560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2566098560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/42.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.480019192 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 16303041 ps |
| CPU time | 1.66 seconds |
| Started | Oct 12 11:22:53 AM UTC 24 |
| Finished | Oct 12 11:22:55 AM UTC 24 |
| Peak memory | 246724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480019192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.480019192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/43.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.3695479867 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 8077285 ps |
| CPU time | 1.93 seconds |
| Started | Oct 12 11:22:53 AM UTC 24 |
| Finished | Oct 12 11:22:56 AM UTC 24 |
| Peak memory | 246856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695479867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3695479867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/44.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.539467986 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 11020745 ps |
| CPU time | 1.73 seconds |
| Started | Oct 12 11:22:53 AM UTC 24 |
| Finished | Oct 12 11:22:56 AM UTC 24 |
| Peak memory | 246852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539467986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.539467986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/45.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.166813847 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 9002692 ps |
| CPU time | 1.88 seconds |
| Started | Oct 12 11:22:53 AM UTC 24 |
| Finished | Oct 12 11:22:56 AM UTC 24 |
| Peak memory | 246792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166813847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.166813847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/46.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.4054818705 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 10486274 ps |
| CPU time | 1.75 seconds |
| Started | Oct 12 11:22:54 AM UTC 24 |
| Finished | Oct 12 11:22:57 AM UTC 24 |
| Peak memory | 246856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054818705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.4054818705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/47.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.967915905 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 48916050 ps |
| CPU time | 3.59 seconds |
| Started | Oct 12 11:22:55 AM UTC 24 |
| Finished | Oct 12 11:22:59 AM UTC 24 |
| Peak memory | 246160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967915905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.967915905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/48.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.2360523423 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 49604081 ps |
| CPU time | 1.85 seconds |
| Started | Oct 12 11:22:56 AM UTC 24 |
| Finished | Oct 12 11:22:59 AM UTC 24 |
| Peak memory | 246856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360523423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2360523423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/49.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3038028869 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 27779027 ps |
| CPU time | 5.8 seconds |
| Started | Oct 12 11:17:08 AM UTC 24 |
| Finished | Oct 12 11:17:15 AM UTC 24 |
| Peak memory | 250180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038028869 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_mem_ rw_with_rand_reset.3038028869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/5.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_rw.538283897 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 34018568 ps |
| CPU time | 6.92 seconds |
| Started | Oct 12 11:17:03 AM UTC 24 |
| Finished | Oct 12 11:17:11 AM UTC 24 |
| Peak memory | 248060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538283897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.538283897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/5.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_intr_test.4094056581 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 14636547 ps |
| CPU time | 1.66 seconds |
| Started | Oct 12 11:17:00 AM UTC 24 |
| Finished | Oct 12 11:17:02 AM UTC 24 |
| Peak memory | 246856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094056581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.4094056581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/5.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1288758204 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 3254213580 ps |
| CPU time | 38.55 seconds |
| Started | Oct 12 11:17:07 AM UTC 24 |
| Finished | Oct 12 11:17:47 AM UTC 24 |
| Peak memory | 258568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288758204 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outstanding.1288758204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/5.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1480649578 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 2401062689 ps |
| CPU time | 182.07 seconds |
| Started | Oct 12 11:16:41 AM UTC 24 |
| Finished | Oct 12 11:19:47 AM UTC 24 |
| Peak memory | 277128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480649578 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors.1480649578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3441070474 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 8218821564 ps |
| CPU time | 367.3 seconds |
| Started | Oct 12 11:16:39 AM UTC 24 |
| Finished | Oct 12 11:22:52 AM UTC 24 |
| Peak memory | 283264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441070474 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shado w_reg_errors_with_csr_rw.3441070474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_errors.3375956118 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 268534089 ps |
| CPU time | 20.17 seconds |
| Started | Oct 12 11:16:45 AM UTC 24 |
| Finished | Oct 12 11:17:07 AM UTC 24 |
| Peak memory | 260560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375956118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3375956118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/5.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3201784773 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 213999476 ps |
| CPU time | 16.86 seconds |
| Started | Oct 12 11:17:43 AM UTC 24 |
| Finished | Oct 12 11:18:01 AM UTC 24 |
| Peak memory | 262468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201784773 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_mem_ rw_with_rand_reset.3201784773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/6.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_rw.1888489134 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 55792468 ps |
| CPU time | 5.42 seconds |
| Started | Oct 12 11:17:38 AM UTC 24 |
| Finished | Oct 12 11:17:44 AM UTC 24 |
| Peak memory | 248260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888489134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1888489134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/6.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_intr_test.2821263528 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 11037537 ps |
| CPU time | 2.33 seconds |
| Started | Oct 12 11:17:34 AM UTC 24 |
| Finished | Oct 12 11:17:37 AM UTC 24 |
| Peak memory | 246032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821263528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2821263528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/6.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.807671666 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 2534266652 ps |
| CPU time | 55.13 seconds |
| Started | Oct 12 11:17:41 AM UTC 24 |
| Finished | Oct 12 11:18:38 AM UTC 24 |
| Peak memory | 258432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807671666 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outstanding.807671666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/6.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_errors.3012204524 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 220489092 ps |
| CPU time | 10.62 seconds |
| Started | Oct 12 11:17:31 AM UTC 24 |
| Finished | Oct 12 11:17:42 AM UTC 24 |
| Peak memory | 260360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012204524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3012204524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/6.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3501426088 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 38413615 ps |
| CPU time | 6.76 seconds |
| Started | Oct 12 11:18:08 AM UTC 24 |
| Finished | Oct 12 11:18:16 AM UTC 24 |
| Peak memory | 266572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501426088 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_mem_ rw_with_rand_reset.3501426088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/7.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_rw.4282737135 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 19873146 ps |
| CPU time | 4.43 seconds |
| Started | Oct 12 11:18:07 AM UTC 24 |
| Finished | Oct 12 11:18:12 AM UTC 24 |
| Peak memory | 250176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282737135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.4282737135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/7.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_intr_test.4064485345 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 7427265 ps |
| CPU time | 1.74 seconds |
| Started | Oct 12 11:18:05 AM UTC 24 |
| Finished | Oct 12 11:18:08 AM UTC 24 |
| Peak memory | 246728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064485345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.4064485345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/7.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.823448767 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 1547372095 ps |
| CPU time | 22.26 seconds |
| Started | Oct 12 11:18:08 AM UTC 24 |
| Finished | Oct 12 11:18:31 AM UTC 24 |
| Peak memory | 260340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823448767 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outstanding.823448767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/7.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3396669007 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 8987960897 ps |
| CPU time | 366.87 seconds |
| Started | Oct 12 11:17:43 AM UTC 24 |
| Finished | Oct 12 11:23:56 AM UTC 24 |
| Peak memory | 277196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396669007 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shado w_reg_errors_with_csr_rw.3396669007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_errors.2236728831 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 279832256 ps |
| CPU time | 21.68 seconds |
| Started | Oct 12 11:17:47 AM UTC 24 |
| Finished | Oct 12 11:18:10 AM UTC 24 |
| Peak memory | 260360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236728831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2236728831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/7.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_intg_err.666844104 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 112891387 ps |
| CPU time | 3.24 seconds |
| Started | Oct 12 11:18:02 AM UTC 24 |
| Finished | Oct 12 11:18:07 AM UTC 24 |
| Peak memory | 248132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666844104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.666844104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/7.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1192831586 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 77819245 ps |
| CPU time | 9.23 seconds |
| Started | Oct 12 11:18:20 AM UTC 24 |
| Finished | Oct 12 11:18:30 AM UTC 24 |
| Peak memory | 250256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192831586 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_mem_ rw_with_rand_reset.1192831586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/8.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_rw.2795390881 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 68010699 ps |
| CPU time | 6.27 seconds |
| Started | Oct 12 11:18:17 AM UTC 24 |
| Finished | Oct 12 11:18:25 AM UTC 24 |
| Peak memory | 248060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795390881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2795390881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/8.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_intr_test.987101222 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 8349265 ps |
| CPU time | 1.86 seconds |
| Started | Oct 12 11:18:16 AM UTC 24 |
| Finished | Oct 12 11:18:19 AM UTC 24 |
| Peak memory | 246848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987101222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.987101222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/8.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1549004181 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 511852484 ps |
| CPU time | 44.39 seconds |
| Started | Oct 12 11:18:18 AM UTC 24 |
| Finished | Oct 12 11:19:04 AM UTC 24 |
| Peak memory | 258296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549004181 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outstanding.1549004181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/8.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.187090874 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 10612345347 ps |
| CPU time | 221.99 seconds |
| Started | Oct 12 11:18:11 AM UTC 24 |
| Finished | Oct 12 11:21:57 AM UTC 24 |
| Peak memory | 277332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187090874 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors.187090874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3362508107 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 4791041841 ps |
| CPU time | 704.19 seconds |
| Started | Oct 12 11:18:09 AM UTC 24 |
| Finished | Oct 12 11:30:03 AM UTC 24 |
| Peak memory | 277204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362508107 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shado w_reg_errors_with_csr_rw.3362508107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_errors.2291627129 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 424537377 ps |
| CPU time | 9.74 seconds |
| Started | Oct 12 11:18:12 AM UTC 24 |
| Finished | Oct 12 11:18:23 AM UTC 24 |
| Peak memory | 260360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291627129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2291627129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/8.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_intg_err.56676406 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 159648780 ps |
| CPU time | 3.44 seconds |
| Started | Oct 12 11:18:13 AM UTC 24 |
| Finished | Oct 12 11:18:18 AM UTC 24 |
| Peak memory | 248260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56676406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.56676406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/8.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.762117873 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 110543499 ps |
| CPU time | 5.81 seconds |
| Started | Oct 12 11:18:37 AM UTC 24 |
| Finished | Oct 12 11:18:43 AM UTC 24 |
| Peak memory | 250248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762117873 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_mem_r w_with_rand_reset.762117873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/9.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_rw.1101028888 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 299735175 ps |
| CPU time | 6.82 seconds |
| Started | Oct 12 11:18:33 AM UTC 24 |
| Finished | Oct 12 11:18:41 AM UTC 24 |
| Peak memory | 248132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101028888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1101028888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/9.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2630921749 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 318736780 ps |
| CPU time | 23.94 seconds |
| Started | Oct 12 11:18:35 AM UTC 24 |
| Finished | Oct 12 11:19:01 AM UTC 24 |
| Peak memory | 260344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630921749 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outstanding.2630921749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/9.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.805169365 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 16703951186 ps |
| CPU time | 671.27 seconds |
| Started | Oct 12 11:18:24 AM UTC 24 |
| Finished | Oct 12 11:29:45 AM UTC 24 |
| Peak memory | 279176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805169365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow _reg_errors_with_csr_rw.805169365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_errors.2302546991 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 46911114 ps |
| CPU time | 7.62 seconds |
| Started | Oct 12 11:18:26 AM UTC 24 |
| Finished | Oct 12 11:18:35 AM UTC 24 |
| Peak memory | 260436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302546991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.2302546991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/9.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy.1811152962 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 140043849911 ps |
| CPU time | 2185.1 seconds |
| Started | Oct 12 09:03:02 AM UTC 24 |
| Finished | Oct 12 09:39:53 AM UTC 24 |
| Peak memory | 283640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811152962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1811152962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_alert_accum.902904286 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 26427422844 ps |
| CPU time | 214.08 seconds |
| Started | Oct 12 09:03:02 AM UTC 24 |
| Finished | Oct 12 09:06:40 AM UTC 24 |
| Peak memory | 267232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902904286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.902904286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_intr_timeout.1729979029 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 92809773 ps |
| CPU time | 3.91 seconds |
| Started | Oct 12 09:03:02 AM UTC 24 |
| Finished | Oct 12 09:03:07 AM UTC 24 |
| Peak memory | 250588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729979029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1729979029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg.2308102691 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 16728756498 ps |
| CPU time | 1873.15 seconds |
| Started | Oct 12 09:03:02 AM UTC 24 |
| Finished | Oct 12 09:34:38 AM UTC 24 |
| Peak memory | 300004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308102691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2308102691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/0.alert_handler_ping_timeout.202646118 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10025796243 ps |
| CPU time | 164.21 seconds |
| Started | Oct 12 09:03:02 AM UTC 24 |
| Finished | Oct 12 09:05:49 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202646118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.202646118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_classes.3109119576 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4486359971 ps |
| CPU time | 45.13 seconds |
| Started | Oct 12 09:03:02 AM UTC 24 |
| Finished | Oct 12 09:03:49 AM UTC 24 |
| Peak memory | 267228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109119576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3109119576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/0.alert_handler_sig_int_fail.420096311 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 676742054 ps |
| CPU time | 11 seconds |
| Started | Oct 12 09:03:02 AM UTC 24 |
| Finished | Oct 12 09:03:14 AM UTC 24 |
| Peak memory | 260888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420096311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.420096311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all.1785191551 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 137595667082 ps |
| CPU time | 1488.83 seconds |
| Started | Oct 12 09:03:02 AM UTC 24 |
| Finished | Oct 12 09:28:09 AM UTC 24 |
| Peak memory | 299812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785191551 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_stress_all.1785191551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/0.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy_stress.3479225066 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 588660351 ps |
| CPU time | 15.26 seconds |
| Started | Oct 12 09:03:07 AM UTC 24 |
| Finished | Oct 12 09:03:23 AM UTC 24 |
| Peak memory | 260840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479225066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3479225066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_intr_timeout.2838437645 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 4370181385 ps |
| CPU time | 54.38 seconds |
| Started | Oct 12 09:03:06 AM UTC 24 |
| Finished | Oct 12 09:04:02 AM UTC 24 |
| Peak memory | 267036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838437645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2838437645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg.3110804657 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 40498613013 ps |
| CPU time | 1724.42 seconds |
| Started | Oct 12 09:03:07 AM UTC 24 |
| Finished | Oct 12 09:32:10 AM UTC 24 |
| Peak memory | 283428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110804657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3110804657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg_stub_clk.940766901 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 46161609812 ps |
| CPU time | 2349.91 seconds |
| Started | Oct 12 09:03:07 AM UTC 24 |
| Finished | Oct 12 09:42:44 AM UTC 24 |
| Peak memory | 293884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940766901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.940766901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/1.alert_handler_ping_timeout.2599319143 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5716550969 ps |
| CPU time | 220.19 seconds |
| Started | Oct 12 09:03:07 AM UTC 24 |
| Finished | Oct 12 09:06:50 AM UTC 24 |
| Peak memory | 261092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599319143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2599319143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_alerts.122243602 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 1121597858 ps |
| CPU time | 14.59 seconds |
| Started | Oct 12 09:03:06 AM UTC 24 |
| Finished | Oct 12 09:03:22 AM UTC 24 |
| Peak memory | 261120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122243602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.122243602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_classes.612137637 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3253149029 ps |
| CPU time | 52.17 seconds |
| Started | Oct 12 09:03:06 AM UTC 24 |
| Finished | Oct 12 09:04:00 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612137637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.612137637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/1.alert_handler_sec_cm.1698590968 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1006707792 ps |
| CPU time | 35.19 seconds |
| Started | Oct 12 09:03:08 AM UTC 24 |
| Finished | Oct 12 09:03:45 AM UTC 24 |
| Peak memory | 295052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698590968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1698590968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all_with_rand_reset.92745484 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1414794182 ps |
| CPU time | 132.5 seconds |
| Started | Oct 12 09:03:07 AM UTC 24 |
| Finished | Oct 12 09:05:22 AM UTC 24 |
| Peak memory | 277544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=92745484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.aler t_handler_stress_all_with_rand_reset.92745484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/10.alert_handler_alert_accum_saturation.3716755157 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 178255051 ps |
| CPU time | 7.13 seconds |
| Started | Oct 12 09:12:49 AM UTC 24 |
| Finished | Oct 12 09:12:57 AM UTC 24 |
| Peak memory | 261040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716755157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3716755157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/10.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy.2625806160 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 128234323801 ps |
| CPU time | 1957.88 seconds |
| Started | Oct 12 09:11:25 AM UTC 24 |
| Finished | Oct 12 09:44:26 AM UTC 24 |
| Peak memory | 283428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625806160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2625806160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/10.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy_stress.2690821509 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 3305369189 ps |
| CPU time | 18.3 seconds |
| Started | Oct 12 09:12:28 AM UTC 24 |
| Finished | Oct 12 09:12:48 AM UTC 24 |
| Peak memory | 261100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690821509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2690821509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/10.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_alert_accum.227081209 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 3294137066 ps |
| CPU time | 176.27 seconds |
| Started | Oct 12 09:11:17 AM UTC 24 |
| Finished | Oct 12 09:14:16 AM UTC 24 |
| Peak memory | 267040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227081209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.227081209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/10.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_intr_timeout.374343309 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 418225898 ps |
| CPU time | 6.95 seconds |
| Started | Oct 12 09:11:12 AM UTC 24 |
| Finished | Oct 12 09:11:20 AM UTC 24 |
| Peak memory | 260868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374343309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.374343309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/10.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg_stub_clk.2875234865 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 24885852141 ps |
| CPU time | 1580.76 seconds |
| Started | Oct 12 09:11:54 AM UTC 24 |
| Finished | Oct 12 09:38:33 AM UTC 24 |
| Peak memory | 283700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875234865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2875234865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/10.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/10.alert_handler_ping_timeout.1986880023 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 7195042496 ps |
| CPU time | 259.18 seconds |
| Started | Oct 12 09:11:32 AM UTC 24 |
| Finished | Oct 12 09:15:55 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986880023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1986880023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_alerts.1767382234 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 615585575 ps |
| CPU time | 40.09 seconds |
| Started | Oct 12 09:10:42 AM UTC 24 |
| Finished | Oct 12 09:11:24 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767382234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1767382234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/10.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_classes.3139224826 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 848727348 ps |
| CPU time | 22.55 seconds |
| Started | Oct 12 09:10:46 AM UTC 24 |
| Finished | Oct 12 09:11:11 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139224826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3139224826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/10.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/10.alert_handler_sig_int_fail.3095978344 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 271518149 ps |
| CPU time | 30.37 seconds |
| Started | Oct 12 09:11:21 AM UTC 24 |
| Finished | Oct 12 09:11:53 AM UTC 24 |
| Peak memory | 261024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095978344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3095978344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/10.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/10.alert_handler_smoke.2575247303 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 654307028 ps |
| CPU time | 55.99 seconds |
| Started | Oct 12 09:10:41 AM UTC 24 |
| Finished | Oct 12 09:11:39 AM UTC 24 |
| Peak memory | 266908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575247303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2575247303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/10.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy.793796453 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 39232769262 ps |
| CPU time | 1107.28 seconds |
| Started | Oct 12 09:13:32 AM UTC 24 |
| Finished | Oct 12 09:32:13 AM UTC 24 |
| Peak memory | 283436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793796453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.793796453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/11.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy_stress.2003541794 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 570251930 ps |
| CPU time | 21.77 seconds |
| Started | Oct 12 09:14:17 AM UTC 24 |
| Finished | Oct 12 09:14:40 AM UTC 24 |
| Peak memory | 260764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003541794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2003541794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/11.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_alert_accum.2917597157 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 5331144179 ps |
| CPU time | 150.4 seconds |
| Started | Oct 12 09:13:26 AM UTC 24 |
| Finished | Oct 12 09:15:59 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917597157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2917597157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/11.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_intr_timeout.2793243634 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 68301529 ps |
| CPU time | 7.54 seconds |
| Started | Oct 12 09:13:21 AM UTC 24 |
| Finished | Oct 12 09:13:29 AM UTC 24 |
| Peak memory | 262876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793243634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2793243634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/11.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg.4181526009 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 72408203219 ps |
| CPU time | 1493.16 seconds |
| Started | Oct 12 09:13:34 AM UTC 24 |
| Finished | Oct 12 09:38:45 AM UTC 24 |
| Peak memory | 300088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181526009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.4181526009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/11.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg_stub_clk.3714184380 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 9339908371 ps |
| CPU time | 1181.57 seconds |
| Started | Oct 12 09:13:53 AM UTC 24 |
| Finished | Oct 12 09:33:50 AM UTC 24 |
| Peak memory | 297772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714184380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3714184380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/11.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/11.alert_handler_ping_timeout.1444661283 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 106615264517 ps |
| CPU time | 303.36 seconds |
| Started | Oct 12 09:13:32 AM UTC 24 |
| Finished | Oct 12 09:18:40 AM UTC 24 |
| Peak memory | 260904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444661283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1444661283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_alerts.3982199019 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 568929962 ps |
| CPU time | 38.13 seconds |
| Started | Oct 12 09:13:13 AM UTC 24 |
| Finished | Oct 12 09:13:52 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982199019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3982199019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/11.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_classes.3723035602 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 115088810 ps |
| CPU time | 6.26 seconds |
| Started | Oct 12 09:13:17 AM UTC 24 |
| Finished | Oct 12 09:13:24 AM UTC 24 |
| Peak memory | 264852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723035602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3723035602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/11.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/11.alert_handler_sig_int_fail.1523148392 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 601966303 ps |
| CPU time | 49.91 seconds |
| Started | Oct 12 09:13:30 AM UTC 24 |
| Finished | Oct 12 09:14:21 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523148392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1523148392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/11.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/11.alert_handler_smoke.138841806 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 1370687860 ps |
| CPU time | 21.08 seconds |
| Started | Oct 12 09:13:12 AM UTC 24 |
| Finished | Oct 12 09:13:34 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138841806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.138841806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/11.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all.523536550 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 78382201314 ps |
| CPU time | 3523.42 seconds |
| Started | Oct 12 09:14:22 AM UTC 24 |
| Finished | Oct 12 10:13:47 AM UTC 24 |
| Peak memory | 318764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523536550 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_stress_all.523536550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/11.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/12.alert_handler_alert_accum_saturation.3498274442 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 49752562 ps |
| CPU time | 3.81 seconds |
| Started | Oct 12 09:17:10 AM UTC 24 |
| Finished | Oct 12 09:17:16 AM UTC 24 |
| Peak memory | 260968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498274442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3498274442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/12.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy_stress.2650560148 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 543487122 ps |
| CPU time | 20.07 seconds |
| Started | Oct 12 09:16:58 AM UTC 24 |
| Finished | Oct 12 09:17:19 AM UTC 24 |
| Peak memory | 260764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650560148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2650560148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/12.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_alert_accum.3843765384 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 1141927697 ps |
| CPU time | 97.99 seconds |
| Started | Oct 12 09:15:56 AM UTC 24 |
| Finished | Oct 12 09:17:36 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843765384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3843765384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/12.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_intr_timeout.2176461500 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1162411437 ps |
| CPU time | 74.35 seconds |
| Started | Oct 12 09:15:42 AM UTC 24 |
| Finished | Oct 12 09:16:58 AM UTC 24 |
| Peak memory | 260752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176461500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2176461500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/12.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg_stub_clk.3821662029 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 217041456567 ps |
| CPU time | 2799.38 seconds |
| Started | Oct 12 09:16:37 AM UTC 24 |
| Finished | Oct 12 10:03:48 AM UTC 24 |
| Peak memory | 295988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821662029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3821662029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/12.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_alerts.2768859817 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 1700982516 ps |
| CPU time | 55.06 seconds |
| Started | Oct 12 09:15:15 AM UTC 24 |
| Finished | Oct 12 09:16:12 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768859817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2768859817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/12.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_classes.1215138023 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1057886829 ps |
| CPU time | 79.07 seconds |
| Started | Oct 12 09:15:15 AM UTC 24 |
| Finished | Oct 12 09:16:36 AM UTC 24 |
| Peak memory | 267164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215138023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1215138023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/12.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/12.alert_handler_sig_int_fail.3507730098 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 1260360496 ps |
| CPU time | 29 seconds |
| Started | Oct 12 09:16:00 AM UTC 24 |
| Finished | Oct 12 09:16:31 AM UTC 24 |
| Peak memory | 260760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507730098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3507730098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/12.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/12.alert_handler_smoke.3150769040 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 3598230192 ps |
| CPU time | 48.72 seconds |
| Started | Oct 12 09:14:50 AM UTC 24 |
| Finished | Oct 12 09:15:41 AM UTC 24 |
| Peak memory | 261156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150769040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3150769040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/12.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all.3433965216 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 21233946395 ps |
| CPU time | 222.02 seconds |
| Started | Oct 12 09:17:00 AM UTC 24 |
| Finished | Oct 12 09:20:45 AM UTC 24 |
| Peak memory | 267236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433965216 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_stress_all.3433965216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/12.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/13.alert_handler_alert_accum_saturation.2554695944 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 21667794 ps |
| CPU time | 3.85 seconds |
| Started | Oct 12 09:19:16 AM UTC 24 |
| Finished | Oct 12 09:19:21 AM UTC 24 |
| Peak memory | 260976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554695944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2554695944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/13.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy.3356645460 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 118328163625 ps |
| CPU time | 2106.1 seconds |
| Started | Oct 12 09:18:07 AM UTC 24 |
| Finished | Oct 12 09:53:36 AM UTC 24 |
| Peak memory | 293672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356645460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3356645460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/13.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy_stress.662411055 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 780493798 ps |
| CPU time | 20.16 seconds |
| Started | Oct 12 09:19:11 AM UTC 24 |
| Finished | Oct 12 09:19:33 AM UTC 24 |
| Peak memory | 261032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662411055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.662411055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/13.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_alert_accum.1794704797 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 44956243682 ps |
| CPU time | 247.93 seconds |
| Started | Oct 12 09:17:57 AM UTC 24 |
| Finished | Oct 12 09:22:09 AM UTC 24 |
| Peak memory | 267228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794704797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1794704797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/13.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_intr_timeout.521262677 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1773979590 ps |
| CPU time | 54.24 seconds |
| Started | Oct 12 09:17:48 AM UTC 24 |
| Finished | Oct 12 09:18:44 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521262677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.521262677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/13.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg.2268901457 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 19471556623 ps |
| CPU time | 1246.92 seconds |
| Started | Oct 12 09:18:41 AM UTC 24 |
| Finished | Oct 12 09:39:43 AM UTC 24 |
| Peak memory | 277272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268901457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2268901457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/13.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg_stub_clk.2793894355 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 422081870839 ps |
| CPU time | 2761.41 seconds |
| Started | Oct 12 09:18:45 AM UTC 24 |
| Finished | Oct 12 10:05:19 AM UTC 24 |
| Peak memory | 283432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793894355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2793894355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/13.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_alerts.3180910312 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1036143674 ps |
| CPU time | 91.05 seconds |
| Started | Oct 12 09:17:38 AM UTC 24 |
| Finished | Oct 12 09:19:11 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180910312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3180910312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/13.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_classes.1413243511 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 171535832 ps |
| CPU time | 17.52 seconds |
| Started | Oct 12 09:17:47 AM UTC 24 |
| Finished | Oct 12 09:18:06 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413243511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1413243511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/13.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/13.alert_handler_sig_int_fail.3365313472 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 305185555 ps |
| CPU time | 19.18 seconds |
| Started | Oct 12 09:17:59 AM UTC 24 |
| Finished | Oct 12 09:18:19 AM UTC 24 |
| Peak memory | 266904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365313472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3365313472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/13.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/13.alert_handler_smoke.2912777180 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 568136018 ps |
| CPU time | 34.26 seconds |
| Started | Oct 12 09:17:20 AM UTC 24 |
| Finished | Oct 12 09:17:56 AM UTC 24 |
| Peak memory | 266908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912777180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2912777180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/13.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/14.alert_handler_alert_accum_saturation.2525680393 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 39973198 ps |
| CPU time | 3.37 seconds |
| Started | Oct 12 09:21:32 AM UTC 24 |
| Finished | Oct 12 09:21:36 AM UTC 24 |
| Peak memory | 260968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525680393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2525680393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/14.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy_stress.1966947302 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 516980759 ps |
| CPU time | 16.53 seconds |
| Started | Oct 12 09:21:19 AM UTC 24 |
| Finished | Oct 12 09:21:37 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966947302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1966947302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/14.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_alert_accum.1066400127 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 3933210440 ps |
| CPU time | 163.03 seconds |
| Started | Oct 12 09:20:36 AM UTC 24 |
| Finished | Oct 12 09:23:22 AM UTC 24 |
| Peak memory | 267040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066400127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1066400127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/14.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_intr_timeout.2145563400 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 469798524 ps |
| CPU time | 34.64 seconds |
| Started | Oct 12 09:20:24 AM UTC 24 |
| Finished | Oct 12 09:21:01 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145563400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2145563400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/14.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg.3464175806 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 11667963736 ps |
| CPU time | 1274.94 seconds |
| Started | Oct 12 09:20:59 AM UTC 24 |
| Finished | Oct 12 09:42:29 AM UTC 24 |
| Peak memory | 283452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464175806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3464175806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/14.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg_stub_clk.647366014 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 127843437430 ps |
| CPU time | 1735.06 seconds |
| Started | Oct 12 09:21:02 AM UTC 24 |
| Finished | Oct 12 09:50:17 AM UTC 24 |
| Peak memory | 279352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647366014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.647366014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/14.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/14.alert_handler_ping_timeout.425554726 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 38124286553 ps |
| CPU time | 604.74 seconds |
| Started | Oct 12 09:20:52 AM UTC 24 |
| Finished | Oct 12 09:31:04 AM UTC 24 |
| Peak memory | 260900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425554726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.425554726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/14.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_alerts.3873304470 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 98797949 ps |
| CPU time | 13.95 seconds |
| Started | Oct 12 09:20:19 AM UTC 24 |
| Finished | Oct 12 09:20:34 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873304470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3873304470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/14.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_classes.2034764524 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 481831687 ps |
| CPU time | 51.65 seconds |
| Started | Oct 12 09:20:24 AM UTC 24 |
| Finished | Oct 12 09:21:18 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034764524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2034764524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/14.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/14.alert_handler_sig_int_fail.1368698234 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 583118346 ps |
| CPU time | 10.05 seconds |
| Started | Oct 12 09:20:47 AM UTC 24 |
| Finished | Oct 12 09:20:58 AM UTC 24 |
| Peak memory | 261028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368698234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1368698234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/14.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/14.alert_handler_smoke.1754804126 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1439643649 ps |
| CPU time | 48.42 seconds |
| Started | Oct 12 09:19:33 AM UTC 24 |
| Finished | Oct 12 09:20:23 AM UTC 24 |
| Peak memory | 267172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754804126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1754804126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/14.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all.1115334361 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 2260986325 ps |
| CPU time | 205.08 seconds |
| Started | Oct 12 09:21:32 AM UTC 24 |
| Finished | Oct 12 09:25:00 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115334361 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_stress_all.1115334361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/14.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all_with_rand_reset.1845872521 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2713111739 ps |
| CPU time | 221.2 seconds |
| Started | Oct 12 09:21:37 AM UTC 24 |
| Finished | Oct 12 09:25:22 AM UTC 24 |
| Peak memory | 277404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1845872521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.a lert_handler_stress_all_with_rand_reset.1845872521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/14.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/15.alert_handler_alert_accum_saturation.1051126176 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 89296969 ps |
| CPU time | 4.79 seconds |
| Started | Oct 12 09:24:00 AM UTC 24 |
| Finished | Oct 12 09:24:06 AM UTC 24 |
| Peak memory | 261040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051126176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1051126176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/15.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy.1707421183 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 13332844607 ps |
| CPU time | 837.48 seconds |
| Started | Oct 12 09:23:08 AM UTC 24 |
| Finished | Oct 12 09:37:16 AM UTC 24 |
| Peak memory | 283444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707421183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1707421183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/15.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy_stress.2435761695 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 3820939853 ps |
| CPU time | 20.79 seconds |
| Started | Oct 12 09:23:53 AM UTC 24 |
| Finished | Oct 12 09:24:15 AM UTC 24 |
| Peak memory | 261092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435761695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2435761695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/15.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_alert_accum.680150772 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 951018468 ps |
| CPU time | 42.81 seconds |
| Started | Oct 12 09:22:29 AM UTC 24 |
| Finished | Oct 12 09:23:13 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680150772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.680150772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/15.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_intr_timeout.835716659 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 159713811 ps |
| CPU time | 15.35 seconds |
| Started | Oct 12 09:22:11 AM UTC 24 |
| Finished | Oct 12 09:22:27 AM UTC 24 |
| Peak memory | 260760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835716659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.835716659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/15.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg_stub_clk.2373682867 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 15279256916 ps |
| CPU time | 1327.1 seconds |
| Started | Oct 12 09:23:33 AM UTC 24 |
| Finished | Oct 12 09:45:56 AM UTC 24 |
| Peak memory | 293748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373682867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2373682867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/15.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/15.alert_handler_ping_timeout.1380039803 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 20954625694 ps |
| CPU time | 339.08 seconds |
| Started | Oct 12 09:23:14 AM UTC 24 |
| Finished | Oct 12 09:28:57 AM UTC 24 |
| Peak memory | 260840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380039803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1380039803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/15.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_alerts.3418379845 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 95209999 ps |
| CPU time | 5.35 seconds |
| Started | Oct 12 09:21:50 AM UTC 24 |
| Finished | Oct 12 09:21:57 AM UTC 24 |
| Peak memory | 262876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418379845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3418379845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/15.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_classes.639997725 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 700670407 ps |
| CPU time | 61.69 seconds |
| Started | Oct 12 09:21:57 AM UTC 24 |
| Finished | Oct 12 09:23:01 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639997725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.639997725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/15.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/15.alert_handler_sig_int_fail.2735804380 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1484147197 ps |
| CPU time | 28.57 seconds |
| Started | Oct 12 09:23:02 AM UTC 24 |
| Finished | Oct 12 09:23:32 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735804380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2735804380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/15.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/15.alert_handler_smoke.4118439398 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 111357135 ps |
| CPU time | 10.61 seconds |
| Started | Oct 12 09:21:38 AM UTC 24 |
| Finished | Oct 12 09:21:50 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118439398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.4118439398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/15.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all.2026171017 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 43764804228 ps |
| CPU time | 1234.48 seconds |
| Started | Oct 12 09:23:57 AM UTC 24 |
| Finished | Oct 12 09:44:46 AM UTC 24 |
| Peak memory | 297824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026171017 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_stress_all.2026171017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/15.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all_with_rand_reset.1855770420 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 9101675220 ps |
| CPU time | 307.87 seconds |
| Started | Oct 12 09:24:07 AM UTC 24 |
| Finished | Oct 12 09:29:19 AM UTC 24 |
| Peak memory | 279380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1855770420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.a lert_handler_stress_all_with_rand_reset.1855770420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/15.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/16.alert_handler_alert_accum_saturation.3604051035 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 168165633 ps |
| CPU time | 3.6 seconds |
| Started | Oct 12 09:25:27 AM UTC 24 |
| Finished | Oct 12 09:25:31 AM UTC 24 |
| Peak memory | 260968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604051035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3604051035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/16.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy.2736012533 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 54681546705 ps |
| CPU time | 2270.94 seconds |
| Started | Oct 12 09:24:47 AM UTC 24 |
| Finished | Oct 12 10:03:04 AM UTC 24 |
| Peak memory | 293728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736012533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2736012533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/16.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy_stress.3544319867 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 2277246493 ps |
| CPU time | 10.28 seconds |
| Started | Oct 12 09:25:22 AM UTC 24 |
| Finished | Oct 12 09:25:34 AM UTC 24 |
| Peak memory | 260900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544319867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3544319867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/16.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_alert_accum.3786837893 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 23258510760 ps |
| CPU time | 367.9 seconds |
| Started | Oct 12 09:24:41 AM UTC 24 |
| Finished | Oct 12 09:30:54 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786837893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3786837893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/16.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_intr_timeout.904603137 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 192506141 ps |
| CPU time | 6.29 seconds |
| Started | Oct 12 09:24:41 AM UTC 24 |
| Finished | Oct 12 09:24:48 AM UTC 24 |
| Peak memory | 250556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904603137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.904603137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/16.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg.3821339102 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 24439699474 ps |
| CPU time | 1517.59 seconds |
| Started | Oct 12 09:25:01 AM UTC 24 |
| Finished | Oct 12 09:50:36 AM UTC 24 |
| Peak memory | 283432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821339102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3821339102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/16.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_alerts.20065005 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 588422596 ps |
| CPU time | 31.8 seconds |
| Started | Oct 12 09:24:13 AM UTC 24 |
| Finished | Oct 12 09:24:46 AM UTC 24 |
| Peak memory | 261056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20065005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ran dom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.20065005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/16.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_classes.3486590587 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 13583242180 ps |
| CPU time | 67.25 seconds |
| Started | Oct 12 09:24:16 AM UTC 24 |
| Finished | Oct 12 09:25:25 AM UTC 24 |
| Peak memory | 267036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486590587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3486590587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/16.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/16.alert_handler_sig_int_fail.4173397083 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 677320169 ps |
| CPU time | 40.18 seconds |
| Started | Oct 12 09:24:45 AM UTC 24 |
| Finished | Oct 12 09:25:27 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173397083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.4173397083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/16.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/16.alert_handler_smoke.1237136290 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 506137443 ps |
| CPU time | 34.18 seconds |
| Started | Oct 12 09:24:08 AM UTC 24 |
| Finished | Oct 12 09:24:44 AM UTC 24 |
| Peak memory | 266980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237136290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1237136290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/16.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/17.alert_handler_alert_accum_saturation.3560363667 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 18428841 ps |
| CPU time | 4.38 seconds |
| Started | Oct 12 09:27:58 AM UTC 24 |
| Finished | Oct 12 09:28:04 AM UTC 24 |
| Peak memory | 260968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560363667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3560363667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/17.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy.4100535441 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 128190030339 ps |
| CPU time | 1686.62 seconds |
| Started | Oct 12 09:26:25 AM UTC 24 |
| Finished | Oct 12 09:54:51 AM UTC 24 |
| Peak memory | 295908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100535441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.4100535441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/17.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy_stress.318863251 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 4291604390 ps |
| CPU time | 55.94 seconds |
| Started | Oct 12 09:27:22 AM UTC 24 |
| Finished | Oct 12 09:28:20 AM UTC 24 |
| Peak memory | 260904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318863251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.318863251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/17.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_alert_accum.2168002260 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 3939081538 ps |
| CPU time | 64.92 seconds |
| Started | Oct 12 09:26:12 AM UTC 24 |
| Finished | Oct 12 09:27:19 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168002260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2168002260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/17.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_intr_timeout.721156920 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 554107725 ps |
| CPU time | 55.36 seconds |
| Started | Oct 12 09:26:04 AM UTC 24 |
| Finished | Oct 12 09:27:01 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721156920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.721156920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/17.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg.2720204441 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 39748990279 ps |
| CPU time | 1536 seconds |
| Started | Oct 12 09:27:02 AM UTC 24 |
| Finished | Oct 12 09:52:55 AM UTC 24 |
| Peak memory | 299800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720204441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2720204441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/17.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg_stub_clk.110742052 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 277335156365 ps |
| CPU time | 2323.2 seconds |
| Started | Oct 12 09:27:20 AM UTC 24 |
| Finished | Oct 12 10:06:28 AM UTC 24 |
| Peak memory | 299832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110742052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.110742052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/17.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/17.alert_handler_ping_timeout.2890100132 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 83141511231 ps |
| CPU time | 277.98 seconds |
| Started | Oct 12 09:26:34 AM UTC 24 |
| Finished | Oct 12 09:31:15 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890100132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2890100132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_alerts.2789462844 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 244645938 ps |
| CPU time | 34.62 seconds |
| Started | Oct 12 09:25:35 AM UTC 24 |
| Finished | Oct 12 09:26:11 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789462844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2789462844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/17.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_classes.4269992421 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 206391656 ps |
| CPU time | 20.24 seconds |
| Started | Oct 12 09:25:49 AM UTC 24 |
| Finished | Oct 12 09:26:11 AM UTC 24 |
| Peak memory | 261020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269992421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.4269992421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/17.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/17.alert_handler_sig_int_fail.3942976940 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1455590927 ps |
| CPU time | 67.71 seconds |
| Started | Oct 12 09:26:12 AM UTC 24 |
| Finished | Oct 12 09:27:22 AM UTC 24 |
| Peak memory | 260960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942976940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3942976940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/17.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/17.alert_handler_smoke.2248632820 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 839268276 ps |
| CPU time | 59.25 seconds |
| Started | Oct 12 09:25:32 AM UTC 24 |
| Finished | Oct 12 09:26:33 AM UTC 24 |
| Peak memory | 266908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248632820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2248632820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/17.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/17.alert_handler_stress_all.821697474 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 319177635 ps |
| CPU time | 8.93 seconds |
| Started | Oct 12 09:27:47 AM UTC 24 |
| Finished | Oct 12 09:27:57 AM UTC 24 |
| Peak memory | 262884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821697474 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_stress_all.821697474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/17.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/18.alert_handler_alert_accum_saturation.2329079057 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 39596183 ps |
| CPU time | 4.96 seconds |
| Started | Oct 12 09:30:05 AM UTC 24 |
| Finished | Oct 12 09:30:11 AM UTC 24 |
| Peak memory | 261040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329079057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2329079057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/18.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy.43327833 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 26365504455 ps |
| CPU time | 1882.15 seconds |
| Started | Oct 12 09:28:58 AM UTC 24 |
| Finished | Oct 12 10:00:43 AM UTC 24 |
| Peak memory | 283700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43327833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/a lert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.43327833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/18.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy_stress.1421471224 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 235324678 ps |
| CPU time | 18.47 seconds |
| Started | Oct 12 09:29:45 AM UTC 24 |
| Finished | Oct 12 09:30:05 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421471224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1421471224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/18.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_alert_accum.1053825510 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 654488013 ps |
| CPU time | 69.08 seconds |
| Started | Oct 12 09:28:33 AM UTC 24 |
| Finished | Oct 12 09:29:44 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053825510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1053825510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/18.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_intr_timeout.3598494509 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 4751715480 ps |
| CPU time | 72.3 seconds |
| Started | Oct 12 09:28:32 AM UTC 24 |
| Finished | Oct 12 09:29:46 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598494509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3598494509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/18.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg_stub_clk.3277230209 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 161820238899 ps |
| CPU time | 3017.28 seconds |
| Started | Oct 12 09:29:21 AM UTC 24 |
| Finished | Oct 12 10:20:13 AM UTC 24 |
| Peak memory | 302308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277230209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3277230209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/18.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/18.alert_handler_ping_timeout.3926079394 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 92186388409 ps |
| CPU time | 235.26 seconds |
| Started | Oct 12 09:29:14 AM UTC 24 |
| Finished | Oct 12 09:33:13 AM UTC 24 |
| Peak memory | 260908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926079394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3926079394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/18.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_alerts.3278689836 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 237400329 ps |
| CPU time | 10.17 seconds |
| Started | Oct 12 09:28:20 AM UTC 24 |
| Finished | Oct 12 09:28:31 AM UTC 24 |
| Peak memory | 264852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278689836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3278689836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/18.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_classes.1002051185 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 4438174273 ps |
| CPU time | 49.41 seconds |
| Started | Oct 12 09:28:26 AM UTC 24 |
| Finished | Oct 12 09:29:17 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002051185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1002051185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/18.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/18.alert_handler_sig_int_fail.3003238882 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 934499591 ps |
| CPU time | 23.41 seconds |
| Started | Oct 12 09:28:49 AM UTC 24 |
| Finished | Oct 12 09:29:14 AM UTC 24 |
| Peak memory | 266908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003238882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.3003238882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/18.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/18.alert_handler_smoke.2331762293 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 1281935793 ps |
| CPU time | 20.74 seconds |
| Started | Oct 12 09:28:11 AM UTC 24 |
| Finished | Oct 12 09:28:33 AM UTC 24 |
| Peak memory | 267172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331762293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2331762293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/18.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all.34832570 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1506268948 ps |
| CPU time | 94.47 seconds |
| Started | Oct 12 09:29:47 AM UTC 24 |
| Finished | Oct 12 09:31:24 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34832570 -assert nopostproc +UVM_TES TNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_stress_all.34832570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/18.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all_with_rand_reset.3613804460 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 3728432587 ps |
| CPU time | 124.28 seconds |
| Started | Oct 12 09:30:12 AM UTC 24 |
| Finished | Oct 12 09:32:19 AM UTC 24 |
| Peak memory | 277596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3613804460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.a lert_handler_stress_all_with_rand_reset.3613804460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/18.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/19.alert_handler_alert_accum_saturation.2357205495 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 37208124 ps |
| CPU time | 3.66 seconds |
| Started | Oct 12 09:32:20 AM UTC 24 |
| Finished | Oct 12 09:32:25 AM UTC 24 |
| Peak memory | 260964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357205495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2357205495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/19.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy.449216526 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 91918677039 ps |
| CPU time | 919.17 seconds |
| Started | Oct 12 09:31:25 AM UTC 24 |
| Finished | Oct 12 09:46:55 AM UTC 24 |
| Peak memory | 283376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449216526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.449216526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/19.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy_stress.2973828562 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 99156673 ps |
| CPU time | 9.74 seconds |
| Started | Oct 12 09:32:12 AM UTC 24 |
| Finished | Oct 12 09:32:23 AM UTC 24 |
| Peak memory | 260764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973828562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2973828562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/19.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_alert_accum.3549620883 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 1859193601 ps |
| CPU time | 180 seconds |
| Started | Oct 12 09:31:12 AM UTC 24 |
| Finished | Oct 12 09:34:16 AM UTC 24 |
| Peak memory | 262876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549620883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.3549620883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/19.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_intr_timeout.2340105470 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 231163005 ps |
| CPU time | 5.19 seconds |
| Started | Oct 12 09:31:05 AM UTC 24 |
| Finished | Oct 12 09:31:12 AM UTC 24 |
| Peak memory | 250516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340105470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2340105470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/19.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg.3654925759 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 49315219983 ps |
| CPU time | 1255.75 seconds |
| Started | Oct 12 09:31:37 AM UTC 24 |
| Finished | Oct 12 09:52:47 AM UTC 24 |
| Peak memory | 283492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654925759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3654925759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/19.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg_stub_clk.3219306542 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 90757064006 ps |
| CPU time | 1445.56 seconds |
| Started | Oct 12 09:31:42 AM UTC 24 |
| Finished | Oct 12 09:56:04 AM UTC 24 |
| Peak memory | 283704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219306542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3219306542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/19.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/19.alert_handler_ping_timeout.2269338229 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 8526818094 ps |
| CPU time | 342.87 seconds |
| Started | Oct 12 09:31:33 AM UTC 24 |
| Finished | Oct 12 09:37:20 AM UTC 24 |
| Peak memory | 261164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269338229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2269338229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/19.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_alerts.3578433497 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1413309613 ps |
| CPU time | 40.95 seconds |
| Started | Oct 12 09:30:54 AM UTC 24 |
| Finished | Oct 12 09:31:36 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578433497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3578433497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/19.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_classes.334031123 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 7105636704 ps |
| CPU time | 45.08 seconds |
| Started | Oct 12 09:30:55 AM UTC 24 |
| Finished | Oct 12 09:31:42 AM UTC 24 |
| Peak memory | 261084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334031123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.334031123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/19.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/19.alert_handler_sig_int_fail.2115894950 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 2359908565 ps |
| CPU time | 67.79 seconds |
| Started | Oct 12 09:31:17 AM UTC 24 |
| Finished | Oct 12 09:32:26 AM UTC 24 |
| Peak memory | 260824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115894950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2115894950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/19.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/19.alert_handler_smoke.601839634 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 1389492933 ps |
| CPU time | 46.06 seconds |
| Started | Oct 12 09:30:44 AM UTC 24 |
| Finished | Oct 12 09:31:32 AM UTC 24 |
| Peak memory | 260760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601839634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.601839634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/19.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/2.alert_handler_alert_accum_saturation.1448474690 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 139314432 ps |
| CPU time | 5.01 seconds |
| Started | Oct 12 09:03:37 AM UTC 24 |
| Finished | Oct 12 09:03:43 AM UTC 24 |
| Peak memory | 260964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448474690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1448474690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy.649160774 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 18357605636 ps |
| CPU time | 1259.35 seconds |
| Started | Oct 12 09:03:25 AM UTC 24 |
| Finished | Oct 12 09:24:39 AM UTC 24 |
| Peak memory | 283436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649160774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.649160774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy_stress.3308992275 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 147308673 ps |
| CPU time | 15.72 seconds |
| Started | Oct 12 09:03:33 AM UTC 24 |
| Finished | Oct 12 09:03:50 AM UTC 24 |
| Peak memory | 260840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308992275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3308992275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_alert_accum.2643598370 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 4192032666 ps |
| CPU time | 265.75 seconds |
| Started | Oct 12 09:03:20 AM UTC 24 |
| Finished | Oct 12 09:07:50 AM UTC 24 |
| Peak memory | 267228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643598370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2643598370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_intr_timeout.3594598331 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 989518223 ps |
| CPU time | 56.28 seconds |
| Started | Oct 12 09:03:16 AM UTC 24 |
| Finished | Oct 12 09:04:15 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594598331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3594598331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg_stub_clk.1487952370 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 40267136655 ps |
| CPU time | 1019.18 seconds |
| Started | Oct 12 09:03:33 AM UTC 24 |
| Finished | Oct 12 09:20:45 AM UTC 24 |
| Peak memory | 283428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487952370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1487952370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_alerts.109661026 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 341578852 ps |
| CPU time | 36.27 seconds |
| Started | Oct 12 09:03:14 AM UTC 24 |
| Finished | Oct 12 09:03:52 AM UTC 24 |
| Peak memory | 261056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109661026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.109661026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_classes.1118636816 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 80306322 ps |
| CPU time | 14.39 seconds |
| Started | Oct 12 09:03:16 AM UTC 24 |
| Finished | Oct 12 09:03:32 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118636816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1118636816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/2.alert_handler_sec_cm.59425537 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 460495208 ps |
| CPU time | 20.24 seconds |
| Started | Oct 12 09:03:42 AM UTC 24 |
| Finished | Oct 12 09:04:04 AM UTC 24 |
| Peak memory | 295056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59425537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_ha ndler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.59425537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/2.alert_handler_smoke.3639245182 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 38161341 ps |
| CPU time | 5.39 seconds |
| Started | Oct 12 09:03:08 AM UTC 24 |
| Finished | Oct 12 09:03:15 AM UTC 24 |
| Peak memory | 261020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639245182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3639245182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all.1846483294 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 196663904851 ps |
| CPU time | 3558.74 seconds |
| Started | Oct 12 09:03:34 AM UTC 24 |
| Finished | Oct 12 10:03:33 AM UTC 24 |
| Peak memory | 300020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846483294 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_stress_all.1846483294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/2.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/20.alert_handler_entropy.786923380 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 87931988497 ps |
| CPU time | 1877.94 seconds |
| Started | Oct 12 09:33:25 AM UTC 24 |
| Finished | Oct 12 10:05:05 AM UTC 24 |
| Peak memory | 299760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786923380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.786923380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/20.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_alert_accum.2320879623 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 4040983401 ps |
| CPU time | 231.8 seconds |
| Started | Oct 12 09:33:09 AM UTC 24 |
| Finished | Oct 12 09:37:04 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320879623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2320879623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/20.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_intr_timeout.4075908798 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 209424891 ps |
| CPU time | 26.18 seconds |
| Started | Oct 12 09:32:59 AM UTC 24 |
| Finished | Oct 12 09:33:27 AM UTC 24 |
| Peak memory | 261020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075908798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.4075908798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/20.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg.2611353658 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 49401282067 ps |
| CPU time | 1593.82 seconds |
| Started | Oct 12 09:33:42 AM UTC 24 |
| Finished | Oct 12 10:00:35 AM UTC 24 |
| Peak memory | 279528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611353658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2611353658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/20.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg_stub_clk.354108117 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 31256859704 ps |
| CPU time | 1785.97 seconds |
| Started | Oct 12 09:33:52 AM UTC 24 |
| Finished | Oct 12 10:03:58 AM UTC 24 |
| Peak memory | 283448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354108117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.354108117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/20.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/20.alert_handler_ping_timeout.1851157133 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 110916788595 ps |
| CPU time | 247.01 seconds |
| Started | Oct 12 09:33:28 AM UTC 24 |
| Finished | Oct 12 09:37:39 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851157133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1851157133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/20.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_alerts.3181931540 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 340486410 ps |
| CPU time | 41.19 seconds |
| Started | Oct 12 09:32:25 AM UTC 24 |
| Finished | Oct 12 09:33:08 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181931540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3181931540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/20.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_classes.3082577637 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 484792461 ps |
| CPU time | 30.13 seconds |
| Started | Oct 12 09:32:27 AM UTC 24 |
| Finished | Oct 12 09:32:59 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082577637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3082577637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/20.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/20.alert_handler_sig_int_fail.653304368 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 972138238 ps |
| CPU time | 25.84 seconds |
| Started | Oct 12 09:33:14 AM UTC 24 |
| Finished | Oct 12 09:33:41 AM UTC 24 |
| Peak memory | 261056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653304368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.653304368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/20.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/20.alert_handler_smoke.1650623945 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 2514573942 ps |
| CPU time | 59.43 seconds |
| Started | Oct 12 09:32:23 AM UTC 24 |
| Finished | Oct 12 09:33:24 AM UTC 24 |
| Peak memory | 267236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650623945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1650623945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/20.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all.1432738334 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 103578005535 ps |
| CPU time | 2799.96 seconds |
| Started | Oct 12 09:34:06 AM UTC 24 |
| Finished | Oct 12 10:21:18 AM UTC 24 |
| Peak memory | 302636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432738334 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_stress_all.1432738334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/20.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/21.alert_handler_entropy.3905844449 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 89909619511 ps |
| CPU time | 1428.34 seconds |
| Started | Oct 12 09:35:57 AM UTC 24 |
| Finished | Oct 12 10:00:03 AM UTC 24 |
| Peak memory | 283504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905844449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3905844449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/21.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_alert_accum.909020462 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 909052376 ps |
| CPU time | 72.41 seconds |
| Started | Oct 12 09:35:25 AM UTC 24 |
| Finished | Oct 12 09:36:39 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909020462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.909020462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/21.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_intr_timeout.2301429362 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 273310117 ps |
| CPU time | 26.91 seconds |
| Started | Oct 12 09:34:56 AM UTC 24 |
| Finished | Oct 12 09:35:24 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301429362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.2301429362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/21.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg.3517645573 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 19321250162 ps |
| CPU time | 1137.5 seconds |
| Started | Oct 12 09:37:05 AM UTC 24 |
| Finished | Oct 12 09:56:17 AM UTC 24 |
| Peak memory | 283564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517645573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3517645573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/21.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg_stub_clk.2412735664 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 97262720081 ps |
| CPU time | 1227.21 seconds |
| Started | Oct 12 09:37:07 AM UTC 24 |
| Finished | Oct 12 09:57:49 AM UTC 24 |
| Peak memory | 283436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412735664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2412735664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/21.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/21.alert_handler_ping_timeout.550118420 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 11614045807 ps |
| CPU time | 330.02 seconds |
| Started | Oct 12 09:36:41 AM UTC 24 |
| Finished | Oct 12 09:42:16 AM UTC 24 |
| Peak memory | 261096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550118420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.550118420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_alerts.2149491998 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 776083226 ps |
| CPU time | 12.88 seconds |
| Started | Oct 12 09:34:41 AM UTC 24 |
| Finished | Oct 12 09:34:55 AM UTC 24 |
| Peak memory | 267164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149491998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2149491998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/21.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_classes.3472095435 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 231439899 ps |
| CPU time | 32.29 seconds |
| Started | Oct 12 09:34:55 AM UTC 24 |
| Finished | Oct 12 09:35:29 AM UTC 24 |
| Peak memory | 261024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472095435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3472095435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/21.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/21.alert_handler_sig_int_fail.4268759084 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 930323723 ps |
| CPU time | 25.31 seconds |
| Started | Oct 12 09:35:29 AM UTC 24 |
| Finished | Oct 12 09:35:56 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268759084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.4268759084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/21.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/21.alert_handler_smoke.1218492766 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 429150484 ps |
| CPU time | 31.94 seconds |
| Started | Oct 12 09:34:21 AM UTC 24 |
| Finished | Oct 12 09:34:54 AM UTC 24 |
| Peak memory | 266980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218492766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1218492766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/21.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all.1852185665 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 9362523464 ps |
| CPU time | 719.99 seconds |
| Started | Oct 12 09:37:18 AM UTC 24 |
| Finished | Oct 12 09:49:28 AM UTC 24 |
| Peak memory | 281456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852185665 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_stress_all.1852185665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/21.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/22.alert_handler_entropy.2417245136 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 8627160043 ps |
| CPU time | 892.45 seconds |
| Started | Oct 12 09:38:57 AM UTC 24 |
| Finished | Oct 12 09:54:01 AM UTC 24 |
| Peak memory | 283504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417245136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2417245136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/22.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_alert_accum.277089452 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1605001155 ps |
| CPU time | 137.33 seconds |
| Started | Oct 12 09:38:48 AM UTC 24 |
| Finished | Oct 12 09:41:09 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277089452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.277089452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/22.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_intr_timeout.2578684288 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 131991319 ps |
| CPU time | 13.73 seconds |
| Started | Oct 12 09:38:35 AM UTC 24 |
| Finished | Oct 12 09:38:51 AM UTC 24 |
| Peak memory | 260752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578684288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2578684288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/22.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg.2689270351 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 636444735103 ps |
| CPU time | 2431.46 seconds |
| Started | Oct 12 09:39:24 AM UTC 24 |
| Finished | Oct 12 10:20:23 AM UTC 24 |
| Peak memory | 296104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689270351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2689270351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/22.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg_stub_clk.1343792174 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 92010238697 ps |
| CPU time | 1748.69 seconds |
| Started | Oct 12 09:39:42 AM UTC 24 |
| Finished | Oct 12 10:09:10 AM UTC 24 |
| Peak memory | 283364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343792174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1343792174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/22.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/22.alert_handler_ping_timeout.1441048153 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 12120343015 ps |
| CPU time | 452.1 seconds |
| Started | Oct 12 09:39:06 AM UTC 24 |
| Finished | Oct 12 09:46:44 AM UTC 24 |
| Peak memory | 261096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441048153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1441048153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_alerts.2583350718 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 17365488 ps |
| CPU time | 4.74 seconds |
| Started | Oct 12 09:38:28 AM UTC 24 |
| Finished | Oct 12 09:38:34 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583350718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2583350718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/22.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_classes.2029596091 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 289463526 ps |
| CPU time | 27.81 seconds |
| Started | Oct 12 09:38:35 AM UTC 24 |
| Finished | Oct 12 09:39:05 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029596091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2029596091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/22.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/22.alert_handler_smoke.2312553119 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 802160028 ps |
| CPU time | 45.41 seconds |
| Started | Oct 12 09:37:40 AM UTC 24 |
| Finished | Oct 12 09:38:27 AM UTC 24 |
| Peak memory | 266908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312553119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2312553119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/22.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all_with_rand_reset.3158274965 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 2208053496 ps |
| CPU time | 230.47 seconds |
| Started | Oct 12 09:39:45 AM UTC 24 |
| Finished | Oct 12 09:43:39 AM UTC 24 |
| Peak memory | 283548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3158274965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.a lert_handler_stress_all_with_rand_reset.3158274965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/22.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/23.alert_handler_entropy.2549961033 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 31445078131 ps |
| CPU time | 859.46 seconds |
| Started | Oct 12 09:40:43 AM UTC 24 |
| Finished | Oct 12 09:55:13 AM UTC 24 |
| Peak memory | 299740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549961033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2549961033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/23.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_alert_accum.3870715083 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 11825850249 ps |
| CPU time | 123.9 seconds |
| Started | Oct 12 09:40:31 AM UTC 24 |
| Finished | Oct 12 09:42:38 AM UTC 24 |
| Peak memory | 262868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870715083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3870715083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/23.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_intr_timeout.3827906869 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 2101832168 ps |
| CPU time | 18.82 seconds |
| Started | Oct 12 09:40:21 AM UTC 24 |
| Finished | Oct 12 09:40:42 AM UTC 24 |
| Peak memory | 267164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827906869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3827906869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/23.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg.2526857921 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 42917586864 ps |
| CPU time | 877.49 seconds |
| Started | Oct 12 09:40:51 AM UTC 24 |
| Finished | Oct 12 09:55:38 AM UTC 24 |
| Peak memory | 283488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526857921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2526857921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/23.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg_stub_clk.2690851804 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 91597080806 ps |
| CPU time | 1935.18 seconds |
| Started | Oct 12 09:41:10 AM UTC 24 |
| Finished | Oct 12 10:13:47 AM UTC 24 |
| Peak memory | 299744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690851804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2690851804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/23.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/23.alert_handler_ping_timeout.3329567258 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 22295908030 ps |
| CPU time | 250.64 seconds |
| Started | Oct 12 09:40:46 AM UTC 24 |
| Finished | Oct 12 09:45:01 AM UTC 24 |
| Peak memory | 261096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329567258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3329567258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/23.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_alerts.2977895319 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 6286566311 ps |
| CPU time | 52.15 seconds |
| Started | Oct 12 09:39:55 AM UTC 24 |
| Finished | Oct 12 09:40:49 AM UTC 24 |
| Peak memory | 267164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977895319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2977895319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/23.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_classes.857169261 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 905708397 ps |
| CPU time | 28.11 seconds |
| Started | Oct 12 09:40:01 AM UTC 24 |
| Finished | Oct 12 09:40:30 AM UTC 24 |
| Peak memory | 261020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857169261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.857169261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/23.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/23.alert_handler_sig_int_fail.3093256656 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 325578185 ps |
| CPU time | 38.44 seconds |
| Started | Oct 12 09:40:38 AM UTC 24 |
| Finished | Oct 12 09:41:18 AM UTC 24 |
| Peak memory | 260760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093256656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3093256656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/23.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/23.alert_handler_smoke.657354687 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 606686696 ps |
| CPU time | 24.18 seconds |
| Started | Oct 12 09:39:55 AM UTC 24 |
| Finished | Oct 12 09:40:21 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657354687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.657354687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/23.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all.2562961757 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 170503243341 ps |
| CPU time | 2448.92 seconds |
| Started | Oct 12 09:41:19 AM UTC 24 |
| Finished | Oct 12 10:22:34 AM UTC 24 |
| Peak memory | 302572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562961757 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_stress_all.2562961757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/23.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/24.alert_handler_entropy.3334691100 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 68031396875 ps |
| CPU time | 1398.85 seconds |
| Started | Oct 12 09:42:46 AM UTC 24 |
| Finished | Oct 12 10:06:21 AM UTC 24 |
| Peak memory | 283620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334691100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3334691100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/24.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_alert_accum.492276209 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 79278894725 ps |
| CPU time | 283.21 seconds |
| Started | Oct 12 09:42:37 AM UTC 24 |
| Finished | Oct 12 09:47:25 AM UTC 24 |
| Peak memory | 267036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492276209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.492276209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/24.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_intr_timeout.3022413502 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 2684072712 ps |
| CPU time | 67.94 seconds |
| Started | Oct 12 09:42:31 AM UTC 24 |
| Finished | Oct 12 09:43:41 AM UTC 24 |
| Peak memory | 260892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022413502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3022413502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/24.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg.3063786765 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 131475058793 ps |
| CPU time | 1914.68 seconds |
| Started | Oct 12 09:43:29 AM UTC 24 |
| Finished | Oct 12 10:15:46 AM UTC 24 |
| Peak memory | 297768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063786765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3063786765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/24.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg_stub_clk.3529418 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 45641372677 ps |
| CPU time | 2229.21 seconds |
| Started | Oct 12 09:43:40 AM UTC 24 |
| Finished | Oct 12 10:21:13 AM UTC 24 |
| Peak memory | 302324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test + UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3529418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/24.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_alerts.243941087 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 3805658786 ps |
| CPU time | 18.22 seconds |
| Started | Oct 12 09:42:17 AM UTC 24 |
| Finished | Oct 12 09:42:36 AM UTC 24 |
| Peak memory | 267044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243941087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.243941087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/24.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_classes.3328752482 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2380143951 ps |
| CPU time | 62.59 seconds |
| Started | Oct 12 09:42:24 AM UTC 24 |
| Finished | Oct 12 09:43:28 AM UTC 24 |
| Peak memory | 267228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328752482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3328752482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/24.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/24.alert_handler_smoke.1331116195 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 3826722295 ps |
| CPU time | 22.93 seconds |
| Started | Oct 12 09:41:59 AM UTC 24 |
| Finished | Oct 12 09:42:23 AM UTC 24 |
| Peak memory | 267044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331116195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1331116195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/24.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all.1798083708 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 181617853471 ps |
| CPU time | 2892.39 seconds |
| Started | Oct 12 09:43:42 AM UTC 24 |
| Finished | Oct 12 10:32:26 AM UTC 24 |
| Peak memory | 302380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798083708 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_stress_all.1798083708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/24.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all_with_rand_reset.3893952342 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1233283974 ps |
| CPU time | 45.4 seconds |
| Started | Oct 12 09:44:07 AM UTC 24 |
| Finished | Oct 12 09:44:53 AM UTC 24 |
| Peak memory | 283484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3893952342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.a lert_handler_stress_all_with_rand_reset.3893952342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/24.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/25.alert_handler_entropy.1567328357 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 54582495201 ps |
| CPU time | 1171.74 seconds |
| Started | Oct 12 09:44:43 AM UTC 24 |
| Finished | Oct 12 10:04:28 AM UTC 24 |
| Peak memory | 297956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567328357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1567328357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/25.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_alert_accum.3873001626 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 8083443123 ps |
| CPU time | 102.39 seconds |
| Started | Oct 12 09:44:27 AM UTC 24 |
| Finished | Oct 12 09:46:12 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873001626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3873001626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/25.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_intr_timeout.4086977722 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 156178587 ps |
| CPU time | 13.67 seconds |
| Started | Oct 12 09:44:27 AM UTC 24 |
| Finished | Oct 12 09:44:42 AM UTC 24 |
| Peak memory | 260752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086977722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.4086977722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/25.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg.2264399971 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 31928890082 ps |
| CPU time | 1563.89 seconds |
| Started | Oct 12 09:44:48 AM UTC 24 |
| Finished | Oct 12 10:11:10 AM UTC 24 |
| Peak memory | 300128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264399971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2264399971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/25.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg_stub_clk.485721854 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 87315088220 ps |
| CPU time | 1884.13 seconds |
| Started | Oct 12 09:44:55 AM UTC 24 |
| Finished | Oct 12 10:16:41 AM UTC 24 |
| Peak memory | 300024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485721854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.485721854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/25.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/25.alert_handler_ping_timeout.3968295056 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 12719167251 ps |
| CPU time | 497.76 seconds |
| Started | Oct 12 09:44:48 AM UTC 24 |
| Finished | Oct 12 09:53:11 AM UTC 24 |
| Peak memory | 260968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968295056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3968295056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/25.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_alerts.3749810030 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 328912452 ps |
| CPU time | 30.98 seconds |
| Started | Oct 12 09:44:14 AM UTC 24 |
| Finished | Oct 12 09:44:46 AM UTC 24 |
| Peak memory | 267164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749810030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3749810030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/25.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_classes.1726991109 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 16947564 ps |
| CPU time | 4.29 seconds |
| Started | Oct 12 09:44:20 AM UTC 24 |
| Finished | Oct 12 09:44:25 AM UTC 24 |
| Peak memory | 250720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726991109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1726991109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/25.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/25.alert_handler_sig_int_fail.274043362 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 718787950 ps |
| CPU time | 18.17 seconds |
| Started | Oct 12 09:44:42 AM UTC 24 |
| Finished | Oct 12 09:45:01 AM UTC 24 |
| Peak memory | 267012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274043362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.274043362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/25.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/25.alert_handler_smoke.3701174845 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 726852457 ps |
| CPU time | 57.3 seconds |
| Started | Oct 12 09:44:08 AM UTC 24 |
| Finished | Oct 12 09:45:07 AM UTC 24 |
| Peak memory | 266908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701174845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3701174845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/25.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all.3635448570 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 12623327641 ps |
| CPU time | 1326.47 seconds |
| Started | Oct 12 09:44:56 AM UTC 24 |
| Finished | Oct 12 10:07:19 AM UTC 24 |
| Peak memory | 300020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635448570 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_stress_all.3635448570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/25.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all_with_rand_reset.3179771848 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 841180545 ps |
| CPU time | 94.17 seconds |
| Started | Oct 12 09:45:01 AM UTC 24 |
| Finished | Oct 12 09:46:38 AM UTC 24 |
| Peak memory | 277536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3179771848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.a lert_handler_stress_all_with_rand_reset.3179771848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/25.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/26.alert_handler_entropy.2389483009 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 13054843853 ps |
| CPU time | 1049.18 seconds |
| Started | Oct 12 09:46:12 AM UTC 24 |
| Finished | Oct 12 10:03:54 AM UTC 24 |
| Peak memory | 283428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389483009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2389483009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/26.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_alert_accum.2789571775 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 1623527503 ps |
| CPU time | 53.95 seconds |
| Started | Oct 12 09:45:58 AM UTC 24 |
| Finished | Oct 12 09:46:54 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789571775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2789571775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/26.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_intr_timeout.1753633901 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 981881751 ps |
| CPU time | 27.46 seconds |
| Started | Oct 12 09:45:48 AM UTC 24 |
| Finished | Oct 12 09:46:17 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753633901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1753633901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/26.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg_stub_clk.476884079 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 171629451832 ps |
| CPU time | 2516.79 seconds |
| Started | Oct 12 09:46:43 AM UTC 24 |
| Finished | Oct 12 10:29:08 AM UTC 24 |
| Peak memory | 300264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476884079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.476884079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/26.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/26.alert_handler_ping_timeout.3233542279 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 15388473401 ps |
| CPU time | 641.69 seconds |
| Started | Oct 12 09:46:17 AM UTC 24 |
| Finished | Oct 12 09:57:06 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233542279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3233542279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/26.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_alerts.613786038 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 2287084846 ps |
| CPU time | 37.07 seconds |
| Started | Oct 12 09:45:08 AM UTC 24 |
| Finished | Oct 12 09:45:47 AM UTC 24 |
| Peak memory | 266980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613786038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.613786038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/26.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_classes.3351373136 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 545446436 ps |
| CPU time | 24.39 seconds |
| Started | Oct 12 09:45:42 AM UTC 24 |
| Finished | Oct 12 09:46:07 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351373136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3351373136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/26.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/26.alert_handler_sig_int_fail.3820037808 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1423708034 ps |
| CPU time | 32.15 seconds |
| Started | Oct 12 09:46:08 AM UTC 24 |
| Finished | Oct 12 09:46:42 AM UTC 24 |
| Peak memory | 261024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820037808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3820037808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/26.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/26.alert_handler_smoke.3996279018 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 2388138338 ps |
| CPU time | 36.57 seconds |
| Started | Oct 12 09:45:02 AM UTC 24 |
| Finished | Oct 12 09:45:41 AM UTC 24 |
| Peak memory | 267044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996279018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3996279018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/26.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all.3785163070 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 180511943601 ps |
| CPU time | 1815.62 seconds |
| Started | Oct 12 09:46:45 AM UTC 24 |
| Finished | Oct 12 10:17:21 AM UTC 24 |
| Peak memory | 316200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785163070 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_stress_all.3785163070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/26.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/27.alert_handler_entropy.1790142964 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 105628964786 ps |
| CPU time | 1601.26 seconds |
| Started | Oct 12 09:49:05 AM UTC 24 |
| Finished | Oct 12 10:16:05 AM UTC 24 |
| Peak memory | 283764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790142964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1790142964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/27.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_alert_accum.1684121169 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 2099134690 ps |
| CPU time | 225.37 seconds |
| Started | Oct 12 09:48:11 AM UTC 24 |
| Finished | Oct 12 09:52:00 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684121169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1684121169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/27.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg.2186367990 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 41283378618 ps |
| CPU time | 904 seconds |
| Started | Oct 12 09:49:30 AM UTC 24 |
| Finished | Oct 12 10:04:45 AM UTC 24 |
| Peak memory | 283428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186367990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2186367990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/27.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg_stub_clk.2086274978 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 94512808629 ps |
| CPU time | 1697 seconds |
| Started | Oct 12 09:49:32 AM UTC 24 |
| Finished | Oct 12 10:18:08 AM UTC 24 |
| Peak memory | 283364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086274978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2086274978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/27.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/27.alert_handler_ping_timeout.1458535216 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 11003037848 ps |
| CPU time | 364.09 seconds |
| Started | Oct 12 09:49:23 AM UTC 24 |
| Finished | Oct 12 09:55:32 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458535216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1458535216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_alerts.2110247727 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 258614791 ps |
| CPU time | 23.47 seconds |
| Started | Oct 12 09:47:26 AM UTC 24 |
| Finished | Oct 12 09:47:51 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110247727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2110247727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/27.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_classes.2665347570 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 455545758 ps |
| CPU time | 11.76 seconds |
| Started | Oct 12 09:47:53 AM UTC 24 |
| Finished | Oct 12 09:48:05 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665347570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2665347570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/27.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/27.alert_handler_sig_int_fail.1416014299 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 237991060 ps |
| CPU time | 32.02 seconds |
| Started | Oct 12 09:48:48 AM UTC 24 |
| Finished | Oct 12 09:49:22 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416014299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1416014299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/27.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/27.alert_handler_smoke.461790945 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 2800100233 ps |
| CPU time | 71.27 seconds |
| Started | Oct 12 09:46:57 AM UTC 24 |
| Finished | Oct 12 09:48:10 AM UTC 24 |
| Peak memory | 267232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461790945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.461790945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/27.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all.1142595235 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 32276575926 ps |
| CPU time | 1782.84 seconds |
| Started | Oct 12 09:49:50 AM UTC 24 |
| Finished | Oct 12 10:19:54 AM UTC 24 |
| Peak memory | 316212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142595235 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_stress_all.1142595235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/27.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/28.alert_handler_entropy.1736170237 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 28520246796 ps |
| CPU time | 2035.1 seconds |
| Started | Oct 12 09:52:01 AM UTC 24 |
| Finished | Oct 12 10:26:20 AM UTC 24 |
| Peak memory | 300200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736170237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1736170237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/28.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_alert_accum.1903137935 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 3457950506 ps |
| CPU time | 199.92 seconds |
| Started | Oct 12 09:51:32 AM UTC 24 |
| Finished | Oct 12 09:54:55 AM UTC 24 |
| Peak memory | 267036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903137935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1903137935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/28.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_intr_timeout.1754727421 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 327247794 ps |
| CPU time | 31.81 seconds |
| Started | Oct 12 09:51:01 AM UTC 24 |
| Finished | Oct 12 09:51:34 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754727421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1754727421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/28.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg.390148536 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 10670887396 ps |
| CPU time | 1077.2 seconds |
| Started | Oct 12 09:52:23 AM UTC 24 |
| Finished | Oct 12 10:10:33 AM UTC 24 |
| Peak memory | 295704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390148536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.390148536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/28.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg_stub_clk.1457626413 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 18550481425 ps |
| CPU time | 574.59 seconds |
| Started | Oct 12 09:52:23 AM UTC 24 |
| Finished | Oct 12 10:02:06 AM UTC 24 |
| Peak memory | 277216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457626413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1457626413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/28.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/28.alert_handler_ping_timeout.269296701 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 20945380535 ps |
| CPU time | 168.95 seconds |
| Started | Oct 12 09:52:10 AM UTC 24 |
| Finished | Oct 12 09:55:01 AM UTC 24 |
| Peak memory | 267048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269296701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.269296701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/28.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_alerts.1297230873 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 789128980 ps |
| CPU time | 22.56 seconds |
| Started | Oct 12 09:50:36 AM UTC 24 |
| Finished | Oct 12 09:51:00 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297230873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1297230873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/28.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_classes.3498413431 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 837710112 ps |
| CPU time | 51.14 seconds |
| Started | Oct 12 09:50:39 AM UTC 24 |
| Finished | Oct 12 09:51:31 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498413431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3498413431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/28.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/28.alert_handler_sig_int_fail.2644786422 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 1203042450 ps |
| CPU time | 43.93 seconds |
| Started | Oct 12 09:51:35 AM UTC 24 |
| Finished | Oct 12 09:52:21 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644786422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2644786422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/28.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/28.alert_handler_smoke.2606296224 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 90173504 ps |
| CPU time | 15.29 seconds |
| Started | Oct 12 09:50:19 AM UTC 24 |
| Finished | Oct 12 09:50:36 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606296224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2606296224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/28.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all.2265558804 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 37901777947 ps |
| CPU time | 2322.69 seconds |
| Started | Oct 12 09:52:37 AM UTC 24 |
| Finished | Oct 12 10:31:46 AM UTC 24 |
| Peak memory | 302304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265558804 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_stress_all.2265558804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/28.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/29.alert_handler_entropy.538463529 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 40518260900 ps |
| CPU time | 1566.86 seconds |
| Started | Oct 12 09:54:02 AM UTC 24 |
| Finished | Oct 12 10:20:28 AM UTC 24 |
| Peak memory | 300008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538463529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.538463529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/29.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_alert_accum.629201605 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 881375498 ps |
| CPU time | 87.04 seconds |
| Started | Oct 12 09:53:38 AM UTC 24 |
| Finished | Oct 12 09:55:08 AM UTC 24 |
| Peak memory | 266560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629201605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.629201605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/29.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_intr_timeout.2863157488 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 575474139 ps |
| CPU time | 24.05 seconds |
| Started | Oct 12 09:53:12 AM UTC 24 |
| Finished | Oct 12 09:53:37 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863157488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2863157488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/29.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg.3388608750 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 46146166765 ps |
| CPU time | 2621.46 seconds |
| Started | Oct 12 09:54:28 AM UTC 24 |
| Finished | Oct 12 10:38:39 AM UTC 24 |
| Peak memory | 300244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388608750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3388608750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/29.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg_stub_clk.3714210208 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 21831715291 ps |
| CPU time | 1305.81 seconds |
| Started | Oct 12 09:54:35 AM UTC 24 |
| Finished | Oct 12 10:16:37 AM UTC 24 |
| Peak memory | 299820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714210208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3714210208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/29.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/29.alert_handler_ping_timeout.2376234784 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 23364071436 ps |
| CPU time | 372.16 seconds |
| Started | Oct 12 09:54:05 AM UTC 24 |
| Finished | Oct 12 10:00:21 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376234784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2376234784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/29.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_alerts.1032944758 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 6512155623 ps |
| CPU time | 64.24 seconds |
| Started | Oct 12 09:52:58 AM UTC 24 |
| Finished | Oct 12 09:54:04 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032944758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1032944758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/29.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_classes.1397299973 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 930102072 ps |
| CPU time | 81.79 seconds |
| Started | Oct 12 09:53:03 AM UTC 24 |
| Finished | Oct 12 09:54:27 AM UTC 24 |
| Peak memory | 267168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397299973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1397299973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/29.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/29.alert_handler_sig_int_fail.3872728165 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 932756333 ps |
| CPU time | 54.38 seconds |
| Started | Oct 12 09:53:38 AM UTC 24 |
| Finished | Oct 12 09:54:34 AM UTC 24 |
| Peak memory | 260484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872728165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3872728165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/29.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/29.alert_handler_smoke.348114759 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 84617039 ps |
| CPU time | 8.39 seconds |
| Started | Oct 12 09:52:52 AM UTC 24 |
| Finished | Oct 12 09:53:02 AM UTC 24 |
| Peak memory | 266904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348114759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.348114759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/29.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all_with_rand_reset.3216986483 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 20137345944 ps |
| CPU time | 354.98 seconds |
| Started | Oct 12 09:54:54 AM UTC 24 |
| Finished | Oct 12 10:00:54 AM UTC 24 |
| Peak memory | 279648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3216986483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.a lert_handler_stress_all_with_rand_reset.3216986483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/29.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/3.alert_handler_alert_accum_saturation.2613407544 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 42033206 ps |
| CPU time | 5.14 seconds |
| Started | Oct 12 09:04:04 AM UTC 24 |
| Finished | Oct 12 09:04:10 AM UTC 24 |
| Peak memory | 260976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613407544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2613407544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy_stress.4169254515 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3894179375 ps |
| CPU time | 75.12 seconds |
| Started | Oct 12 09:04:00 AM UTC 24 |
| Finished | Oct 12 09:05:17 AM UTC 24 |
| Peak memory | 261096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169254515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.4169254515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg_stub_clk.3609113034 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 34240507050 ps |
| CPU time | 2072.93 seconds |
| Started | Oct 12 09:03:58 AM UTC 24 |
| Finished | Oct 12 09:38:55 AM UTC 24 |
| Peak memory | 297760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609113034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3609113034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_alerts.1992953585 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1712371541 ps |
| CPU time | 30.29 seconds |
| Started | Oct 12 09:03:46 AM UTC 24 |
| Finished | Oct 12 09:04:17 AM UTC 24 |
| Peak memory | 266912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992953585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1992953585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_classes.1870775054 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1152344088 ps |
| CPU time | 56.62 seconds |
| Started | Oct 12 09:03:48 AM UTC 24 |
| Finished | Oct 12 09:04:46 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870775054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1870775054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/3.alert_handler_sec_cm.84421536 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 7275695358 ps |
| CPU time | 36.26 seconds |
| Started | Oct 12 09:04:05 AM UTC 24 |
| Finished | Oct 12 09:04:43 AM UTC 24 |
| Peak memory | 295052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84421536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_ha ndler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.84421536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/3.alert_handler_sig_int_fail.3804211858 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 149062754 ps |
| CPU time | 19.96 seconds |
| Started | Oct 12 09:03:49 AM UTC 24 |
| Finished | Oct 12 09:04:10 AM UTC 24 |
| Peak memory | 267008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804211858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3804211858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/3.alert_handler_smoke.3487501317 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 167271598 ps |
| CPU time | 11.89 seconds |
| Started | Oct 12 09:03:44 AM UTC 24 |
| Finished | Oct 12 09:03:58 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487501317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3487501317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/3.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/30.alert_handler_entropy.2424581104 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 92090216259 ps |
| CPU time | 2998.26 seconds |
| Started | Oct 12 09:55:46 AM UTC 24 |
| Finished | Oct 12 10:46:19 AM UTC 24 |
| Peak memory | 300316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424581104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2424581104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/30.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_alert_accum.1121847196 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 20545858583 ps |
| CPU time | 204.38 seconds |
| Started | Oct 12 09:55:33 AM UTC 24 |
| Finished | Oct 12 09:59:01 AM UTC 24 |
| Peak memory | 266968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121847196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1121847196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/30.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_intr_timeout.3396658267 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 998409726 ps |
| CPU time | 81.12 seconds |
| Started | Oct 12 09:55:15 AM UTC 24 |
| Finished | Oct 12 09:56:38 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396658267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3396658267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/30.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg.3262359152 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 40556210917 ps |
| CPU time | 1356.5 seconds |
| Started | Oct 12 09:56:06 AM UTC 24 |
| Finished | Oct 12 10:18:59 AM UTC 24 |
| Peak memory | 283628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262359152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3262359152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/30.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg_stub_clk.3113503292 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 36597107085 ps |
| CPU time | 2201.1 seconds |
| Started | Oct 12 09:56:12 AM UTC 24 |
| Finished | Oct 12 10:33:18 AM UTC 24 |
| Peak memory | 285868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113503292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3113503292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/30.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/30.alert_handler_ping_timeout.3646944895 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 3386103373 ps |
| CPU time | 149.67 seconds |
| Started | Oct 12 09:55:58 AM UTC 24 |
| Finished | Oct 12 09:58:30 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646944895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3646944895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/30.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_alerts.1425220064 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 3488855097 ps |
| CPU time | 75.86 seconds |
| Started | Oct 12 09:55:02 AM UTC 24 |
| Finished | Oct 12 09:56:20 AM UTC 24 |
| Peak memory | 267100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425220064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1425220064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/30.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_classes.3082913522 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 557514708 ps |
| CPU time | 46.08 seconds |
| Started | Oct 12 09:55:08 AM UTC 24 |
| Finished | Oct 12 09:55:56 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082913522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3082913522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/30.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/30.alert_handler_smoke.2651561363 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 3132769086 ps |
| CPU time | 47.13 seconds |
| Started | Oct 12 09:54:56 AM UTC 24 |
| Finished | Oct 12 09:55:45 AM UTC 24 |
| Peak memory | 267044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651561363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2651561363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/30.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all_with_rand_reset.4248548176 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 11803363841 ps |
| CPU time | 236.67 seconds |
| Started | Oct 12 09:56:21 AM UTC 24 |
| Finished | Oct 12 10:00:22 AM UTC 24 |
| Peak memory | 279380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4248548176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.a lert_handler_stress_all_with_rand_reset.4248548176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/30.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/31.alert_handler_entropy.2938315619 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 15998081457 ps |
| CPU time | 1060.64 seconds |
| Started | Oct 12 09:57:51 AM UTC 24 |
| Finished | Oct 12 10:15:45 AM UTC 24 |
| Peak memory | 293656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938315619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2938315619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/31.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_alert_accum.609677466 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 3033622548 ps |
| CPU time | 206.83 seconds |
| Started | Oct 12 09:57:29 AM UTC 24 |
| Finished | Oct 12 10:00:59 AM UTC 24 |
| Peak memory | 267232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609677466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.609677466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/31.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_intr_timeout.47803712 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 3911588710 ps |
| CPU time | 50.65 seconds |
| Started | Oct 12 09:57:16 AM UTC 24 |
| Finished | Oct 12 09:58:09 AM UTC 24 |
| Peak memory | 267292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47803712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc _intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.47803712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/31.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg.743068580 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 8195265815 ps |
| CPU time | 819.83 seconds |
| Started | Oct 12 09:58:11 AM UTC 24 |
| Finished | Oct 12 10:12:01 AM UTC 24 |
| Peak memory | 283376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743068580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.743068580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/31.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg_stub_clk.1511217456 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 100672435441 ps |
| CPU time | 1297.98 seconds |
| Started | Oct 12 09:58:32 AM UTC 24 |
| Finished | Oct 12 10:20:26 AM UTC 24 |
| Peak memory | 300068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511217456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1511217456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/31.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/31.alert_handler_ping_timeout.778778007 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 9174108265 ps |
| CPU time | 414.16 seconds |
| Started | Oct 12 09:58:10 AM UTC 24 |
| Finished | Oct 12 10:05:10 AM UTC 24 |
| Peak memory | 260968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778778007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.778778007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/31.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_alerts.2460100176 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 845909983 ps |
| CPU time | 32.42 seconds |
| Started | Oct 12 09:56:55 AM UTC 24 |
| Finished | Oct 12 09:57:29 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460100176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2460100176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/31.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_classes.3963668661 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 63046253 ps |
| CPU time | 7.35 seconds |
| Started | Oct 12 09:57:07 AM UTC 24 |
| Finished | Oct 12 09:57:15 AM UTC 24 |
| Peak memory | 250588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963668661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3963668661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/31.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/31.alert_handler_sig_int_fail.3309046779 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 373429186 ps |
| CPU time | 33.99 seconds |
| Started | Oct 12 09:57:35 AM UTC 24 |
| Finished | Oct 12 09:58:11 AM UTC 24 |
| Peak memory | 261092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309046779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3309046779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/31.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/31.alert_handler_smoke.3869219379 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 2954254008 ps |
| CPU time | 53.8 seconds |
| Started | Oct 12 09:56:40 AM UTC 24 |
| Finished | Oct 12 09:57:35 AM UTC 24 |
| Peak memory | 267044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869219379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3869219379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/31.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all.125146496 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 126185243840 ps |
| CPU time | 4112.8 seconds |
| Started | Oct 12 09:58:41 AM UTC 24 |
| Finished | Oct 12 11:08:04 AM UTC 24 |
| Peak memory | 302228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125146496 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_stress_all.125146496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/31.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all_with_rand_reset.517293348 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 23083518382 ps |
| CPU time | 445.36 seconds |
| Started | Oct 12 09:59:02 AM UTC 24 |
| Finished | Oct 12 10:06:33 AM UTC 24 |
| Peak memory | 283752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=517293348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.al ert_handler_stress_all_with_rand_reset.517293348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/32.alert_handler_entropy.1538693585 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 49591671682 ps |
| CPU time | 1363.27 seconds |
| Started | Oct 12 10:00:35 AM UTC 24 |
| Finished | Oct 12 10:23:35 AM UTC 24 |
| Peak memory | 293608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538693585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1538693585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/32.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_alert_accum.2481662120 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 191623180 ps |
| CPU time | 10.04 seconds |
| Started | Oct 12 10:00:23 AM UTC 24 |
| Finished | Oct 12 10:00:34 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481662120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2481662120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/32.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_intr_timeout.3167377288 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 663669710 ps |
| CPU time | 55.15 seconds |
| Started | Oct 12 10:00:23 AM UTC 24 |
| Finished | Oct 12 10:01:20 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167377288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3167377288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/32.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg.3136673400 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 12534493012 ps |
| CPU time | 1031.46 seconds |
| Started | Oct 12 10:00:44 AM UTC 24 |
| Finished | Oct 12 10:18:08 AM UTC 24 |
| Peak memory | 283356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136673400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3136673400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/32.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg_stub_clk.3314004550 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 34337274465 ps |
| CPU time | 1939.56 seconds |
| Started | Oct 12 10:00:51 AM UTC 24 |
| Finished | Oct 12 10:33:33 AM UTC 24 |
| Peak memory | 283436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314004550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3314004550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/32.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/32.alert_handler_ping_timeout.3848290059 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 125654387993 ps |
| CPU time | 597.67 seconds |
| Started | Oct 12 10:00:37 AM UTC 24 |
| Finished | Oct 12 10:10:42 AM UTC 24 |
| Peak memory | 260840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848290059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3848290059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/32.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_alerts.536846622 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 1250013499 ps |
| CPU time | 94.07 seconds |
| Started | Oct 12 09:59:57 AM UTC 24 |
| Finished | Oct 12 10:01:34 AM UTC 24 |
| Peak memory | 267172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536846622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.536846622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/32.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_classes.1723657252 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 503485612 ps |
| CPU time | 40.01 seconds |
| Started | Oct 12 10:00:07 AM UTC 24 |
| Finished | Oct 12 10:00:49 AM UTC 24 |
| Peak memory | 260760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723657252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1723657252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/32.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/32.alert_handler_sig_int_fail.3656410325 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 120098819 ps |
| CPU time | 19.9 seconds |
| Started | Oct 12 10:00:30 AM UTC 24 |
| Finished | Oct 12 10:00:51 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656410325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3656410325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/32.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/32.alert_handler_smoke.2634358266 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 466142530 ps |
| CPU time | 36.4 seconds |
| Started | Oct 12 09:59:51 AM UTC 24 |
| Finished | Oct 12 10:00:29 AM UTC 24 |
| Peak memory | 266908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634358266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2634358266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/32.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all.2662792724 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 38528105275 ps |
| CPU time | 1006.95 seconds |
| Started | Oct 12 10:00:51 AM UTC 24 |
| Finished | Oct 12 10:17:50 AM UTC 24 |
| Peak memory | 293596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662792724 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_stress_all.2662792724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/32.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all_with_rand_reset.3685779646 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 12943533173 ps |
| CPU time | 98.06 seconds |
| Started | Oct 12 10:00:52 AM UTC 24 |
| Finished | Oct 12 10:02:33 AM UTC 24 |
| Peak memory | 277328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3685779646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.a lert_handler_stress_all_with_rand_reset.3685779646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/32.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/33.alert_handler_entropy.107908256 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 45205165116 ps |
| CPU time | 755.57 seconds |
| Started | Oct 12 10:01:44 AM UTC 24 |
| Finished | Oct 12 10:14:29 AM UTC 24 |
| Peak memory | 283492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107908256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.107908256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/33.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_alert_accum.4009546870 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 1118381006 ps |
| CPU time | 124.16 seconds |
| Started | Oct 12 10:01:35 AM UTC 24 |
| Finished | Oct 12 10:03:42 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009546870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.4009546870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/33.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_intr_timeout.2814643103 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 554932890 ps |
| CPU time | 25.76 seconds |
| Started | Oct 12 10:01:20 AM UTC 24 |
| Finished | Oct 12 10:01:48 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814643103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2814643103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/33.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg_stub_clk.3664591200 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 79268975783 ps |
| CPU time | 2679.23 seconds |
| Started | Oct 12 10:02:07 AM UTC 24 |
| Finished | Oct 12 10:47:17 AM UTC 24 |
| Peak memory | 302580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664591200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3664591200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/33.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/33.alert_handler_ping_timeout.1583228055 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 2201665605 ps |
| CPU time | 72.47 seconds |
| Started | Oct 12 10:01:49 AM UTC 24 |
| Finished | Oct 12 10:03:03 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583228055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1583228055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_alerts.3242970837 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 2309540423 ps |
| CPU time | 45.79 seconds |
| Started | Oct 12 10:00:55 AM UTC 24 |
| Finished | Oct 12 10:01:42 AM UTC 24 |
| Peak memory | 267036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242970837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.3242970837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/33.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_classes.3388840611 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1803169221 ps |
| CPU time | 74.2 seconds |
| Started | Oct 12 10:01:00 AM UTC 24 |
| Finished | Oct 12 10:02:16 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388840611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3388840611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/33.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/33.alert_handler_sig_int_fail.1001105574 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 173062769 ps |
| CPU time | 6.8 seconds |
| Started | Oct 12 10:01:43 AM UTC 24 |
| Finished | Oct 12 10:01:51 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001105574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1001105574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/33.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/33.alert_handler_smoke.3051179888 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 1030132153 ps |
| CPU time | 46.98 seconds |
| Started | Oct 12 10:00:55 AM UTC 24 |
| Finished | Oct 12 10:01:43 AM UTC 24 |
| Peak memory | 266980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051179888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3051179888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/33.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all.166420805 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 249846904 ps |
| CPU time | 15.45 seconds |
| Started | Oct 12 10:02:17 AM UTC 24 |
| Finished | Oct 12 10:02:34 AM UTC 24 |
| Peak memory | 264860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166420805 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_stress_all.166420805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/33.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/34.alert_handler_entropy.1081878340 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 37719364947 ps |
| CPU time | 2530.3 seconds |
| Started | Oct 12 10:03:23 AM UTC 24 |
| Finished | Oct 12 10:46:03 AM UTC 24 |
| Peak memory | 296236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081878340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1081878340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/34.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_alert_accum.4164359780 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 1008021304 ps |
| CPU time | 74.83 seconds |
| Started | Oct 12 10:03:07 AM UTC 24 |
| Finished | Oct 12 10:04:23 AM UTC 24 |
| Peak memory | 267100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164359780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.4164359780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/34.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_intr_timeout.900789451 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 681960331 ps |
| CPU time | 16.4 seconds |
| Started | Oct 12 10:03:04 AM UTC 24 |
| Finished | Oct 12 10:03:22 AM UTC 24 |
| Peak memory | 261024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900789451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.900789451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/34.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg.890425966 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 22353526470 ps |
| CPU time | 1589.63 seconds |
| Started | Oct 12 10:03:36 AM UTC 24 |
| Finished | Oct 12 10:30:24 AM UTC 24 |
| Peak memory | 277272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890425966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.890425966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/34.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg_stub_clk.3492618690 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 45543982701 ps |
| CPU time | 1145.71 seconds |
| Started | Oct 12 10:03:42 AM UTC 24 |
| Finished | Oct 12 10:23:02 AM UTC 24 |
| Peak memory | 281324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492618690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3492618690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/34.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/34.alert_handler_ping_timeout.4151343580 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 28776295359 ps |
| CPU time | 149.7 seconds |
| Started | Oct 12 10:03:36 AM UTC 24 |
| Finished | Oct 12 10:06:08 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151343580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.4151343580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/34.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_alerts.870075071 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1373555047 ps |
| CPU time | 43.72 seconds |
| Started | Oct 12 10:02:48 AM UTC 24 |
| Finished | Oct 12 10:03:33 AM UTC 24 |
| Peak memory | 266944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870075071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.870075071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/34.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_classes.701165470 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 549166074 ps |
| CPU time | 21.75 seconds |
| Started | Oct 12 10:02:57 AM UTC 24 |
| Finished | Oct 12 10:03:21 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701165470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.701165470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/34.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/34.alert_handler_sig_int_fail.2662272591 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 916401376 ps |
| CPU time | 23.32 seconds |
| Started | Oct 12 10:03:22 AM UTC 24 |
| Finished | Oct 12 10:03:46 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662272591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2662272591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/34.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/34.alert_handler_smoke.2563891870 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 1091424014 ps |
| CPU time | 19.74 seconds |
| Started | Oct 12 10:02:35 AM UTC 24 |
| Finished | Oct 12 10:02:56 AM UTC 24 |
| Peak memory | 266980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563891870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2563891870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/34.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all.1925419717 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 105152457 ps |
| CPU time | 13.73 seconds |
| Started | Oct 12 10:03:47 AM UTC 24 |
| Finished | Oct 12 10:04:02 AM UTC 24 |
| Peak memory | 261092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925419717 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_stress_all.1925419717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/34.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/35.alert_handler_entropy.3610463934 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 52038248285 ps |
| CPU time | 1594.99 seconds |
| Started | Oct 12 10:04:20 AM UTC 24 |
| Finished | Oct 12 10:31:14 AM UTC 24 |
| Peak memory | 283356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610463934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.3610463934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/35.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_alert_accum.1678617864 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1476453187 ps |
| CPU time | 20.68 seconds |
| Started | Oct 12 10:04:03 AM UTC 24 |
| Finished | Oct 12 10:04:25 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678617864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1678617864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/35.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_intr_timeout.3977589944 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 735987719 ps |
| CPU time | 20.71 seconds |
| Started | Oct 12 10:04:01 AM UTC 24 |
| Finished | Oct 12 10:04:23 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977589944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3977589944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/35.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg.3624550876 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 68529996623 ps |
| CPU time | 3486.61 seconds |
| Started | Oct 12 10:04:25 AM UTC 24 |
| Finished | Oct 12 11:03:14 AM UTC 24 |
| Peak memory | 302252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624550876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3624550876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/35.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg_stub_clk.800839093 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 52119433251 ps |
| CPU time | 1077.13 seconds |
| Started | Oct 12 10:04:26 AM UTC 24 |
| Finished | Oct 12 10:22:38 AM UTC 24 |
| Peak memory | 295736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800839093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.800839093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/35.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/35.alert_handler_ping_timeout.383748051 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 7971696304 ps |
| CPU time | 310.86 seconds |
| Started | Oct 12 10:04:23 AM UTC 24 |
| Finished | Oct 12 10:09:39 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383748051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.383748051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/35.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_alerts.846597748 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 1735410050 ps |
| CPU time | 70.3 seconds |
| Started | Oct 12 10:03:56 AM UTC 24 |
| Finished | Oct 12 10:05:09 AM UTC 24 |
| Peak memory | 267012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846597748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.846597748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/35.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_classes.1537880271 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 193770221 ps |
| CPU time | 18.75 seconds |
| Started | Oct 12 10:04:00 AM UTC 24 |
| Finished | Oct 12 10:04:20 AM UTC 24 |
| Peak memory | 265116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537880271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1537880271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/35.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/35.alert_handler_smoke.87178591 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 647452771 ps |
| CPU time | 18.16 seconds |
| Started | Oct 12 10:03:52 AM UTC 24 |
| Finished | Oct 12 10:04:12 AM UTC 24 |
| Peak memory | 267040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87178591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smo ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.87178591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/35.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all.2076581545 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 181655224144 ps |
| CPU time | 3322.65 seconds |
| Started | Oct 12 10:04:30 AM UTC 24 |
| Finished | Oct 12 11:00:33 AM UTC 24 |
| Peak memory | 314592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076581545 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_stress_all.2076581545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/35.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/36.alert_handler_entropy.1035774524 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 103488745311 ps |
| CPU time | 1796.27 seconds |
| Started | Oct 12 10:05:26 AM UTC 24 |
| Finished | Oct 12 10:35:43 AM UTC 24 |
| Peak memory | 295864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035774524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1035774524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/36.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_alert_accum.179885514 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 15304080731 ps |
| CPU time | 127.64 seconds |
| Started | Oct 12 10:05:15 AM UTC 24 |
| Finished | Oct 12 10:07:25 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179885514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.179885514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/36.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_intr_timeout.74449650 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 622974364 ps |
| CPU time | 61.08 seconds |
| Started | Oct 12 10:05:11 AM UTC 24 |
| Finished | Oct 12 10:06:14 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74449650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc _intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.74449650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/36.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg.687813868 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 49697021512 ps |
| CPU time | 1423.5 seconds |
| Started | Oct 12 10:05:48 AM UTC 24 |
| Finished | Oct 12 10:29:48 AM UTC 24 |
| Peak memory | 283436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687813868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.687813868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/36.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg_stub_clk.3008072749 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 19725544665 ps |
| CPU time | 967.12 seconds |
| Started | Oct 12 10:06:10 AM UTC 24 |
| Finished | Oct 12 10:22:29 AM UTC 24 |
| Peak memory | 283372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008072749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3008072749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/36.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/36.alert_handler_ping_timeout.2214344168 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 32462444602 ps |
| CPU time | 346.19 seconds |
| Started | Oct 12 10:05:46 AM UTC 24 |
| Finished | Oct 12 10:11:37 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214344168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2214344168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/36.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_alerts.2482198198 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 2853105197 ps |
| CPU time | 36.48 seconds |
| Started | Oct 12 10:05:07 AM UTC 24 |
| Finished | Oct 12 10:05:46 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482198198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2482198198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/36.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_classes.3135379296 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1184711207 ps |
| CPU time | 36.34 seconds |
| Started | Oct 12 10:05:09 AM UTC 24 |
| Finished | Oct 12 10:05:47 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135379296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3135379296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/36.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/36.alert_handler_sig_int_fail.760857631 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 289404267 ps |
| CPU time | 48.06 seconds |
| Started | Oct 12 10:05:21 AM UTC 24 |
| Finished | Oct 12 10:06:11 AM UTC 24 |
| Peak memory | 267008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760857631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.760857631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/36.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/36.alert_handler_smoke.2665143998 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 869687161 ps |
| CPU time | 26.53 seconds |
| Started | Oct 12 10:04:46 AM UTC 24 |
| Finished | Oct 12 10:05:14 AM UTC 24 |
| Peak memory | 266912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665143998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2665143998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/36.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all.3101573453 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 4652442865 ps |
| CPU time | 268.39 seconds |
| Started | Oct 12 10:06:12 AM UTC 24 |
| Finished | Oct 12 10:10:45 AM UTC 24 |
| Peak memory | 264920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101573453 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_stress_all.3101573453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/36.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/37.alert_handler_entropy.1398300822 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 227170149031 ps |
| CPU time | 2582.45 seconds |
| Started | Oct 12 10:07:21 AM UTC 24 |
| Finished | Oct 12 10:50:54 AM UTC 24 |
| Peak memory | 298416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398300822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1398300822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/37.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_alert_accum.3309034502 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 23245701184 ps |
| CPU time | 375.43 seconds |
| Started | Oct 12 10:06:37 AM UTC 24 |
| Finished | Oct 12 10:12:57 AM UTC 24 |
| Peak memory | 266968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309034502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3309034502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/37.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_intr_timeout.3073483150 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 929123806 ps |
| CPU time | 56.96 seconds |
| Started | Oct 12 10:06:35 AM UTC 24 |
| Finished | Oct 12 10:07:33 AM UTC 24 |
| Peak memory | 260752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073483150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3073483150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/37.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg_stub_clk.1179244823 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 440986236583 ps |
| CPU time | 2208.35 seconds |
| Started | Oct 12 10:07:31 AM UTC 24 |
| Finished | Oct 12 10:44:46 AM UTC 24 |
| Peak memory | 296152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179244823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1179244823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/37.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/37.alert_handler_ping_timeout.3112387230 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 20033945821 ps |
| CPU time | 367.61 seconds |
| Started | Oct 12 10:07:26 AM UTC 24 |
| Finished | Oct 12 10:13:39 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112387230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3112387230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_alerts.2855924022 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 292627554 ps |
| CPU time | 39.78 seconds |
| Started | Oct 12 10:06:23 AM UTC 24 |
| Finished | Oct 12 10:07:05 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855924022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2855924022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/37.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_classes.3285581327 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 2070532847 ps |
| CPU time | 56.58 seconds |
| Started | Oct 12 10:06:31 AM UTC 24 |
| Finished | Oct 12 10:07:30 AM UTC 24 |
| Peak memory | 260764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285581327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3285581327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/37.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/37.alert_handler_sig_int_fail.3349709392 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 935408213 ps |
| CPU time | 23.27 seconds |
| Started | Oct 12 10:07:05 AM UTC 24 |
| Finished | Oct 12 10:07:30 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349709392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3349709392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/37.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/37.alert_handler_smoke.1388234194 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 122510458 ps |
| CPU time | 12.08 seconds |
| Started | Oct 12 10:06:22 AM UTC 24 |
| Finished | Oct 12 10:06:36 AM UTC 24 |
| Peak memory | 262812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388234194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1388234194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/37.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/37.alert_handler_stress_all.2729139426 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 593089637 ps |
| CPU time | 27.99 seconds |
| Started | Oct 12 10:07:35 AM UTC 24 |
| Finished | Oct 12 10:08:04 AM UTC 24 |
| Peak memory | 260764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729139426 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_stress_all.2729139426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/37.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/38.alert_handler_entropy.537521590 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 197235791182 ps |
| CPU time | 2690.92 seconds |
| Started | Oct 12 10:10:14 AM UTC 24 |
| Finished | Oct 12 10:55:38 AM UTC 24 |
| Peak memory | 300528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537521590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.537521590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/38.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_alert_accum.876546166 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1442798866 ps |
| CPU time | 118.42 seconds |
| Started | Oct 12 10:09:56 AM UTC 24 |
| Finished | Oct 12 10:11:57 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876546166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.876546166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/38.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_intr_timeout.2815541571 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 471635337 ps |
| CPU time | 29.58 seconds |
| Started | Oct 12 10:09:39 AM UTC 24 |
| Finished | Oct 12 10:10:10 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815541571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2815541571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/38.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg.1054823267 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 62580789599 ps |
| CPU time | 1280 seconds |
| Started | Oct 12 10:10:26 AM UTC 24 |
| Finished | Oct 12 10:32:01 AM UTC 24 |
| Peak memory | 283364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054823267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1054823267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/38.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg_stub_clk.2121928509 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 10679460118 ps |
| CPU time | 1434.97 seconds |
| Started | Oct 12 10:10:36 AM UTC 24 |
| Finished | Oct 12 10:34:49 AM UTC 24 |
| Peak memory | 300024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121928509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2121928509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/38.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/38.alert_handler_ping_timeout.48256122 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 23158590540 ps |
| CPU time | 429.28 seconds |
| Started | Oct 12 10:10:25 AM UTC 24 |
| Finished | Oct 12 10:17:40 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48256122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.48256122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_alerts.4158321599 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 1554246944 ps |
| CPU time | 78.66 seconds |
| Started | Oct 12 10:08:52 AM UTC 24 |
| Finished | Oct 12 10:10:13 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158321599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.4158321599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/38.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_classes.2128599760 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 343655395 ps |
| CPU time | 41.64 seconds |
| Started | Oct 12 10:09:12 AM UTC 24 |
| Finished | Oct 12 10:09:55 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128599760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2128599760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/38.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/38.alert_handler_sig_int_fail.3667628533 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 200116115 ps |
| CPU time | 11.5 seconds |
| Started | Oct 12 10:10:12 AM UTC 24 |
| Finished | Oct 12 10:10:24 AM UTC 24 |
| Peak memory | 266904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667628533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3667628533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/38.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/38.alert_handler_smoke.3869981247 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 111643476 ps |
| CPU time | 16.2 seconds |
| Started | Oct 12 10:08:34 AM UTC 24 |
| Finished | Oct 12 10:08:51 AM UTC 24 |
| Peak memory | 266980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869981247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3869981247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/38.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all.1282698817 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 11248165521 ps |
| CPU time | 1044.82 seconds |
| Started | Oct 12 10:10:43 AM UTC 24 |
| Finished | Oct 12 10:28:20 AM UTC 24 |
| Peak memory | 300004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282698817 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_stress_all.1282698817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/38.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_alert_accum.1274290980 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 3450515978 ps |
| CPU time | 206.29 seconds |
| Started | Oct 12 10:11:58 AM UTC 24 |
| Finished | Oct 12 10:15:28 AM UTC 24 |
| Peak memory | 267036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274290980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1274290980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/39.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_intr_timeout.3862085532 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 5896802079 ps |
| CPU time | 47.26 seconds |
| Started | Oct 12 10:11:48 AM UTC 24 |
| Finished | Oct 12 10:12:36 AM UTC 24 |
| Peak memory | 260816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862085532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3862085532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/39.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg.2489558264 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 55571989750 ps |
| CPU time | 3000.83 seconds |
| Started | Oct 12 10:12:35 AM UTC 24 |
| Finished | Oct 12 11:03:12 AM UTC 24 |
| Peak memory | 302232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489558264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2489558264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/39.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg_stub_clk.3171020810 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 19871980957 ps |
| CPU time | 1092.01 seconds |
| Started | Oct 12 10:12:38 AM UTC 24 |
| Finished | Oct 12 10:31:02 AM UTC 24 |
| Peak memory | 299760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171020810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3171020810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/39.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/39.alert_handler_ping_timeout.414068341 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 7133205536 ps |
| CPU time | 310.58 seconds |
| Started | Oct 12 10:12:16 AM UTC 24 |
| Finished | Oct 12 10:17:31 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414068341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.414068341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/39.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_alerts.1048641002 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 895448440 ps |
| CPU time | 32.72 seconds |
| Started | Oct 12 10:11:12 AM UTC 24 |
| Finished | Oct 12 10:11:47 AM UTC 24 |
| Peak memory | 267228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048641002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1048641002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/39.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_classes.2370563434 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 6914063469 ps |
| CPU time | 35.11 seconds |
| Started | Oct 12 10:11:38 AM UTC 24 |
| Finished | Oct 12 10:12:15 AM UTC 24 |
| Peak memory | 267040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370563434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2370563434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/39.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/39.alert_handler_sig_int_fail.2957378113 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 586291298 ps |
| CPU time | 32.22 seconds |
| Started | Oct 12 10:12:01 AM UTC 24 |
| Finished | Oct 12 10:12:35 AM UTC 24 |
| Peak memory | 267232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957378113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2957378113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/39.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/39.alert_handler_smoke.2894272922 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 1524923007 ps |
| CPU time | 59.15 seconds |
| Started | Oct 12 10:10:59 AM UTC 24 |
| Finished | Oct 12 10:12:00 AM UTC 24 |
| Peak memory | 260764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894272922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2894272922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/39.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all.1876660470 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 274889777416 ps |
| CPU time | 3272.37 seconds |
| Started | Oct 12 10:12:58 AM UTC 24 |
| Finished | Oct 12 11:08:11 AM UTC 24 |
| Peak memory | 302228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876660470 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_stress_all.1876660470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/39.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all_with_rand_reset.353608884 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 6430290324 ps |
| CPU time | 162.17 seconds |
| Started | Oct 12 10:13:39 AM UTC 24 |
| Finished | Oct 12 10:16:24 AM UTC 24 |
| Peak memory | 277340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=353608884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.al ert_handler_stress_all_with_rand_reset.353608884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/39.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/4.alert_handler_alert_accum_saturation.1054109213 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 143529887 ps |
| CPU time | 5.2 seconds |
| Started | Oct 12 09:04:49 AM UTC 24 |
| Finished | Oct 12 09:04:56 AM UTC 24 |
| Peak memory | 261040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054109213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1054109213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy.1726875823 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 269557282861 ps |
| CPU time | 2356.23 seconds |
| Started | Oct 12 09:04:22 AM UTC 24 |
| Finished | Oct 12 09:44:04 AM UTC 24 |
| Peak memory | 299892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726875823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1726875823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy_stress.4098470501 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 437099359 ps |
| CPU time | 19.02 seconds |
| Started | Oct 12 09:04:47 AM UTC 24 |
| Finished | Oct 12 09:05:07 AM UTC 24 |
| Peak memory | 261032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098470501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.4098470501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_alert_accum.2024771960 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 597315322 ps |
| CPU time | 59.39 seconds |
| Started | Oct 12 09:04:18 AM UTC 24 |
| Finished | Oct 12 09:05:19 AM UTC 24 |
| Peak memory | 266896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024771960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2024771960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_intr_timeout.498368502 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 373197285 ps |
| CPU time | 31.85 seconds |
| Started | Oct 12 09:04:15 AM UTC 24 |
| Finished | Oct 12 09:04:48 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498368502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.498368502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg.2913408440 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 243290197038 ps |
| CPU time | 3291.26 seconds |
| Started | Oct 12 09:04:28 AM UTC 24 |
| Finished | Oct 12 09:59:54 AM UTC 24 |
| Peak memory | 299740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913408440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2913408440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg_stub_clk.2382880870 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 10915263971 ps |
| CPU time | 1221.29 seconds |
| Started | Oct 12 09:04:43 AM UTC 24 |
| Finished | Oct 12 09:25:20 AM UTC 24 |
| Peak memory | 300144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382880870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2382880870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/4.alert_handler_ping_timeout.409911000 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 4656823003 ps |
| CPU time | 164.35 seconds |
| Started | Oct 12 09:04:23 AM UTC 24 |
| Finished | Oct 12 09:07:10 AM UTC 24 |
| Peak memory | 261096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409911000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.409911000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_alerts.4224890591 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 874008768 ps |
| CPU time | 35.53 seconds |
| Started | Oct 12 09:04:11 AM UTC 24 |
| Finished | Oct 12 09:04:48 AM UTC 24 |
| Peak memory | 260868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224890591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.4224890591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_classes.702021034 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 412688389 ps |
| CPU time | 8.92 seconds |
| Started | Oct 12 09:04:11 AM UTC 24 |
| Finished | Oct 12 09:04:21 AM UTC 24 |
| Peak memory | 262880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702021034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.702021034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/4.alert_handler_sec_cm.357580968 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 804448918 ps |
| CPU time | 18.92 seconds |
| Started | Oct 12 09:04:53 AM UTC 24 |
| Finished | Oct 12 09:05:13 AM UTC 24 |
| Peak memory | 295056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357580968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_h andler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.357580968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/4.alert_handler_sig_int_fail.2767427578 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 4581145434 ps |
| CPU time | 29.81 seconds |
| Started | Oct 12 09:04:21 AM UTC 24 |
| Finished | Oct 12 09:04:52 AM UTC 24 |
| Peak memory | 267072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767427578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2767427578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/4.alert_handler_smoke.984658236 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 302593691 ps |
| CPU time | 43.93 seconds |
| Started | Oct 12 09:04:09 AM UTC 24 |
| Finished | Oct 12 09:04:54 AM UTC 24 |
| Peak memory | 266908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984658236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.984658236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/4.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/40.alert_handler_entropy.3603847789 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 147554855380 ps |
| CPU time | 2537.27 seconds |
| Started | Oct 12 10:14:35 AM UTC 24 |
| Finished | Oct 12 10:57:24 AM UTC 24 |
| Peak memory | 298208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603847789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3603847789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/40.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_alert_accum.2768106096 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 8558969897 ps |
| CPU time | 197.64 seconds |
| Started | Oct 12 10:14:17 AM UTC 24 |
| Finished | Oct 12 10:17:38 AM UTC 24 |
| Peak memory | 267036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768106096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2768106096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/40.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_intr_timeout.3996411461 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 140338992 ps |
| CPU time | 12.46 seconds |
| Started | Oct 12 10:14:03 AM UTC 24 |
| Finished | Oct 12 10:14:16 AM UTC 24 |
| Peak memory | 262876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996411461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3996411461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/40.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg_stub_clk.664263287 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 18395219861 ps |
| CPU time | 1624.23 seconds |
| Started | Oct 12 10:14:55 AM UTC 24 |
| Finished | Oct 12 10:42:19 AM UTC 24 |
| Peak memory | 299816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664263287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.664263287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/40.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/40.alert_handler_ping_timeout.1847035723 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 23703538253 ps |
| CPU time | 173.43 seconds |
| Started | Oct 12 10:14:45 AM UTC 24 |
| Finished | Oct 12 10:17:42 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847035723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1847035723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/40.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_alerts.2391012141 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 494691426 ps |
| CPU time | 41.38 seconds |
| Started | Oct 12 10:13:51 AM UTC 24 |
| Finished | Oct 12 10:14:34 AM UTC 24 |
| Peak memory | 267164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391012141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2391012141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/40.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_classes.3628001189 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 859961856 ps |
| CPU time | 59.14 seconds |
| Started | Oct 12 10:13:53 AM UTC 24 |
| Finished | Oct 12 10:14:53 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628001189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3628001189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/40.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/40.alert_handler_sig_int_fail.2508312571 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 536738914 ps |
| CPU time | 17.74 seconds |
| Started | Oct 12 10:14:30 AM UTC 24 |
| Finished | Oct 12 10:14:49 AM UTC 24 |
| Peak memory | 261024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508312571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2508312571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/40.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/40.alert_handler_smoke.3630497567 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 485337708 ps |
| CPU time | 9.68 seconds |
| Started | Oct 12 10:13:51 AM UTC 24 |
| Finished | Oct 12 10:14:02 AM UTC 24 |
| Peak memory | 260764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630497567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3630497567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/40.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all.724191632 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 97129202344 ps |
| CPU time | 2850.19 seconds |
| Started | Oct 12 10:15:29 AM UTC 24 |
| Finished | Oct 12 11:03:35 AM UTC 24 |
| Peak memory | 302320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724191632 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_stress_all.724191632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/40.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all_with_rand_reset.1867420041 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 2654817898 ps |
| CPU time | 213.36 seconds |
| Started | Oct 12 10:15:49 AM UTC 24 |
| Finished | Oct 12 10:19:26 AM UTC 24 |
| Peak memory | 279456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1867420041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.a lert_handler_stress_all_with_rand_reset.1867420041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/41.alert_handler_entropy.3673563568 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 26109578520 ps |
| CPU time | 2007.98 seconds |
| Started | Oct 12 10:17:03 AM UTC 24 |
| Finished | Oct 12 10:50:56 AM UTC 24 |
| Peak memory | 293684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673563568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3673563568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/41.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_alert_accum.4203711219 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 8206104714 ps |
| CPU time | 270.08 seconds |
| Started | Oct 12 10:16:40 AM UTC 24 |
| Finished | Oct 12 10:21:14 AM UTC 24 |
| Peak memory | 262872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203711219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.4203711219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/41.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_intr_timeout.1835470630 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 1155951846 ps |
| CPU time | 46.99 seconds |
| Started | Oct 12 10:16:35 AM UTC 24 |
| Finished | Oct 12 10:17:23 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835470630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1835470630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/41.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg.3325227363 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 81734284785 ps |
| CPU time | 1211.94 seconds |
| Started | Oct 12 10:17:24 AM UTC 24 |
| Finished | Oct 12 10:37:51 AM UTC 24 |
| Peak memory | 283436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325227363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3325227363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/41.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg_stub_clk.1336741546 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 12761101332 ps |
| CPU time | 614.78 seconds |
| Started | Oct 12 10:17:25 AM UTC 24 |
| Finished | Oct 12 10:27:47 AM UTC 24 |
| Peak memory | 283364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336741546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1336741546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/41.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/41.alert_handler_ping_timeout.3102632955 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 31171429127 ps |
| CPU time | 336.52 seconds |
| Started | Oct 12 10:17:07 AM UTC 24 |
| Finished | Oct 12 10:22:48 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102632955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3102632955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/41.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_alerts.907937601 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 1689589507 ps |
| CPU time | 54.19 seconds |
| Started | Oct 12 10:16:06 AM UTC 24 |
| Finished | Oct 12 10:17:02 AM UTC 24 |
| Peak memory | 260764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907937601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.907937601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/41.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_classes.1103916128 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 265845711 ps |
| CPU time | 39.72 seconds |
| Started | Oct 12 10:16:26 AM UTC 24 |
| Finished | Oct 12 10:17:07 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103916128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1103916128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/41.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/41.alert_handler_sig_int_fail.446589471 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 880661475 ps |
| CPU time | 66.6 seconds |
| Started | Oct 12 10:16:43 AM UTC 24 |
| Finished | Oct 12 10:17:51 AM UTC 24 |
| Peak memory | 260784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446589471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.446589471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/41.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/41.alert_handler_smoke.2616061773 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 796471306 ps |
| CPU time | 42.78 seconds |
| Started | Oct 12 10:15:49 AM UTC 24 |
| Finished | Oct 12 10:16:34 AM UTC 24 |
| Peak memory | 266908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616061773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2616061773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/41.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all.409475941 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 253429148772 ps |
| CPU time | 4066.33 seconds |
| Started | Oct 12 10:17:32 AM UTC 24 |
| Finished | Oct 12 11:26:11 AM UTC 24 |
| Peak memory | 302304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409475941 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_stress_all.409475941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/41.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all_with_rand_reset.3558677288 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 4085782191 ps |
| CPU time | 246.26 seconds |
| Started | Oct 12 10:17:39 AM UTC 24 |
| Finished | Oct 12 10:21:49 AM UTC 24 |
| Peak memory | 277408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3558677288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.a lert_handler_stress_all_with_rand_reset.3558677288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/41.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/42.alert_handler_entropy.1725615787 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 79550379753 ps |
| CPU time | 977.34 seconds |
| Started | Oct 12 10:18:11 AM UTC 24 |
| Finished | Oct 12 10:34:41 AM UTC 24 |
| Peak memory | 283356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725615787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1725615787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/42.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_alert_accum.680837502 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 3206076481 ps |
| CPU time | 69.94 seconds |
| Started | Oct 12 10:18:11 AM UTC 24 |
| Finished | Oct 12 10:19:23 AM UTC 24 |
| Peak memory | 267036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680837502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.680837502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/42.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_intr_timeout.893721880 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 489644633 ps |
| CPU time | 32.14 seconds |
| Started | Oct 12 10:17:53 AM UTC 24 |
| Finished | Oct 12 10:18:27 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893721880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.893721880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/42.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg_stub_clk.3506589758 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 30730393835 ps |
| CPU time | 1652.27 seconds |
| Started | Oct 12 10:18:28 AM UTC 24 |
| Finished | Oct 12 10:46:20 AM UTC 24 |
| Peak memory | 300084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506589758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3506589758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/42.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/42.alert_handler_ping_timeout.1831467354 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 10525696786 ps |
| CPU time | 411.01 seconds |
| Started | Oct 12 10:18:16 AM UTC 24 |
| Finished | Oct 12 10:25:13 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831467354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1831467354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/42.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_alerts.1801429149 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2368518744 ps |
| CPU time | 31.8 seconds |
| Started | Oct 12 10:17:42 AM UTC 24 |
| Finished | Oct 12 10:18:16 AM UTC 24 |
| Peak memory | 267036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801429149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1801429149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/42.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_classes.3918690977 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 223187771 ps |
| CPU time | 30.08 seconds |
| Started | Oct 12 10:17:52 AM UTC 24 |
| Finished | Oct 12 10:18:24 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918690977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3918690977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/42.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/42.alert_handler_sig_int_fail.1433648678 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 784460684 ps |
| CPU time | 38.36 seconds |
| Started | Oct 12 10:18:11 AM UTC 24 |
| Finished | Oct 12 10:18:51 AM UTC 24 |
| Peak memory | 266940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433648678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1433648678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/42.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/42.alert_handler_smoke.2501455106 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 205743483 ps |
| CPU time | 28.98 seconds |
| Started | Oct 12 10:17:40 AM UTC 24 |
| Finished | Oct 12 10:18:11 AM UTC 24 |
| Peak memory | 267172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501455106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2501455106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/42.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all.2954517359 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 102426253144 ps |
| CPU time | 3080.26 seconds |
| Started | Oct 12 10:18:52 AM UTC 24 |
| Finished | Oct 12 11:10:51 AM UTC 24 |
| Peak memory | 312748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954517359 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_stress_all.2954517359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/42.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/43.alert_handler_entropy.2549036631 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 172433683958 ps |
| CPU time | 2380.26 seconds |
| Started | Oct 12 10:20:02 AM UTC 24 |
| Finished | Oct 12 11:00:13 AM UTC 24 |
| Peak memory | 296164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549036631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2549036631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/43.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_alert_accum.2387413752 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 3360161096 ps |
| CPU time | 94.6 seconds |
| Started | Oct 12 10:19:53 AM UTC 24 |
| Finished | Oct 12 10:21:30 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387413752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2387413752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/43.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_intr_timeout.4147915269 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 383503768 ps |
| CPU time | 21.99 seconds |
| Started | Oct 12 10:19:45 AM UTC 24 |
| Finished | Oct 12 10:20:09 AM UTC 24 |
| Peak memory | 261024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147915269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.4147915269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/43.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg.461424666 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 33975025338 ps |
| CPU time | 2437.32 seconds |
| Started | Oct 12 10:20:15 AM UTC 24 |
| Finished | Oct 12 11:01:24 AM UTC 24 |
| Peak memory | 302228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461424666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.461424666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/43.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg_stub_clk.2527111964 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 563502721944 ps |
| CPU time | 2302.77 seconds |
| Started | Oct 12 10:20:16 AM UTC 24 |
| Finished | Oct 12 10:59:08 AM UTC 24 |
| Peak memory | 299760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527111964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2527111964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/43.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_alerts.1590210830 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 339573451 ps |
| CPU time | 35.32 seconds |
| Started | Oct 12 10:19:25 AM UTC 24 |
| Finished | Oct 12 10:20:01 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590210830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1590210830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/43.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_classes.4275160866 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 764795422 ps |
| CPU time | 23.57 seconds |
| Started | Oct 12 10:19:27 AM UTC 24 |
| Finished | Oct 12 10:19:52 AM UTC 24 |
| Peak memory | 261020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275160866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.4275160866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/43.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/43.alert_handler_sig_int_fail.1218430205 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 163499320 ps |
| CPU time | 16.82 seconds |
| Started | Oct 12 10:19:57 AM UTC 24 |
| Finished | Oct 12 10:20:16 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218430205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1218430205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/43.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/43.alert_handler_smoke.2355099882 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 2935465895 ps |
| CPU time | 62.03 seconds |
| Started | Oct 12 10:19:11 AM UTC 24 |
| Finished | Oct 12 10:20:15 AM UTC 24 |
| Peak memory | 267236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355099882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2355099882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/43.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all.1419445999 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 10747835307 ps |
| CPU time | 1125.58 seconds |
| Started | Oct 12 10:20:16 AM UTC 24 |
| Finished | Oct 12 10:39:16 AM UTC 24 |
| Peak memory | 300020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419445999 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_stress_all.1419445999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/43.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/44.alert_handler_entropy.1279727478 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 38957024529 ps |
| CPU time | 2533.46 seconds |
| Started | Oct 12 10:21:24 AM UTC 24 |
| Finished | Oct 12 11:04:10 AM UTC 24 |
| Peak memory | 296160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279727478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1279727478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/44.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_alert_accum.2615157459 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 4354024570 ps |
| CPU time | 96.4 seconds |
| Started | Oct 12 10:21:17 AM UTC 24 |
| Finished | Oct 12 10:22:56 AM UTC 24 |
| Peak memory | 267036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615157459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2615157459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/44.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_intr_timeout.586258782 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 5371697239 ps |
| CPU time | 84.72 seconds |
| Started | Oct 12 10:21:17 AM UTC 24 |
| Finished | Oct 12 10:22:44 AM UTC 24 |
| Peak memory | 261088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586258782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.586258782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/44.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg.2485183164 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 52616728645 ps |
| CPU time | 1630.1 seconds |
| Started | Oct 12 10:21:32 AM UTC 24 |
| Finished | Oct 12 10:49:03 AM UTC 24 |
| Peak memory | 299892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485183164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2485183164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/44.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg_stub_clk.2620933423 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 13660445666 ps |
| CPU time | 853.5 seconds |
| Started | Oct 12 10:21:50 AM UTC 24 |
| Finished | Oct 12 10:36:15 AM UTC 24 |
| Peak memory | 283500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620933423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2620933423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/44.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/44.alert_handler_ping_timeout.240473463 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 9752748558 ps |
| CPU time | 92.85 seconds |
| Started | Oct 12 10:21:31 AM UTC 24 |
| Finished | Oct 12 10:23:06 AM UTC 24 |
| Peak memory | 260904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240473463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.240473463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/44.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_alerts.51589741 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 464738241 ps |
| CPU time | 50.32 seconds |
| Started | Oct 12 10:20:32 AM UTC 24 |
| Finished | Oct 12 10:21:24 AM UTC 24 |
| Peak memory | 267008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51589741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ran dom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.51589741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/44.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_classes.4245984443 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 1416737866 ps |
| CPU time | 35.58 seconds |
| Started | Oct 12 10:21:16 AM UTC 24 |
| Finished | Oct 12 10:21:53 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245984443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.4245984443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/44.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/44.alert_handler_sig_int_fail.2794860877 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 72897091 ps |
| CPU time | 7.98 seconds |
| Started | Oct 12 10:21:21 AM UTC 24 |
| Finished | Oct 12 10:21:30 AM UTC 24 |
| Peak memory | 250520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794860877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2794860877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/44.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/44.alert_handler_smoke.3302640230 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 493839067 ps |
| CPU time | 43.49 seconds |
| Started | Oct 12 10:20:29 AM UTC 24 |
| Finished | Oct 12 10:21:14 AM UTC 24 |
| Peak memory | 266908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302640230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3302640230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/44.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all.630929555 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 444520354 ps |
| CPU time | 51.43 seconds |
| Started | Oct 12 10:21:54 AM UTC 24 |
| Finished | Oct 12 10:22:47 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630929555 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_stress_all.630929555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/44.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/45.alert_handler_entropy.1584089055 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 7954248024 ps |
| CPU time | 950.42 seconds |
| Started | Oct 12 10:22:57 AM UTC 24 |
| Finished | Oct 12 10:39:00 AM UTC 24 |
| Peak memory | 283744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584089055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.1584089055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/45.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_alert_accum.756710283 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 1492179864 ps |
| CPU time | 120.52 seconds |
| Started | Oct 12 10:22:49 AM UTC 24 |
| Finished | Oct 12 10:24:52 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756710283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.756710283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/45.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_intr_timeout.2360564887 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 291983791 ps |
| CPU time | 18.24 seconds |
| Started | Oct 12 10:22:48 AM UTC 24 |
| Finished | Oct 12 10:23:08 AM UTC 24 |
| Peak memory | 261084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360564887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2360564887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/45.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg_stub_clk.2280622447 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 273531973527 ps |
| CPU time | 3028.82 seconds |
| Started | Oct 12 10:23:06 AM UTC 24 |
| Finished | Oct 12 11:14:15 AM UTC 24 |
| Peak memory | 302312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280622447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2280622447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/45.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/45.alert_handler_ping_timeout.842311060 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 13980185311 ps |
| CPU time | 156.37 seconds |
| Started | Oct 12 10:22:57 AM UTC 24 |
| Finished | Oct 12 10:25:36 AM UTC 24 |
| Peak memory | 265004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842311060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.842311060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/45.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_alerts.3749764658 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 124049991 ps |
| CPU time | 14.44 seconds |
| Started | Oct 12 10:22:40 AM UTC 24 |
| Finished | Oct 12 10:22:56 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749764658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3749764658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/45.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_classes.667752508 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 125070282 ps |
| CPU time | 8.79 seconds |
| Started | Oct 12 10:22:45 AM UTC 24 |
| Finished | Oct 12 10:22:55 AM UTC 24 |
| Peak memory | 266908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667752508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.667752508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/45.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/45.alert_handler_sig_int_fail.1547704223 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 848987717 ps |
| CPU time | 79.09 seconds |
| Started | Oct 12 10:22:57 AM UTC 24 |
| Finished | Oct 12 10:24:18 AM UTC 24 |
| Peak memory | 266908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547704223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1547704223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/45.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/45.alert_handler_smoke.1243147314 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 311801065 ps |
| CPU time | 31.31 seconds |
| Started | Oct 12 10:22:37 AM UTC 24 |
| Finished | Oct 12 10:23:09 AM UTC 24 |
| Peak memory | 266980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243147314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1243147314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/45.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/45.alert_handler_stress_all.3565911361 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 35598585327 ps |
| CPU time | 776.65 seconds |
| Started | Oct 12 10:23:08 AM UTC 24 |
| Finished | Oct 12 10:36:15 AM UTC 24 |
| Peak memory | 283444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565911361 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_stress_all.3565911361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/45.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/46.alert_handler_entropy.3106296908 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 13719655547 ps |
| CPU time | 894.35 seconds |
| Started | Oct 12 10:24:35 AM UTC 24 |
| Finished | Oct 12 10:39:42 AM UTC 24 |
| Peak memory | 283440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106296908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3106296908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/46.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_alert_accum.535253202 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 1022621483 ps |
| CPU time | 86.53 seconds |
| Started | Oct 12 10:24:14 AM UTC 24 |
| Finished | Oct 12 10:25:42 AM UTC 24 |
| Peak memory | 267168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535253202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.535253202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/46.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_intr_timeout.1802338987 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 3143911781 ps |
| CPU time | 61.56 seconds |
| Started | Oct 12 10:24:04 AM UTC 24 |
| Finished | Oct 12 10:25:07 AM UTC 24 |
| Peak memory | 260820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802338987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1802338987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/46.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg.3619529756 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 102427769350 ps |
| CPU time | 3274.56 seconds |
| Started | Oct 12 10:24:52 AM UTC 24 |
| Finished | Oct 12 11:20:09 AM UTC 24 |
| Peak memory | 302232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619529756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3619529756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/46.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg_stub_clk.1789446466 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 13360676275 ps |
| CPU time | 1190.86 seconds |
| Started | Oct 12 10:24:53 AM UTC 24 |
| Finished | Oct 12 10:45:00 AM UTC 24 |
| Peak memory | 297768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789446466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1789446466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/46.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/46.alert_handler_ping_timeout.4147467350 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 195211765608 ps |
| CPU time | 361.45 seconds |
| Started | Oct 12 10:24:50 AM UTC 24 |
| Finished | Oct 12 10:30:56 AM UTC 24 |
| Peak memory | 260904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147467350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.4147467350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_alerts.3386005024 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 2039797579 ps |
| CPU time | 33.94 seconds |
| Started | Oct 12 10:23:37 AM UTC 24 |
| Finished | Oct 12 10:24:13 AM UTC 24 |
| Peak memory | 267164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386005024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3386005024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/46.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_classes.4268285583 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 1399830227 ps |
| CPU time | 62.37 seconds |
| Started | Oct 12 10:23:45 AM UTC 24 |
| Finished | Oct 12 10:24:49 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268285583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.4268285583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/46.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/46.alert_handler_sig_int_fail.1608137168 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 958273476 ps |
| CPU time | 38.65 seconds |
| Started | Oct 12 10:24:19 AM UTC 24 |
| Finished | Oct 12 10:24:59 AM UTC 24 |
| Peak memory | 266904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608137168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1608137168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/46.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/46.alert_handler_smoke.1678594954 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 932966552 ps |
| CPU time | 27.42 seconds |
| Started | Oct 12 10:23:16 AM UTC 24 |
| Finished | Oct 12 10:23:44 AM UTC 24 |
| Peak memory | 266980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678594954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1678594954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/46.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all.3742671035 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 43698913282 ps |
| CPU time | 2294.76 seconds |
| Started | Oct 12 10:25:01 AM UTC 24 |
| Finished | Oct 12 11:03:45 AM UTC 24 |
| Peak memory | 316468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742671035 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_stress_all.3742671035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/46.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/47.alert_handler_entropy.1043999964 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 83000036013 ps |
| CPU time | 2629.64 seconds |
| Started | Oct 12 10:26:11 AM UTC 24 |
| Finished | Oct 12 11:10:35 AM UTC 24 |
| Peak memory | 296100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043999964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1043999964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/47.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_alert_accum.2859472127 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 2746995014 ps |
| CPU time | 110.04 seconds |
| Started | Oct 12 10:25:44 AM UTC 24 |
| Finished | Oct 12 10:27:36 AM UTC 24 |
| Peak memory | 267232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859472127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2859472127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/47.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_intr_timeout.4163839387 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 331792739 ps |
| CPU time | 27.6 seconds |
| Started | Oct 12 10:25:41 AM UTC 24 |
| Finished | Oct 12 10:26:10 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163839387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.4163839387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/47.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg.2882807692 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 11601970942 ps |
| CPU time | 974.07 seconds |
| Started | Oct 12 10:27:07 AM UTC 24 |
| Finished | Oct 12 10:43:34 AM UTC 24 |
| Peak memory | 283356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882807692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2882807692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/47.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg_stub_clk.157037464 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 9342793983 ps |
| CPU time | 832.26 seconds |
| Started | Oct 12 10:27:37 AM UTC 24 |
| Finished | Oct 12 10:41:41 AM UTC 24 |
| Peak memory | 283432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157037464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.157037464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/47.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/47.alert_handler_ping_timeout.3587454609 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 222235494122 ps |
| CPU time | 614.05 seconds |
| Started | Oct 12 10:26:22 AM UTC 24 |
| Finished | Oct 12 10:36:44 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587454609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3587454609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/47.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_alerts.4003628056 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 63837167 ps |
| CPU time | 7.65 seconds |
| Started | Oct 12 10:25:32 AM UTC 24 |
| Finished | Oct 12 10:25:41 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003628056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.4003628056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/47.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_classes.3753922308 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 401091448 ps |
| CPU time | 20.47 seconds |
| Started | Oct 12 10:25:37 AM UTC 24 |
| Finished | Oct 12 10:25:59 AM UTC 24 |
| Peak memory | 260760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753922308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3753922308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/47.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/47.alert_handler_sig_int_fail.2547810165 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 2149698539 ps |
| CPU time | 64.41 seconds |
| Started | Oct 12 10:26:00 AM UTC 24 |
| Finished | Oct 12 10:27:06 AM UTC 24 |
| Peak memory | 260824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547810165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2547810165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/47.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/47.alert_handler_smoke.3706156408 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 120309171 ps |
| CPU time | 16.42 seconds |
| Started | Oct 12 10:25:14 AM UTC 24 |
| Finished | Oct 12 10:25:32 AM UTC 24 |
| Peak memory | 266908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706156408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3706156408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/47.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all.1295458175 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 7976703213 ps |
| CPU time | 202.13 seconds |
| Started | Oct 12 10:27:49 AM UTC 24 |
| Finished | Oct 12 10:31:15 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295458175 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_stress_all.1295458175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/47.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all_with_rand_reset.2897414580 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 5199758413 ps |
| CPU time | 234.61 seconds |
| Started | Oct 12 10:28:23 AM UTC 24 |
| Finished | Oct 12 10:32:21 AM UTC 24 |
| Peak memory | 283744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2897414580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.a lert_handler_stress_all_with_rand_reset.2897414580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/47.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/48.alert_handler_entropy.564745481 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 38882866183 ps |
| CPU time | 2742.46 seconds |
| Started | Oct 12 10:29:50 AM UTC 24 |
| Finished | Oct 12 11:16:08 AM UTC 24 |
| Peak memory | 302312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564745481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.564745481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/48.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_alert_accum.395708118 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 1367068751 ps |
| CPU time | 40.52 seconds |
| Started | Oct 12 10:29:31 AM UTC 24 |
| Finished | Oct 12 10:30:13 AM UTC 24 |
| Peak memory | 267164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395708118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.395708118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/48.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_intr_timeout.1903555509 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 465284876 ps |
| CPU time | 23.9 seconds |
| Started | Oct 12 10:29:26 AM UTC 24 |
| Finished | Oct 12 10:29:51 AM UTC 24 |
| Peak memory | 261020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903555509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1903555509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/48.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg.2954765157 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 16284648456 ps |
| CPU time | 1515.37 seconds |
| Started | Oct 12 10:30:14 AM UTC 24 |
| Finished | Oct 12 10:55:50 AM UTC 24 |
| Peak memory | 293672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954765157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2954765157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/48.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg_stub_clk.1273171618 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 16106049901 ps |
| CPU time | 1095.23 seconds |
| Started | Oct 12 10:30:18 AM UTC 24 |
| Finished | Oct 12 10:48:49 AM UTC 24 |
| Peak memory | 295916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273171618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1273171618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/48.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/48.alert_handler_ping_timeout.70226371 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 92497220343 ps |
| CPU time | 593.19 seconds |
| Started | Oct 12 10:29:51 AM UTC 24 |
| Finished | Oct 12 10:39:53 AM UTC 24 |
| Peak memory | 260908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70226371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.70226371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/48.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_alerts.3631250982 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 1054835062 ps |
| CPU time | 27.93 seconds |
| Started | Oct 12 10:29:10 AM UTC 24 |
| Finished | Oct 12 10:29:40 AM UTC 24 |
| Peak memory | 261020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631250982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3631250982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/48.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_classes.4042139760 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 238436639 ps |
| CPU time | 10.94 seconds |
| Started | Oct 12 10:29:18 AM UTC 24 |
| Finished | Oct 12 10:29:30 AM UTC 24 |
| Peak memory | 265116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042139760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.4042139760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/48.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/48.alert_handler_sig_int_fail.3828032208 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 1700483565 ps |
| CPU time | 34.66 seconds |
| Started | Oct 12 10:29:41 AM UTC 24 |
| Finished | Oct 12 10:30:17 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828032208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3828032208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/48.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/48.alert_handler_smoke.4024694433 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 250735093 ps |
| CPU time | 25.08 seconds |
| Started | Oct 12 10:28:58 AM UTC 24 |
| Finished | Oct 12 10:29:25 AM UTC 24 |
| Peak memory | 266908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024694433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.4024694433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/48.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all.2311917740 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 33174775816 ps |
| CPU time | 1643.24 seconds |
| Started | Oct 12 10:30:26 AM UTC 24 |
| Finished | Oct 12 10:58:11 AM UTC 24 |
| Peak memory | 300084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311917740 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_stress_all.2311917740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/48.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all_with_rand_reset.3909955766 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 7675945895 ps |
| CPU time | 278.13 seconds |
| Started | Oct 12 10:30:57 AM UTC 24 |
| Finished | Oct 12 10:35:40 AM UTC 24 |
| Peak memory | 277600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3909955766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.a lert_handler_stress_all_with_rand_reset.3909955766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/48.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/49.alert_handler_entropy.4151200189 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 94262807123 ps |
| CPU time | 1590.33 seconds |
| Started | Oct 12 10:31:49 AM UTC 24 |
| Finished | Oct 12 10:58:40 AM UTC 24 |
| Peak memory | 283432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151200189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.4151200189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/49.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_alert_accum.86021687 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 661381359 ps |
| CPU time | 62.15 seconds |
| Started | Oct 12 10:31:37 AM UTC 24 |
| Finished | Oct 12 10:32:41 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86021687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc _alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.86021687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/49.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_intr_timeout.464974229 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 495243066 ps |
| CPU time | 19.21 seconds |
| Started | Oct 12 10:31:28 AM UTC 24 |
| Finished | Oct 12 10:31:49 AM UTC 24 |
| Peak memory | 261024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464974229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.464974229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/49.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg.1430596231 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 20079893839 ps |
| CPU time | 1167.89 seconds |
| Started | Oct 12 10:32:03 AM UTC 24 |
| Finished | Oct 12 10:51:47 AM UTC 24 |
| Peak memory | 295716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430596231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1430596231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/49.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg_stub_clk.1657383009 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 159644428826 ps |
| CPU time | 2613.3 seconds |
| Started | Oct 12 10:32:17 AM UTC 24 |
| Finished | Oct 12 11:16:24 AM UTC 24 |
| Peak memory | 302384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657383009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1657383009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/49.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/49.alert_handler_ping_timeout.1193364616 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 21044890626 ps |
| CPU time | 316.73 seconds |
| Started | Oct 12 10:31:59 AM UTC 24 |
| Finished | Oct 12 10:37:21 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193364616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1193364616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_alerts.2055730709 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 445830045 ps |
| CPU time | 9.91 seconds |
| Started | Oct 12 10:31:16 AM UTC 24 |
| Finished | Oct 12 10:31:27 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055730709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2055730709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/49.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_classes.2803786482 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 1557368608 ps |
| CPU time | 41.1 seconds |
| Started | Oct 12 10:31:16 AM UTC 24 |
| Finished | Oct 12 10:31:59 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803786482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2803786482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/49.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/49.alert_handler_sig_int_fail.3135486879 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 461767173 ps |
| CPU time | 24.99 seconds |
| Started | Oct 12 10:31:49 AM UTC 24 |
| Finished | Oct 12 10:32:16 AM UTC 24 |
| Peak memory | 267172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135486879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3135486879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/49.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/49.alert_handler_smoke.124250160 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 2047045349 ps |
| CPU time | 30.31 seconds |
| Started | Oct 12 10:31:05 AM UTC 24 |
| Finished | Oct 12 10:31:36 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124250160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.124250160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/49.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all.3281344633 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 433182724 ps |
| CPU time | 32.65 seconds |
| Started | Oct 12 10:32:22 AM UTC 24 |
| Finished | Oct 12 10:32:56 AM UTC 24 |
| Peak memory | 260760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281344633 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_stress_all.3281344633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/49.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all_with_rand_reset.3306242528 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 1746843053 ps |
| CPU time | 157.73 seconds |
| Started | Oct 12 10:32:29 AM UTC 24 |
| Finished | Oct 12 10:35:10 AM UTC 24 |
| Peak memory | 283488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3306242528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.a lert_handler_stress_all_with_rand_reset.3306242528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/49.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/5.alert_handler_alert_accum_saturation.2219796176 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 54513760 ps |
| CPU time | 4.71 seconds |
| Started | Oct 12 09:05:31 AM UTC 24 |
| Finished | Oct 12 09:05:36 AM UTC 24 |
| Peak memory | 261168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219796176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2219796176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/5.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy_stress.1730118827 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1107121134 ps |
| CPU time | 19.7 seconds |
| Started | Oct 12 09:05:23 AM UTC 24 |
| Finished | Oct 12 09:05:44 AM UTC 24 |
| Peak memory | 260764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730118827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1730118827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/5.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_alert_accum.2953672207 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1498747988 ps |
| CPU time | 113.66 seconds |
| Started | Oct 12 09:05:08 AM UTC 24 |
| Finished | Oct 12 09:07:04 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953672207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2953672207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/5.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_intr_timeout.2461686570 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 6285361124 ps |
| CPU time | 46.58 seconds |
| Started | Oct 12 09:05:04 AM UTC 24 |
| Finished | Oct 12 09:05:52 AM UTC 24 |
| Peak memory | 260820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461686570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2461686570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/5.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg.1165227461 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 13935324560 ps |
| CPU time | 1103.16 seconds |
| Started | Oct 12 09:05:18 AM UTC 24 |
| Finished | Oct 12 09:23:54 AM UTC 24 |
| Peak memory | 293672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165227461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1165227461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/5.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg_stub_clk.3640578777 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 85356185168 ps |
| CPU time | 1504.37 seconds |
| Started | Oct 12 09:05:20 AM UTC 24 |
| Finished | Oct 12 09:30:42 AM UTC 24 |
| Peak memory | 283688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640578777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3640578777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/5.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/5.alert_handler_ping_timeout.3545193358 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 2593767823 ps |
| CPU time | 138.84 seconds |
| Started | Oct 12 09:05:14 AM UTC 24 |
| Finished | Oct 12 09:07:36 AM UTC 24 |
| Peak memory | 261092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545193358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3545193358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_alerts.1284897226 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 604950044 ps |
| CPU time | 32.73 seconds |
| Started | Oct 12 09:04:55 AM UTC 24 |
| Finished | Oct 12 09:05:29 AM UTC 24 |
| Peak memory | 266908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284897226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1284897226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/5.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_classes.1279699622 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 712117935 ps |
| CPU time | 29.62 seconds |
| Started | Oct 12 09:04:56 AM UTC 24 |
| Finished | Oct 12 09:05:27 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279699622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1279699622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/5.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/5.alert_handler_sig_int_fail.3325206825 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1435091654 ps |
| CPU time | 30.85 seconds |
| Started | Oct 12 09:05:10 AM UTC 24 |
| Finished | Oct 12 09:05:43 AM UTC 24 |
| Peak memory | 260868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325206825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3325206825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/5.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/5.alert_handler_smoke.704918921 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 374405470 ps |
| CPU time | 44.71 seconds |
| Started | Oct 12 09:04:54 AM UTC 24 |
| Finished | Oct 12 09:05:40 AM UTC 24 |
| Peak memory | 267168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704918921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.704918921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/5.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all.719090814 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 59815061494 ps |
| CPU time | 817.31 seconds |
| Started | Oct 12 09:05:28 AM UTC 24 |
| Finished | Oct 12 09:19:15 AM UTC 24 |
| Peak memory | 277208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719090814 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_stress_all.719090814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/5.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all_with_rand_reset.1065212036 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 7231788811 ps |
| CPU time | 277.89 seconds |
| Started | Oct 12 09:05:31 AM UTC 24 |
| Finished | Oct 12 09:10:13 AM UTC 24 |
| Peak memory | 279452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1065212036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.al ert_handler_stress_all_with_rand_reset.1065212036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy_stress.2003812667 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 913060153 ps |
| CPU time | 32.91 seconds |
| Started | Oct 12 09:06:17 AM UTC 24 |
| Finished | Oct 12 09:06:51 AM UTC 24 |
| Peak memory | 261096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003812667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2003812667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/6.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_alert_accum.1504521990 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 1769629663 ps |
| CPU time | 197.85 seconds |
| Started | Oct 12 09:05:45 AM UTC 24 |
| Finished | Oct 12 09:09:06 AM UTC 24 |
| Peak memory | 266968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504521990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1504521990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/6.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_intr_timeout.1411866066 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2203382387 ps |
| CPU time | 85.85 seconds |
| Started | Oct 12 09:05:44 AM UTC 24 |
| Finished | Oct 12 09:07:11 AM UTC 24 |
| Peak memory | 261084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411866066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1411866066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/6.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg.2950086622 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 48572105685 ps |
| CPU time | 1020.74 seconds |
| Started | Oct 12 09:05:53 AM UTC 24 |
| Finished | Oct 12 09:23:06 AM UTC 24 |
| Peak memory | 283444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950086622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2950086622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/6.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg_stub_clk.4004008224 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 19510740896 ps |
| CPU time | 1098.17 seconds |
| Started | Oct 12 09:06:07 AM UTC 24 |
| Finished | Oct 12 09:24:39 AM UTC 24 |
| Peak memory | 297836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004008224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.4004008224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/6.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_alerts.3518991412 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 1100167386 ps |
| CPU time | 25.86 seconds |
| Started | Oct 12 09:05:39 AM UTC 24 |
| Finished | Oct 12 09:06:06 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518991412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3518991412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/6.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_classes.1931392251 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 2188667863 ps |
| CPU time | 70.73 seconds |
| Started | Oct 12 09:05:41 AM UTC 24 |
| Finished | Oct 12 09:06:54 AM UTC 24 |
| Peak memory | 266968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931392251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1931392251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/6.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/6.alert_handler_smoke.3650117176 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 562872547 ps |
| CPU time | 13.25 seconds |
| Started | Oct 12 09:05:37 AM UTC 24 |
| Finished | Oct 12 09:05:51 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650117176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3650117176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/6.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all.4139808707 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 264124659628 ps |
| CPU time | 2274.45 seconds |
| Started | Oct 12 09:06:19 AM UTC 24 |
| Finished | Oct 12 09:44:39 AM UTC 24 |
| Peak memory | 300020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139808707 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_stress_all.4139808707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/6.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all_with_rand_reset.2631386932 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3056981398 ps |
| CPU time | 418.98 seconds |
| Started | Oct 12 09:06:26 AM UTC 24 |
| Finished | Oct 12 09:13:31 AM UTC 24 |
| Peak memory | 279716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2631386932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.al ert_handler_stress_all_with_rand_reset.2631386932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/7.alert_handler_alert_accum_saturation.3269501576 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 256350296 ps |
| CPU time | 5.3 seconds |
| Started | Oct 12 09:07:17 AM UTC 24 |
| Finished | Oct 12 09:07:23 AM UTC 24 |
| Peak memory | 261040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269501576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3269501576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/7.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy.1586532080 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 36158471526 ps |
| CPU time | 2694.79 seconds |
| Started | Oct 12 09:06:55 AM UTC 24 |
| Finished | Oct 12 09:52:20 AM UTC 24 |
| Peak memory | 299820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586532080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1586532080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/7.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy_stress.2408031858 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 103792281 ps |
| CPU time | 10.12 seconds |
| Started | Oct 12 09:07:12 AM UTC 24 |
| Finished | Oct 12 09:07:24 AM UTC 24 |
| Peak memory | 260768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408031858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2408031858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/7.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_alert_accum.1455250045 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 1781046142 ps |
| CPU time | 129.47 seconds |
| Started | Oct 12 09:06:51 AM UTC 24 |
| Finished | Oct 12 09:09:03 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455250045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1455250045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/7.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_intr_timeout.511402801 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 2904499416 ps |
| CPU time | 51.21 seconds |
| Started | Oct 12 09:06:40 AM UTC 24 |
| Finished | Oct 12 09:07:33 AM UTC 24 |
| Peak memory | 260824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511402801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.511402801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/7.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg.1230391204 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 16272539938 ps |
| CPU time | 718.32 seconds |
| Started | Oct 12 09:07:06 AM UTC 24 |
| Finished | Oct 12 09:19:14 AM UTC 24 |
| Peak memory | 283428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230391204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1230391204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/7.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg_stub_clk.4035049719 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 128837027381 ps |
| CPU time | 1990.06 seconds |
| Started | Oct 12 09:07:11 AM UTC 24 |
| Finished | Oct 12 09:40:44 AM UTC 24 |
| Peak memory | 300080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035049719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.4035049719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/7.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/7.alert_handler_ping_timeout.1783922880 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 5606777389 ps |
| CPU time | 217.02 seconds |
| Started | Oct 12 09:07:05 AM UTC 24 |
| Finished | Oct 12 09:10:46 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783922880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1783922880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/7.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_alerts.659553638 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 323051552 ps |
| CPU time | 43.04 seconds |
| Started | Oct 12 09:06:31 AM UTC 24 |
| Finished | Oct 12 09:07:16 AM UTC 24 |
| Peak memory | 266912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659553638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.659553638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/7.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_classes.152114242 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1990822010 ps |
| CPU time | 40.43 seconds |
| Started | Oct 12 09:06:32 AM UTC 24 |
| Finished | Oct 12 09:07:14 AM UTC 24 |
| Peak memory | 267104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152114242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.152114242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/7.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/7.alert_handler_sig_int_fail.298645798 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 740959662 ps |
| CPU time | 61.81 seconds |
| Started | Oct 12 09:06:52 AM UTC 24 |
| Finished | Oct 12 09:07:55 AM UTC 24 |
| Peak memory | 261024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298645798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.298645798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/7.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/7.alert_handler_smoke.3724831073 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 15326681305 ps |
| CPU time | 50.44 seconds |
| Started | Oct 12 09:06:28 AM UTC 24 |
| Finished | Oct 12 09:07:21 AM UTC 24 |
| Peak memory | 267100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724831073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3724831073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/7.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all.3559306229 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 45813815815 ps |
| CPU time | 805 seconds |
| Started | Oct 12 09:07:15 AM UTC 24 |
| Finished | Oct 12 09:20:50 AM UTC 24 |
| Peak memory | 277228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559306229 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_stress_all.3559306229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/7.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/8.alert_handler_alert_accum_saturation.730922821 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 140462252 ps |
| CPU time | 5.42 seconds |
| Started | Oct 12 09:09:02 AM UTC 24 |
| Finished | Oct 12 09:09:09 AM UTC 24 |
| Peak memory | 261232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730922821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.730922821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/8.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy.1776274063 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 73371832162 ps |
| CPU time | 1884.97 seconds |
| Started | Oct 12 09:07:53 AM UTC 24 |
| Finished | Oct 12 09:39:40 AM UTC 24 |
| Peak memory | 293748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776274063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1776274063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/8.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy_stress.1739737543 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 3159432338 ps |
| CPU time | 54.62 seconds |
| Started | Oct 12 09:08:39 AM UTC 24 |
| Finished | Oct 12 09:09:36 AM UTC 24 |
| Peak memory | 261096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739737543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1739737543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/8.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_alert_accum.3211704747 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 1424607303 ps |
| CPU time | 112.37 seconds |
| Started | Oct 12 09:07:50 AM UTC 24 |
| Finished | Oct 12 09:09:45 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211704747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3211704747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/8.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_intr_timeout.3970934780 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 248739636 ps |
| CPU time | 12.04 seconds |
| Started | Oct 12 09:07:36 AM UTC 24 |
| Finished | Oct 12 09:07:49 AM UTC 24 |
| Peak memory | 260752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970934780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3970934780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/8.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg.1818391293 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 41543299633 ps |
| CPU time | 1176.02 seconds |
| Started | Oct 12 09:07:56 AM UTC 24 |
| Finished | Oct 12 09:27:46 AM UTC 24 |
| Peak memory | 293728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818391293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1818391293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/8.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg_stub_clk.3744919102 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 82736698236 ps |
| CPU time | 3111.51 seconds |
| Started | Oct 12 09:08:26 AM UTC 24 |
| Finished | Oct 12 10:00:53 AM UTC 24 |
| Peak memory | 300080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744919102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3744919102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/8.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/8.alert_handler_ping_timeout.3866308874 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 5274624717 ps |
| CPU time | 266.73 seconds |
| Started | Oct 12 09:07:56 AM UTC 24 |
| Finished | Oct 12 09:12:27 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866308874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3866308874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_alerts.3248601480 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 274326019 ps |
| CPU time | 25.15 seconds |
| Started | Oct 12 09:07:25 AM UTC 24 |
| Finished | Oct 12 09:07:52 AM UTC 24 |
| Peak memory | 266940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248601480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3248601480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/8.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_classes.3822835179 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 752755490 ps |
| CPU time | 49.38 seconds |
| Started | Oct 12 09:07:34 AM UTC 24 |
| Finished | Oct 12 09:08:25 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822835179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3822835179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/8.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/8.alert_handler_sig_int_fail.3251696112 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 488102041 ps |
| CPU time | 45.69 seconds |
| Started | Oct 12 09:07:52 AM UTC 24 |
| Finished | Oct 12 09:08:39 AM UTC 24 |
| Peak memory | 266916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251696112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3251696112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/8.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/8.alert_handler_smoke.1986242147 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 304169939 ps |
| CPU time | 29.56 seconds |
| Started | Oct 12 09:07:24 AM UTC 24 |
| Finished | Oct 12 09:07:55 AM UTC 24 |
| Peak memory | 261020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986242147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1986242147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/8.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all.15994819 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 38780846078 ps |
| CPU time | 523.65 seconds |
| Started | Oct 12 09:08:56 AM UTC 24 |
| Finished | Oct 12 09:17:47 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15994819 -assert nopostproc +UVM_TES TNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_stress_all.15994819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/8.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/9.alert_handler_alert_accum_saturation.4161221806 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 36183029 ps |
| CPU time | 5.61 seconds |
| Started | Oct 12 09:10:34 AM UTC 24 |
| Finished | Oct 12 09:10:41 AM UTC 24 |
| Peak memory | 260964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161221806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.4161221806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/9.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy.126789819 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 89491423817 ps |
| CPU time | 974.33 seconds |
| Started | Oct 12 09:09:56 AM UTC 24 |
| Finished | Oct 12 09:26:22 AM UTC 24 |
| Peak memory | 283496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126789819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.126789819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/9.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy_stress.492925383 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 707399872 ps |
| CPU time | 14.96 seconds |
| Started | Oct 12 09:10:26 AM UTC 24 |
| Finished | Oct 12 09:10:42 AM UTC 24 |
| Peak memory | 261028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492925383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.492925383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/9.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_alert_accum.3519824938 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 2556777588 ps |
| CPU time | 48.61 seconds |
| Started | Oct 12 09:09:47 AM UTC 24 |
| Finished | Oct 12 09:10:37 AM UTC 24 |
| Peak memory | 260896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519824938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3519824938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/9.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_intr_timeout.2074661575 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 632371989 ps |
| CPU time | 44.5 seconds |
| Started | Oct 12 09:09:38 AM UTC 24 |
| Finished | Oct 12 09:10:24 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074661575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2074661575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/9.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg.2249444951 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 271087564638 ps |
| CPU time | 3270.85 seconds |
| Started | Oct 12 09:10:13 AM UTC 24 |
| Finished | Oct 12 10:05:23 AM UTC 24 |
| Peak memory | 299816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249444951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2249444951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/9.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg_stub_clk.3674052027 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 6542386670 ps |
| CPU time | 812.55 seconds |
| Started | Oct 12 09:10:14 AM UTC 24 |
| Finished | Oct 12 09:23:58 AM UTC 24 |
| Peak memory | 283616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674052027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3674052027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/9.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/9.alert_handler_ping_timeout.2696984214 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 8648045672 ps |
| CPU time | 347.89 seconds |
| Started | Oct 12 09:10:09 AM UTC 24 |
| Finished | Oct 12 09:16:02 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696984214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2696984214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/9.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_alerts.816193390 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 3911680706 ps |
| CPU time | 37.65 seconds |
| Started | Oct 12 09:09:10 AM UTC 24 |
| Finished | Oct 12 09:09:49 AM UTC 24 |
| Peak memory | 267072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816193390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.816193390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/9.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_classes.1989793722 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 379765603 ps |
| CPU time | 29.51 seconds |
| Started | Oct 12 09:09:37 AM UTC 24 |
| Finished | Oct 12 09:10:08 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989793722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1989793722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/9.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/9.alert_handler_sig_int_fail.3337145280 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 59576207 ps |
| CPU time | 4.53 seconds |
| Started | Oct 12 09:09:50 AM UTC 24 |
| Finished | Oct 12 09:09:55 AM UTC 24 |
| Peak memory | 250816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337145280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3337145280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/9.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/9.alert_handler_smoke.4249880262 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 823036728 ps |
| CPU time | 28.78 seconds |
| Started | Oct 12 09:09:07 AM UTC 24 |
| Finished | Oct 12 09:09:37 AM UTC 24 |
| Peak memory | 266904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249880262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.4249880262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/9.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all.444815394 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 999743889 ps |
| CPU time | 58.5 seconds |
| Started | Oct 12 09:10:32 AM UTC 24 |
| Finished | Oct 12 09:11:32 AM UTC 24 |
| Peak memory | 261020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444815394 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_11/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_stress_all.444815394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/9.alert_handler_stress_all/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |