Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T3,T7
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1812440050	1598496	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1812440050	306865	0	0
SrcBusyKnown_A	1812440050	1784238570	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812440050	1598496	0	0
T1	1983940	6726	0	0
T2	0	1682	0	0
T3	0	23798	0	0
T4	1118560	1621	0	0
T5	12170	0	0	0
T6	52300	0	0	0
T7	0	3643	0	0
T17	14720	0	0	0
T19	0	312	0	0
T24	21620	0	0	0
T25	14120	0	0	0
T26	11610	0	0	0
T27	10350	0	0	0
T28	12710	0	0	0
T29	0	323	0	0
T32	0	165	0	0
T33	0	764	0	0
T34	0	1002	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3181128	3176072	0	0
T4	649816	648804	0	0
T5	7616	7170	0	0
T6	33856	30540	0	0
T17	9430	9050	0	0
T24	14204	13210	0	0
T25	8746	7682	0	0
T26	31774	30910	0	0
T27	27338	26390	0	0
T28	76372	75212	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812440050	306865	0	0
T1	1983940	1525	0	0
T2	0	320	0	0
T3	0	2875	0	0
T4	1118560	200	0	0
T5	12170	0	0	0
T6	52300	0	0	0
T7	0	448	0	0
T17	14720	0	0	0
T19	0	40	0	0
T24	21620	0	0	0
T25	14120	0	0	0
T26	11610	0	0	0
T27	10350	0	0	0
T28	12710	0	0	0
T29	0	100	0	0
T32	0	20	0	0
T33	0	200	0	0
T34	0	340	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812440050	1784238570	0	0
T1	1983940	1980520	0	0
T4	1118560	1117010	0	0
T5	12170	11340	0	0
T6	52300	46720	0	0
T17	14720	14040	0	0
T24	21620	19870	0	0
T25	14120	12150	0	0
T26	11610	11210	0	0
T27	10350	9950	0	0
T28	12710	12490	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	181244005	99161	0	0
DstReqKnown_A	461686227	456940303	0	0
SrcAckBusyChk_A	181244005	27807	0	0
SrcBusyKnown_A	181244005	178423857	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	99161	0	0
T1	198394	491	0	0
T2	0	113	0	0
T3	0	1463	0	0
T4	111856	103	0	0
T5	1217	0	0	0
T6	5230	0	0	0
T7	0	160	0	0
T17	1472	0	0	0
T19	0	22	0	0
T24	2162	0	0	0
T25	1412	0	0	0
T26	1161	0	0	0
T27	1035	0	0	0
T28	1271	0	0	0
T29	0	25	0	0
T32	0	12	0	0
T33	0	55	0	0
T34	0	83	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461686227	456940303	0	0
T1	481426	480586	0	0
T4	87923	87760	0	0
T5	1169	1089	0	0
T6	5122	4576	0	0
T17	1441	1374	0	0
T24	2162	1987	0	0
T25	1356	1167	0	0
T26	4649	4487	0	0
T27	4143	3981	0	0
T28	11095	10891	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	27807	0	0
T1	198394	150	0	0
T2	0	32	0	0
T3	0	282	0	0
T4	111856	20	0	0
T5	1217	0	0	0
T6	5230	0	0	0
T7	0	32	0	0
T17	1472	0	0	0
T19	0	4	0	0
T24	2162	0	0	0
T25	1412	0	0	0
T26	1161	0	0	0
T27	1035	0	0	0
T28	1271	0	0	0
T29	0	10	0	0
T32	0	2	0	0
T33	0	20	0	0
T34	0	34	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	178423857	0	0
T1	198394	198052	0	0
T4	111856	111701	0	0
T5	1217	1134	0	0
T6	5230	4672	0	0
T17	1472	1404	0	0
T24	2162	1987	0	0
T25	1412	1215	0	0
T26	1161	1121	0	0
T27	1035	995	0	0
T28	1271	1249	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	181244005	144398	0	0
DstReqKnown_A	229944675	228765499	0	0
SrcAckBusyChk_A	181244005	27807	0	0
SrcBusyKnown_A	181244005	178423857	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	144398	0	0
T1	198394	665	0	0
T2	0	162	0	0
T3	0	2354	0	0
T4	111856	167	0	0
T5	1217	0	0	0
T6	5230	0	0	0
T7	0	258	0	0
T17	1472	0	0	0
T19	0	31	0	0
T24	2162	0	0	0
T25	1412	0	0	0
T26	1161	0	0	0
T27	1035	0	0	0
T28	1271	0	0	0
T29	0	31	0	0
T32	0	17	0	0
T33	0	78	0	0
T34	0	101	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	229944675	228765499	0	0
T1	240848	240587	0	0
T4	43942	43880	0	0
T5	559	545	0	0
T6	2606	2427	0	0
T17	701	687	0	0
T24	1071	1037	0	0
T25	618	584	0	0
T26	2715	2701	0	0
T27	2093	2052	0	0
T28	6658	6616	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	27807	0	0
T1	198394	150	0	0
T2	0	32	0	0
T3	0	282	0	0
T4	111856	20	0	0
T5	1217	0	0	0
T6	5230	0	0	0
T7	0	32	0	0
T17	1472	0	0	0
T19	0	4	0	0
T24	2162	0	0	0
T25	1412	0	0	0
T26	1161	0	0	0
T27	1035	0	0	0
T28	1271	0	0	0
T29	0	10	0	0
T32	0	2	0	0
T33	0	20	0	0
T34	0	34	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	178423857	0	0
T1	198394	198052	0	0
T4	111856	111701	0	0
T5	1217	1134	0	0
T6	5230	4672	0	0
T17	1472	1404	0	0
T24	2162	1987	0	0
T25	1412	1215	0	0
T26	1161	1121	0	0
T27	1035	995	0	0
T28	1271	1249	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	181244005	231839	0	0
DstReqKnown_A	114971673	114382167	0	0
SrcAckBusyChk_A	181244005	27807	0	0
SrcBusyKnown_A	181244005	178423857	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	231839	0	0
T1	198394	1019	0	0
T2	0	262	0	0
T3	0	4098	0	0
T4	111856	274	0	0
T5	1217	0	0	0
T6	5230	0	0	0
T7	0	458	0	0
T17	1472	0	0	0
T19	0	56	0	0
T24	2162	0	0	0
T25	1412	0	0	0
T26	1161	0	0	0
T27	1035	0	0	0
T28	1271	0	0	0
T29	0	47	0	0
T32	0	30	0	0
T33	0	115	0	0
T34	0	132	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114971673	114382167	0	0
T1	120423	120293	0	0
T4	21971	21940	0	0
T5	279	272	0	0
T6	1303	1213	0	0
T17	351	344	0	0
T24	535	518	0	0
T25	309	292	0	0
T26	1356	1349	0	0
T27	1046	1025	0	0
T28	3328	3307	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	27807	0	0
T1	198394	150	0	0
T2	0	32	0	0
T3	0	282	0	0
T4	111856	20	0	0
T5	1217	0	0	0
T6	5230	0	0	0
T7	0	32	0	0
T17	1472	0	0	0
T19	0	4	0	0
T24	2162	0	0	0
T25	1412	0	0	0
T26	1161	0	0	0
T27	1035	0	0	0
T28	1271	0	0	0
T29	0	10	0	0
T32	0	2	0	0
T33	0	20	0	0
T34	0	34	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	178423857	0	0
T1	198394	198052	0	0
T4	111856	111701	0	0
T5	1217	1134	0	0
T6	5230	4672	0	0
T17	1472	1404	0	0
T24	2162	1987	0	0
T25	1412	1215	0	0
T26	1161	1121	0	0
T27	1035	995	0	0
T28	1271	1249	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	181244005	98086	0	0
DstReqKnown_A	493507901	488516000	0	0
SrcAckBusyChk_A	181244005	27807	0	0
SrcBusyKnown_A	181244005	178423857	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	98086	0	0
T1	198394	482	0	0
T2	0	112	0	0
T3	0	1424	0	0
T4	111856	102	0	0
T5	1217	0	0	0
T6	5230	0	0	0
T7	0	158	0	0
T17	1472	0	0	0
T19	0	17	0	0
T24	2162	0	0	0
T25	1412	0	0	0
T26	1161	0	0	0
T27	1035	0	0	0
T28	1271	0	0	0
T29	0	25	0	0
T32	0	9	0	0
T33	0	55	0	0
T34	0	83	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493507901	488516000	0	0
T1	505702	504826	0	0
T4	115588	115419	0	0
T5	1217	1134	0	0
T6	5336	4767	0	0
T17	1502	1433	0	0
T24	2253	2069	0	0
T25	1412	1215	0	0
T26	4843	4674	0	0
T27	4316	4147	0	0
T28	11558	11346	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	27807	0	0
T1	198394	150	0	0
T2	0	32	0	0
T3	0	282	0	0
T4	111856	20	0	0
T5	1217	0	0	0
T6	5230	0	0	0
T7	0	32	0	0
T17	1472	0	0	0
T19	0	4	0	0
T24	2162	0	0	0
T25	1412	0	0	0
T26	1161	0	0	0
T27	1035	0	0	0
T28	1271	0	0	0
T29	0	10	0	0
T32	0	2	0	0
T33	0	20	0	0
T34	0	34	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	178423857	0	0
T1	198394	198052	0	0
T4	111856	111701	0	0
T5	1217	1134	0	0
T6	5230	4672	0	0
T17	1472	1404	0	0
T24	2162	1987	0	0
T25	1412	1215	0	0
T26	1161	1121	0	0
T27	1035	995	0	0
T28	1271	1249	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	181244005	141775	0	0
DstReqKnown_A	237033942	234642617	0	0
SrcAckBusyChk_A	181244005	27284	0	0
SrcBusyKnown_A	181244005	178423857	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	141775	0	0
T1	198394	662	0	0
T2	0	194	0	0
T3	0	2334	0	0
T4	111856	156	0	0
T5	1217	0	0	0
T6	5230	0	0	0
T7	0	144	0	0
T17	1472	0	0	0
T19	0	30	0	0
T24	2162	0	0	0
T25	1412	0	0	0
T26	1161	0	0	0
T27	1035	0	0	0
T28	1271	0	0	0
T29	0	35	0	0
T32	0	15	0	0
T33	0	80	0	0
T34	0	99	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237033942	234642617	0	0
T1	242165	241744	0	0
T4	55484	55403	0	0
T5	584	545	0	0
T6	2561	2287	0	0
T17	720	687	0	0
T24	1081	994	0	0
T25	678	583	0	0
T26	2324	2244	0	0
T27	2071	1990	0	0
T28	5547	5446	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	27284	0	0
T1	198394	150	0	0
T2	0	32	0	0
T3	0	282	0	0
T4	111856	20	0	0
T5	1217	0	0	0
T6	5230	0	0	0
T7	0	16	0	0
T17	1472	0	0	0
T19	0	4	0	0
T24	2162	0	0	0
T25	1412	0	0	0
T26	1161	0	0	0
T27	1035	0	0	0
T28	1271	0	0	0
T29	0	10	0	0
T32	0	2	0	0
T33	0	20	0	0
T34	0	34	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	178423857	0	0
T1	198394	198052	0	0
T4	111856	111701	0	0
T5	1217	1134	0	0
T6	5230	4672	0	0
T17	1472	1404	0	0
T24	2162	1987	0	0
T25	1412	1215	0	0
T26	1161	1121	0	0
T27	1035	995	0	0
T28	1271	1249	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T3,T7
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	181244005	121295	0	0
DstReqKnown_A	461686227	456940303	0	0
SrcAckBusyChk_A	181244005	33574	0	0
SrcBusyKnown_A	181244005	178423857	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	121295	0	0
T1	198394	505	0	0
T2	0	113	0	0
T3	0	1515	0	0
T4	111856	102	0	0
T5	1217	0	0	0
T6	5230	0	0	0
T7	0	318	0	0
T17	1472	0	0	0
T19	0	22	0	0
T24	2162	0	0	0
T25	1412	0	0	0
T26	1161	0	0	0
T27	1035	0	0	0
T28	1271	0	0	0
T29	0	25	0	0
T32	0	12	0	0
T33	0	59	0	0
T34	0	83	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461686227	456940303	0	0
T1	481426	480586	0	0
T4	87923	87760	0	0
T5	1169	1089	0	0
T6	5122	4576	0	0
T17	1441	1374	0	0
T24	2162	1987	0	0
T25	1356	1167	0	0
T26	4649	4487	0	0
T27	4143	3981	0	0
T28	11095	10891	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	33574	0	0
T1	198394	155	0	0
T2	0	32	0	0
T3	0	293	0	0
T4	111856	20	0	0
T5	1217	0	0	0
T6	5230	0	0	0
T7	0	64	0	0
T17	1472	0	0	0
T19	0	4	0	0
T24	2162	0	0	0
T25	1412	0	0	0
T26	1161	0	0	0
T27	1035	0	0	0
T28	1271	0	0	0
T29	0	10	0	0
T32	0	2	0	0
T33	0	20	0	0
T34	0	34	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	178423857	0	0
T1	198394	198052	0	0
T4	111856	111701	0	0
T5	1217	1134	0	0
T6	5230	4672	0	0
T17	1472	1404	0	0
T24	2162	1987	0	0
T25	1412	1215	0	0
T26	1161	1121	0	0
T27	1035	995	0	0
T28	1271	1249	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T3,T7
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	181244005	177790	0	0
DstReqKnown_A	229944675	228765499	0	0
SrcAckBusyChk_A	181244005	33791	0	0
SrcBusyKnown_A	181244005	178423857	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	177790	0	0
T1	198394	679	0	0
T2	0	162	0	0
T3	0	2432	0	0
T4	111856	159	0	0
T5	1217	0	0	0
T6	5230	0	0	0
T7	0	513	0	0
T17	1472	0	0	0
T19	0	32	0	0
T24	2162	0	0	0
T25	1412	0	0	0
T26	1161	0	0	0
T27	1035	0	0	0
T28	1271	0	0	0
T29	0	32	0	0
T32	0	17	0	0
T33	0	77	0	0
T34	0	100	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	229944675	228765499	0	0
T1	240848	240587	0	0
T4	43942	43880	0	0
T5	559	545	0	0
T6	2606	2427	0	0
T17	701	687	0	0
T24	1071	1037	0	0
T25	618	584	0	0
T26	2715	2701	0	0
T27	2093	2052	0	0
T28	6658	6616	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	33791	0	0
T1	198394	155	0	0
T2	0	32	0	0
T3	0	293	0	0
T4	111856	20	0	0
T5	1217	0	0	0
T6	5230	0	0	0
T7	0	64	0	0
T17	1472	0	0	0
T19	0	4	0	0
T24	2162	0	0	0
T25	1412	0	0	0
T26	1161	0	0	0
T27	1035	0	0	0
T28	1271	0	0	0
T29	0	10	0	0
T32	0	2	0	0
T33	0	20	0	0
T34	0	34	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	178423857	0	0
T1	198394	198052	0	0
T4	111856	111701	0	0
T5	1217	1134	0	0
T6	5230	4672	0	0
T17	1472	1404	0	0
T24	2162	1987	0	0
T25	1412	1215	0	0
T26	1161	1121	0	0
T27	1035	995	0	0
T28	1271	1249	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T3,T7
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	181244005	287307	0	0
DstReqKnown_A	114971673	114382167	0	0
SrcAckBusyChk_A	181244005	33842	0	0
SrcBusyKnown_A	181244005	178423857	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	287307	0	0
T1	198394	1056	0	0
T2	0	259	0	0
T3	0	4255	0	0
T4	111856	290	0	0
T5	1217	0	0	0
T6	5230	0	0	0
T7	0	898	0	0
T17	1472	0	0	0
T19	0	56	0	0
T24	2162	0	0	0
T25	1412	0	0	0
T26	1161	0	0	0
T27	1035	0	0	0
T28	1271	0	0	0
T29	0	45	0	0
T32	0	28	0	0
T33	0	110	0	0
T34	0	135	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114971673	114382167	0	0
T1	120423	120293	0	0
T4	21971	21940	0	0
T5	279	272	0	0
T6	1303	1213	0	0
T17	351	344	0	0
T24	535	518	0	0
T25	309	292	0	0
T26	1356	1349	0	0
T27	1046	1025	0	0
T28	3328	3307	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	33842	0	0
T1	198394	155	0	0
T2	0	32	0	0
T3	0	293	0	0
T4	111856	20	0	0
T5	1217	0	0	0
T6	5230	0	0	0
T7	0	64	0	0
T17	1472	0	0	0
T19	0	4	0	0
T24	2162	0	0	0
T25	1412	0	0	0
T26	1161	0	0	0
T27	1035	0	0	0
T28	1271	0	0	0
T29	0	10	0	0
T32	0	2	0	0
T33	0	20	0	0
T34	0	34	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	178423857	0	0
T1	198394	198052	0	0
T4	111856	111701	0	0
T5	1217	1134	0	0
T6	5230	4672	0	0
T17	1472	1404	0	0
T24	2162	1987	0	0
T25	1412	1215	0	0
T26	1161	1121	0	0
T27	1035	995	0	0
T28	1271	1249	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T3,T7
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	181244005	120131	0	0
DstReqKnown_A	493507901	488516000	0	0
SrcAckBusyChk_A	181244005	33681	0	0
SrcBusyKnown_A	181244005	178423857	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	120131	0	0
T1	198394	491	0	0
T2	0	111	0	0
T3	0	1480	0	0
T4	111856	102	0	0
T5	1217	0	0	0
T6	5230	0	0	0
T7	0	311	0	0
T17	1472	0	0	0
T19	0	18	0	0
T24	2162	0	0	0
T25	1412	0	0	0
T26	1161	0	0	0
T27	1035	0	0	0
T28	1271	0	0	0
T29	0	25	0	0
T32	0	9	0	0
T33	0	57	0	0
T34	0	83	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493507901	488516000	0	0
T1	505702	504826	0	0
T4	115588	115419	0	0
T5	1217	1134	0	0
T6	5336	4767	0	0
T17	1502	1433	0	0
T24	2253	2069	0	0
T25	1412	1215	0	0
T26	4843	4674	0	0
T27	4316	4147	0	0
T28	11558	11346	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	33681	0	0
T1	198394	155	0	0
T2	0	32	0	0
T3	0	293	0	0
T4	111856	20	0	0
T5	1217	0	0	0
T6	5230	0	0	0
T7	0	64	0	0
T17	1472	0	0	0
T19	0	4	0	0
T24	2162	0	0	0
T25	1412	0	0	0
T26	1161	0	0	0
T27	1035	0	0	0
T28	1271	0	0	0
T29	0	10	0	0
T32	0	2	0	0
T33	0	20	0	0
T34	0	34	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	178423857	0	0
T1	198394	198052	0	0
T4	111856	111701	0	0
T5	1217	1134	0	0
T6	5230	4672	0	0
T17	1472	1404	0	0
T24	2162	1987	0	0
T25	1412	1215	0	0
T26	1161	1121	0	0
T27	1035	995	0	0
T28	1271	1249	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T3,T7
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	181244005	176714	0	0
DstReqKnown_A	237033942	234642617	0	0
SrcAckBusyChk_A	181244005	33465	0	0
SrcBusyKnown_A	181244005	178423857	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	176714	0	0
T1	198394	676	0	0
T2	0	194	0	0
T3	0	2443	0	0
T4	111856	166	0	0
T5	1217	0	0	0
T6	5230	0	0	0
T7	0	425	0	0
T17	1472	0	0	0
T19	0	28	0	0
T24	2162	0	0	0
T25	1412	0	0	0
T26	1161	0	0	0
T27	1035	0	0	0
T28	1271	0	0	0
T29	0	33	0	0
T32	0	16	0	0
T33	0	78	0	0
T34	0	103	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237033942	234642617	0	0
T1	242165	241744	0	0
T4	55484	55403	0	0
T5	584	545	0	0
T6	2561	2287	0	0
T17	720	687	0	0
T24	1081	994	0	0
T25	678	583	0	0
T26	2324	2244	0	0
T27	2071	1990	0	0
T28	5547	5446	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	33465	0	0
T1	198394	155	0	0
T2	0	32	0	0
T3	0	293	0	0
T4	111856	20	0	0
T5	1217	0	0	0
T6	5230	0	0	0
T7	0	48	0	0
T17	1472	0	0	0
T19	0	4	0	0
T24	2162	0	0	0
T25	1412	0	0	0
T26	1161	0	0	0
T27	1035	0	0	0
T28	1271	0	0	0
T29	0	10	0	0
T32	0	2	0	0
T33	0	20	0	0
T34	0	34	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181244005	178423857	0	0
T1	198394	198052	0	0
T4	111856	111701	0	0
T5	1217	1134	0	0
T6	5230	4672	0	0
T17	1472	1404	0	0
T24	2162	1987	0	0
T25	1412	1215	0	0
T26	1161	1121	0	0
T27	1035	995	0	0
T28	1271	1249	0	0