CLKMGR Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: 1c75f24e99

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.120s	125.653us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.080s	130.223us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.010s	65.752us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	6.810s	677.954us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.820s	103.858us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.990s	374.710us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.010s	65.752us	20	20	100.00
		clkmgr_csr_aliasing	1.820s	103.858us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.210s	180.446us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.780s	322.530us	50	50	100.00
V2	extclk	clkmgr_extclk	1.380s	230.485us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.070s	174.984us	50	50	100.00
V2	jitter	clkmgr_smoke	1.120s	125.653us	50	50	100.00
V2	frequency	clkmgr_frequency	18.560s	2.480ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	15.810s	2.294ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	18.560s	2.480ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.260m	11.173ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.950s	148.277us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.550s	305.140us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	3.470s	276.681us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	3.470s	276.681us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.080s	130.223us	5	5	100.00
		clkmgr_csr_rw	1.010s	65.752us	20	20	100.00
		clkmgr_csr_aliasing	1.820s	103.858us	5	5	100.00
		clkmgr_same_csr_outstanding	2.700s	624.454us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.080s	130.223us	5	5	100.00
		clkmgr_csr_rw	1.010s	65.752us	20	20	100.00
		clkmgr_csr_aliasing	1.820s	103.858us	5	5	100.00
		clkmgr_same_csr_outstanding	2.700s	624.454us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.310s	408.781us	5	5	100.00
		clkmgr_tl_intg_err	2.600s	211.470us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	3.110s	686.194us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	3.110s	686.194us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	3.110s	686.194us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	3.110s	686.194us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	4.170s	594.433us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	2.600s	211.470us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	18.560s	2.480ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	15.810s	2.294ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	3.110s	686.194us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.630s	213.867us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.210s	186.886us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.140s	101.059us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.470s	226.132us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.200s	112.955us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.010s	65.752us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.310s	408.781us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.010s	65.752us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.010s	65.752us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.310s	408.781us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.750s	1.380ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	28.293m	276.186ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1009	1010	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.01	98.80

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:753) [clkmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 29.clkmgr_stress_all_with_rand_reset.11042059452829847714836562539086970983118962436178531016364938283863658837150
      Line 801, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/29.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10264478405 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 10264478405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• dv
• 2024.04.16_04.32.18
• 2024.02.20_10.31.13
• 2024.01.22_10.47.21