Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	903442	0	0
SrcPulseCheck_M	2147483647	901617	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	903442
T1	3455091	3237
T2	2031882	8400
T3	0	11376
T4	102866	190
T5	429394	160
T6	4845	0
T7	4082	0
T10	0	5058
T17	50690	0
T18	25479	0
T19	16501	0
T20	29138	0
T21	7846	0
T22	9471	0
T23	3979	0
T24	6427	0
T25	6303	0
T26	0	60
T28	0	408
T29	0	884
T30	0	484
T31	0	268
T32	0	560
T62	4863	1
T63	17741	2
T66	11853	1
T70	8111	2
T72	5256	1
T132	3825	1
T133	0	1
T134	0	1
T135	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	901617
T1	786341	3237
T2	1365636	8403
T3	0	11376
T4	96847	190
T5	103779	160
T6	4980	0
T7	5053	0
T10	0	4707
T17	13780	0
T18	8030	0
T19	9742	0
T20	2980	0
T21	828	0
T22	992	0
T23	420	0
T24	6440	0
T25	4932	0
T26	0	60
T28	0	408
T29	0	884
T30	0	484
T31	0	268
T32	0	560
T62	3318	1
T63	7714	2
T66	5049	1
T70	16008	2
T72	9505	1
T132	4122	1
T133	0	1
T134	0	1
T135	0	2

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	412060805	24185	0	0
SrcPulseCheck_M	152251160	24185	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	412060805	24185
T1	834565	150
T2	0	497
T3	0	596
T4	126366	38
T5	129534	32
T6	3274	0
T7	2050	0
T17	11773	0
T18	6315	0
T19	3447	0
T24	4300	0
T25	5182	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152251160	24185
T1	172270	150
T2	0	497
T3	0	596
T4	30276	38
T5	32383	32
T6	1705	0
T7	2008	0
T17	1594	0
T18	1513	0
T19	3520	0
T24	2151	0
T25	1187	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	412060805	29675	0	0
SrcPulseCheck_M	152251160	29696	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	412060805	29675
T1	834565	150
T2	0	510
T3	0	606
T4	126366	76
T5	129534	64
T6	3274	0
T7	2050	0
T17	11773	0
T18	6315	0
T19	3447	0
T24	4300	0
T25	5182	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152251160	29696
T1	172270	150
T2	0	510
T3	0	606
T4	30276	76
T5	32383	64
T6	1705	0
T7	2008	0
T17	1594	0
T18	1513	0
T19	3520	0
T24	2151	0
T25	1187	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152251160	29669	0	0
SrcPulseCheck_M	412060805	29678	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152251160	29669
T1	172270	150
T2	0	510
T3	0	606
T4	30276	76
T5	32383	64
T6	1705	0
T7	2008	0
T17	1594	0
T18	1513	0
T19	3520	0
T24	2151	0
T25	1187	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	412060805	29678
T1	834565	150
T2	0	510
T3	0	606
T4	126366	76
T5	129534	64
T6	3274	0
T7	2050	0
T17	11773	0
T18	6315	0
T19	3447	0
T24	4300	0
T25	5182	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	206532727	24185	0	0
SrcPulseCheck_M	152251160	24185	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	206532727	24185
T1	418541	150
T2	0	497
T3	0	596
T4	36295	38
T5	37869	32
T6	1570	0
T7	1037	0
T17	7160	0
T18	3164	0
T19	1698	0
T24	2138	0
T25	2558	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152251160	24185
T1	172270	150
T2	0	497
T3	0	596
T4	30276	38
T5	32383	32
T6	1705	0
T7	2008	0
T17	1594	0
T18	1513	0
T19	3520	0
T24	2151	0
T25	1187	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	206532727	29455	0	0
SrcPulseCheck_M	152251160	29478	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	206532727	29455
T1	418541	150
T2	0	510
T3	0	606
T4	36295	76
T5	37869	64
T6	1570	0
T7	1037	0
T17	7160	0
T18	3164	0
T19	1698	0
T24	2138	0
T25	2558	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152251160	29478
T1	172270	150
T2	0	510
T3	0	606
T4	30276	76
T5	32383	64
T6	1705	0
T7	2008	0
T17	1594	0
T18	1513	0
T19	3520	0
T24	2151	0
T25	1187	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152251160	29447	0	0
SrcPulseCheck_M	206532727	29458	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152251160	29447
T1	172270	150
T2	0	510
T3	0	606
T4	30276	76
T5	32383	64
T6	1705	0
T7	2008	0
T17	1594	0
T18	1513	0
T19	3520	0
T24	2151	0
T25	1187	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	206532727	29458
T1	418541	150
T2	0	510
T3	0	606
T4	36295	76
T5	37869	64
T6	1570	0
T7	1037	0
T17	7160	0
T18	3164	0
T19	1698	0
T24	2138	0
T25	2558	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	103265749	24185	0	0
SrcPulseCheck_M	152251160	24185	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	103265749	24185
T1	209268	150
T2	0	497
T3	0	596
T4	18150	38
T5	18935	32
T6	785	0
T7	517	0
T17	3580	0
T18	1582	0
T19	849	0
T24	1069	0
T25	1279	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152251160	24185
T1	172270	150
T2	0	497
T3	0	596
T4	30276	38
T5	32383	32
T6	1705	0
T7	2008	0
T17	1594	0
T18	1513	0
T19	3520	0
T24	2151	0
T25	1187	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	103265749	29551	0	0
SrcPulseCheck_M	152251160	29583	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	103265749	29551
T1	209268	150
T2	0	510
T3	0	606
T4	18150	76
T5	18935	64
T6	785	0
T7	517	0
T17	3580	0
T18	1582	0
T19	849	0
T24	1069	0
T25	1279	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152251160	29583
T1	172270	150
T2	0	510
T3	0	606
T4	30276	76
T5	32383	64
T6	1705	0
T7	2008	0
T17	1594	0
T18	1513	0
T19	3520	0
T24	2151	0
T25	1187	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152251160	29546	0	0
SrcPulseCheck_M	103265749	29553	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152251160	29546
T1	172270	150
T2	0	510
T3	0	606
T4	30276	76
T5	32383	64
T6	1705	0
T7	2008	0
T17	1594	0
T18	1513	0
T19	3520	0
T24	2151	0
T25	1187	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	103265749	29553
T1	209268	150
T2	0	510
T3	0	606
T4	18150	76
T5	18935	64
T6	785	0
T7	517	0
T17	3580	0
T18	1582	0
T19	849	0
T24	1069	0
T25	1279	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	439370856	24185	0	0
SrcPulseCheck_M	152251160	24185	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	439370856	24185
T1	983365	150
T2	0	497
T3	0	596
T4	131636	38
T5	134935	32
T6	3411	0
T7	2136	0
T17	12263	0
T18	6577	0
T19	3591	0
T24	4479	0
T25	5398	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152251160	24185
T1	172270	150
T2	0	497
T3	0	596
T4	30276	38
T5	32383	32
T6	1705	0
T7	2008	0
T17	1594	0
T18	1513	0
T19	3520	0
T24	2151	0
T25	1187	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	439370856	29673	0	0
SrcPulseCheck_M	152251160	29690	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	439370856	29673
T1	983365	150
T2	0	510
T3	0	606
T4	131636	76
T5	134935	64
T6	3411	0
T7	2136	0
T17	12263	0
T18	6577	0
T19	3591	0
T24	4479	0
T25	5398	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152251160	29690
T1	172270	150
T2	0	510
T3	0	606
T4	30276	76
T5	32383	64
T6	1705	0
T7	2008	0
T17	1594	0
T18	1513	0
T19	3520	0
T24	2151	0
T25	1187	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152251160	29655	0	0
SrcPulseCheck_M	439370856	29676	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152251160	29655
T1	172270	150
T2	0	510
T3	0	606
T4	30276	76
T5	32383	64
T6	1705	0
T7	2008	0
T17	1594	0
T18	1513	0
T19	3520	0
T24	2151	0
T25	1187	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	439370856	29676
T1	983365	150
T2	0	510
T3	0	606
T4	131636	76
T5	134935	64
T6	3411	0
T7	2136	0
T17	12263	0
T18	6577	0
T19	3591	0
T24	4479	0
T25	5398	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	210863317	23669	0	0
SrcPulseCheck_M	152251160	24185	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	210863317	23669
T1	463382	150
T2	0	497
T3	0	596
T4	63186	19
T5	64770	29
T6	1637	0
T7	1025	0
T17	5886	0
T18	3157	0
T19	1724	0
T24	2151	0
T25	2590	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152251160	24185
T1	172270	150
T2	0	497
T3	0	596
T4	30276	38
T5	32383	32
T6	1705	0
T7	2008	0
T17	1594	0
T18	1513	0
T19	3520	0
T24	2151	0
T25	1187	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	210863317	29283	0	0
SrcPulseCheck_M	152251160	29514	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	210863317	29283
T1	463382	150
T2	0	510
T3	0	606
T4	63186	76
T5	64770	64
T6	1637	0
T7	1025	0
T17	5886	0
T18	3157	0
T19	1724	0
T24	2151	0
T25	2590	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152251160	29514
T1	172270	150
T2	0	510
T3	0	606
T4	30276	76
T5	32383	64
T6	1705	0
T7	2008	0
T17	1594	0
T18	1513	0
T19	3520	0
T24	2151	0
T25	1187	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152251160	29084	0	0
SrcPulseCheck_M	210863317	29314	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152251160	29084
T1	172270	150
T2	0	510
T3	0	606
T4	30276	57
T5	32383	62
T6	1705	0
T7	2008	0
T17	1594	0
T18	1513	0
T19	3520	0
T24	2151	0
T25	1187	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	210863317	29314
T1	463382	150
T2	0	510
T3	0	606
T4	63186	76
T5	64770	64
T6	1637	0
T7	1025	0
T17	5886	0
T18	3157	0
T19	1724	0
T24	2151	0
T25	2590	0
T28	0	16
T29	0	40
T30	0	20
T31	0	8
T32	0	24

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T65,T63,T64
1	0	Covered	T65,T63,T64
1	1	Covered	T64,T70,T71

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T65,T63,T64
1	0	Covered	T64,T70,T71
1	1	Covered	T65,T63,T64

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152251160	28	0	0
SrcPulseCheck_M	412060805	28	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152251160	28
T63	17741	1
T64	3736	2
T65	9019	1
T68	6787	2
T70	8111	2
T71	2948	2
T72	5256	2
T132	3825	1
T133	7401	1
T134	8058	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	412060805	28
T63	17031	1
T64	17077	2
T65	9514	1
T68	26061	2
T70	33853	2
T71	23581	2
T72	20183	2
T132	9178	1
T133	50753	1
T134	33634	5

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T64,T69,T70
1	0	Covered	T64,T69,T70
1	1	Covered	T70,T71,T134

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T64,T69,T70
1	0	Covered	T70,T71,T134
1	1	Covered	T64,T69,T70

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152251160	33	0	0
SrcPulseCheck_M	412060805	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152251160	33
T64	3736	1
T66	11853	1
T68	6787	1
T69	14921	1
T70	8111	2
T71	2948	3
T72	5256	2
T132	3825	1
T133	7401	2
T136	5938	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	412060805	33
T64	17077	1
T66	11853	1
T68	26061	1
T69	14323	1
T70	33853	2
T71	23581	3
T72	20183	2
T132	9178	1
T133	50753	2
T136	19657	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T62,T63,T70
1	0	Covered	T62,T63,T70
1	1	Covered	T135,T137,T138

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T62,T63,T70
1	0	Covered	T135,T137,T138
1	1	Covered	T62,T63,T70

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152251160	35	0	0
SrcPulseCheck_M	206532727	35	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152251160	35
T62	4863	1
T63	17741	2
T66	11853	1
T70	8111	2
T72	5256	1
T132	3825	1
T133	7401	1
T134	8058	1
T135	6673	2
T139	5124	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	206532727	35
T62	3318	1
T63	7714	2
T66	5049	1
T70	16008	2
T72	9505	1
T132	4122	1
T133	24367	1
T134	16020	1
T135	2744	2
T139	4764	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T63,T64,T70
1	0	Covered	T63,T64,T70
1	1	Covered	T72,T133,T138

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T63,T64,T70
1	0	Covered	T72,T133,T138
1	1	Covered	T63,T64,T70

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152251160	30	0	0
SrcPulseCheck_M	206532727	30	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152251160	30
T63	17741	2
T64	3736	1
T66	11853	3
T70	8111	2
T72	5256	2
T133	7401	3
T135	6673	1
T139	5124	1
T140	5250	2
T141	5100	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	206532727	30
T63	7714	2
T64	8166	1
T66	5049	3
T70	16008	2
T72	9505	2
T133	24367	3
T135	2744	1
T139	4764	1
T140	10766	2
T141	4405	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T65,T62,T63
1	0	Covered	T65,T62,T63
1	1	Covered	T70,T66,T133

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T65,T62,T63
1	0	Covered	T70,T66,T133
1	1	Covered	T65,T62,T63

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152251160	39	0	0
SrcPulseCheck_M	103265749	39	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152251160	39
T62	4863	1
T63	17741	1
T64	3736	1
T65	9019	1
T66	11853	3
T68	6787	1
T70	8111	3
T71	2948	1
T133	7401	4
T134	8058	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	103265749	39
T62	1658	1
T63	3857	1
T64	4083	1
T65	2110	1
T66	2522	3
T68	6283	1
T70	8003	3
T71	5772	1
T133	12182	4
T134	8011	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T65,T62,T64
1	0	Covered	T65,T62,T64
1	1	Covered	T71,T66,T134

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T65,T62,T64
1	0	Covered	T71,T66,T134
1	1	Covered	T65,T62,T64

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152251160	33	0	0
SrcPulseCheck_M	103265749	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152251160	33
T62	4863	1
T64	3736	1
T65	9019	1
T66	11853	2
T68	6787	1
T71	2948	2
T133	7401	2
T134	8058	3
T135	6673	1
T139	5124	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	103265749	33
T62	1658	1
T64	4083	1
T65	2110	1
T66	2522	2
T68	6283	1
T71	5772	2
T133	12182	2
T134	8011	3
T135	1371	1
T139	2381	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T62,T63,T69
1	0	Covered	T62,T63,T69
1	1	Covered	T133,T134,T142

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T62,T63,T69
1	0	Covered	T133,T134,T142
1	1	Covered	T62,T63,T69

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152251160	31	0	0
SrcPulseCheck_M	439370856	31	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152251160	31
T62	4863	1
T63	17741	1
T69	14921	1
T70	8111	3
T71	2948	2
T72	5256	1
T133	7401	2
T134	8058	2
T135	6673	1
T140	5250	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	439370856	31
T62	8106	1
T63	17741	1
T69	14921	1
T70	35265	3
T71	24565	2
T72	21025	1
T133	52870	2
T134	35037	2
T135	6879	1
T140	23864	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T62,T63,T64
1	0	Covered	T62,T63,T64
1	1	Covered	T134,T143

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T62,T63,T64
1	0	Covered	T134,T143
1	1	Covered	T62,T63,T64

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152251160	36	0	0
SrcPulseCheck_M	439370856	36	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152251160	36
T62	4863	2
T63	17741	1
T64	3736	1
T66	11853	1
T68	6787	2
T69	14921	1
T70	8111	2
T71	2948	2
T72	5256	1
T134	8058	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	439370856	36
T62	8106	2
T63	17741	1
T64	17790	1
T66	12348	1
T68	27149	2
T69	14921	1
T70	35265	2
T71	24565	2
T72	21025	1
T134	35037	4

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T63,T69,T70
1	0	Covered	T63,T69,T70
1	1	Covered	T134,T144,T145

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T63,T69,T70
1	0	Covered	T134,T144,T145
1	1	Covered	T63,T69,T70

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152251160	30	0	0
SrcPulseCheck_M	210863317	30	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152251160	30
T63	17741	1
T67	7811	1
T69	14921	2
T70	8111	2
T71	2948	1
T72	5256	1
T133	7401	1
T134	8058	3
T140	5250	2
T144	10102	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	210863317	30
T63	8515	1
T67	7498	1
T69	7162	2
T70	16927	2
T71	11791	1
T72	10092	1
T133	25377	1
T134	16818	3
T140	11455	2
T144	10102	3

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T63,T70,T71
1	0	Covered	T63,T70,T71
1	1	Covered	T71,T134,T144

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T63,T70,T71
1	0	Covered	T71,T134,T144
1	1	Covered	T63,T70,T71

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152251160	25	0	0
SrcPulseCheck_M	210863317	25	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152251160	25
T63	17741	1
T67	7811	1
T70	8111	2
T71	2948	2
T132	3825	1
T133	7401	1
T134	8058	3
T138	17660	1
T140	5250	1
T144	10102	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	210863317	25
T63	8515	1
T67	7498	1
T70	16927	2
T71	11791	2
T132	4590	1
T133	25377	1
T134	16818	3
T138	8830	1
T140	11455	1
T144	10102	3

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T1,T2,T28
1	0	Covered	T1,T2,T28
1	1	Covered	T1,T2,T28

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T1,T2,T28
1	0	Covered	T1,T2,T28
1	1	Covered	T1,T2,T28

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	409801198	91199	0	0
SrcPulseCheck_M	13936137	90672	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	409801198	91199
T1	834565	650
T2	721077	1635
T3	0	2286
T5	129534	0
T10	0	1243
T17	11773	0
T18	6315	0
T19	3447	0
T20	10224	0
T21	2847	0
T22	3418	0
T23	1447	0
T26	0	16
T28	0	90
T29	0	152
T30	0	88
T31	0	58
T32	0	107

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	13936137	90672
T1	5758	650
T2	341313	1636
T3	0	2286
T5	286	0
T10	0	1126
T17	858	0
T18	460	0
T19	251	0
T20	745	0
T21	207	0
T22	248	0
T23	105	0
T26	0	16
T28	0	90
T29	0	152
T30	0	88
T31	0	58
T32	0	107

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T1,T2,T28
1	0	Covered	T1,T2,T28
1	1	Covered	T1,T2,T28

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T1,T2,T28
1	0	Covered	T1,T2,T28
1	1	Covered	T1,T2,T28

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	205447380	90750	0	0
SrcPulseCheck_M	13936137	90225	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	205447380	90750
T1	418541	650
T2	360307	1629
T3	0	2286
T5	37869	0
T10	0	1243
T17	7160	0
T18	3164	0
T19	1698	0
T20	5510	0
T21	1356	0
T22	1662	0
T23	684	0
T26	0	16
T28	0	90
T29	0	152
T30	0	88
T31	0	58
T32	0	107

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	13936137	90225
T1	5758	650
T2	341313	1630
T3	0	2286
T5	286	0
T10	0	1126
T17	858	0
T18	460	0
T19	251	0
T20	745	0
T21	207	0
T22	248	0
T23	105	0
T26	0	16
T28	0	90
T29	0	152
T30	0	88
T31	0	58
T32	0	107

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T1,T2,T28
1	0	Covered	T1,T2,T28
1	1	Covered	T1,T2,T28

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T1,T2,T28
1	0	Covered	T1,T2,T28
1	1	Covered	T1,T2,T28

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	102723095	89730	0	0
SrcPulseCheck_M	13936137	89206	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	102723095	89730
T1	209268	648
T2	180152	1621
T3	0	2286
T5	18935	0
T10	0	1243
T17	3580	0
T18	1582	0
T19	849	0
T20	2754	0
T21	678	0
T22	831	0
T23	342	0
T26	0	14
T28	0	90
T29	0	152
T30	0	88
T31	0	58
T32	0	107

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	13936137	89206
T1	5758	648
T2	341313	1622
T3	0	2286
T5	286	0
T10	0	1126
T17	858	0
T18	460	0
T19	251	0
T20	745	0
T21	207	0
T22	248	0
T23	105	0
T26	0	14
T28	0	90
T29	0	152
T30	0	88
T31	0	58
T32	0	107

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T1,T2,T28
1	0	Covered	T1,T2,T28
1	1	Covered	T1,T2,T28

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T1,T2,T28
1	0	Covered	T1,T2,T28
1	1	Covered	T1,T2,T28

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	437016983	108659	0	0
SrcPulseCheck_M	13960541	108662	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	437016983	108659
T1	983365	839
T2	770346	1998
T3	0	2710
T5	134935	0
T10	0	1329
T17	12263	0
T18	6577	0
T19	3591	0
T20	10650	0
T21	2965	0
T22	3560	0
T23	1506	0
T26	0	14
T28	0	90
T29	0	308
T30	0	160
T31	0	70
T32	0	167

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	13960541	108662
T1	5986	839
T2	341697	1998
T3	0	2710
T5	286	0
T10	0	1329
T17	858	0
T18	460	0
T19	251	0
T20	745	0
T21	207	0
T22	248	0
T23	105	0
T26	0	14
T28	0	90
T29	0	308
T30	0	160
T31	0	70
T32	0	167

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T1,T2,T28
1	0	Covered	T1,T2,T28
1	1	Covered	T1,T2,T28

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T1,T2,T28
1	0	Covered	T1,T2,T28
1	1	Covered	T1,T2,T28

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T6,T7

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	209733488	107337	0	0
SrcPulseCheck_M	13522613	105967	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	209733488	107337
T1	463382	775
T2	369772	1998
T3	0	2631
T5	64770	0
T10	0	1368
T17	5886	0
T18	3157	0
T19	1724	0
T20	5112	0
T21	1423	0
T22	1708	0
T23	723	0
T26	0	14
T28	0	126
T29	0	296
T30	0	136
T31	0	54
T32	0	167

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	13522613	105967
T1	5950	775
T2	341697	1999
T3	0	2631
T5	286	0
T10	0	1368
T17	858	0
T18	460	0
T19	251	0
T20	745	0
T21	207	0
T22	248	0
T23	105	0
T26	0	14
T28	0	126
T29	0	296
T30	0	136
T31	0	54
T32	0	167

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb