Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1522511600	1385568	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1522511600	267841	0	0
SrcBusyKnown_A	1522511600	1494842640	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1522511600	1385568	0	0
T1	1722700	4623	0	0
T2	0	25785	0	0
T3	0	47574	0	0
T4	302760	1853	0	0
T5	323830	1612	0	0
T6	17050	0	0	0
T7	20080	0	0	0
T17	15940	0	0	0
T18	15130	0	0	0
T19	35200	0	0	0
T24	21510	0	0	0
T25	11870	0	0	0
T28	0	1239	0	0
T29	0	2088	0	0
T30	0	1613	0	0
T31	0	272	0	0
T32	0	1994	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5818242	5811814	0	0
T4	751266	101196	0	0
T5	772086	232272	0	0
T6	21354	19856	0	0
T7	13530	12664	0	0
T17	81324	80370	0	0
T18	41590	40686	0	0
T19	22618	21900	0	0
T24	28274	27244	0	0
T25	34014	33408	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1522511600	267841	0	0
T1	1722700	1500	0	0
T2	0	5035	0	0
T3	0	6010	0	0
T4	302760	536	0	0
T5	323830	472	0	0
T6	17050	0	0	0
T7	20080	0	0	0
T17	15940	0	0	0
T18	15130	0	0	0
T19	35200	0	0	0
T24	21510	0	0	0
T25	11870	0	0	0
T28	0	160	0	0
T29	0	400	0	0
T30	0	200	0	0
T31	0	80	0	0
T32	0	240	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1522511600	1494842640	0	0
T1	1722700	1720770	0	0
T4	302760	36830	0	0
T5	323830	88360	0	0
T6	17050	15700	0	0
T7	20080	18490	0	0
T17	15940	15710	0	0
T18	15130	14750	0	0
T19	35200	33960	0	0
T24	21510	20700	0	0
T25	11870	11620	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152251160	86632	0	0
DstReqKnown_A	412060805	407350824	0	0
SrcAckBusyChk_A	152251160	24185	0	0
SrcBusyKnown_A	152251160	149484264	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	86632	0	0
T1	172270	377	0	0
T2	0	1783	0	0
T3	0	2954	0	0
T4	30276	96	0	0
T5	32383	81	0	0
T6	1705	0	0	0
T7	2008	0	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T24	2151	0	0	0
T25	1187	0	0	0
T28	0	76	0	0
T29	0	146	0	0
T30	0	103	0	0
T31	0	20	0	0
T32	0	123	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412060805	407350824	0	0
T1	834565	833471	0	0
T4	126366	15370	0	0
T5	129534	35281	0	0
T6	3274	3016	0	0
T7	2050	1888	0	0
T17	11773	11597	0	0
T18	6315	6153	0	0
T19	3447	3326	0	0
T24	4300	4138	0	0
T25	5182	5075	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	24185	0	0
T1	172270	150	0	0
T2	0	497	0	0
T3	0	596	0	0
T4	30276	38	0	0
T5	32383	32	0	0
T6	1705	0	0	0
T7	2008	0	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T24	2151	0	0	0
T25	1187	0	0	0
T28	0	16	0	0
T29	0	40	0	0
T30	0	20	0	0
T31	0	8	0	0
T32	0	24	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	149484264	0	0
T1	172270	172077	0	0
T4	30276	3683	0	0
T5	32383	8836	0	0
T6	1705	1570	0	0
T7	2008	1849	0	0
T17	1594	1571	0	0
T18	1513	1475	0	0
T19	3520	3396	0	0
T24	2151	2070	0	0
T25	1187	1162	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152251160	124905	0	0
DstReqKnown_A	206532727	205334126	0	0
SrcAckBusyChk_A	152251160	24185	0	0
SrcBusyKnown_A	152251160	149484264	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	124905	0	0
T1	172270	467	0	0
T2	0	2560	0	0
T3	0	4729	0	0
T4	30276	133	0	0
T5	32383	113	0	0
T6	1705	0	0	0
T7	2008	0	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T24	2151	0	0	0
T25	1187	0	0	0
T28	0	125	0	0
T29	0	211	0	0
T30	0	161	0	0
T31	0	28	0	0
T32	0	195	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206532727	205334126	0	0
T1	418541	418253	0	0
T4	36295	7687	0	0
T5	37869	17640	0	0
T6	1570	1508	0	0
T7	1037	1023	0	0
T17	7160	7139	0	0
T18	3164	3136	0	0
T19	1698	1663	0	0
T24	2138	2069	0	0
T25	2558	2537	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	24185	0	0
T1	172270	150	0	0
T2	0	497	0	0
T3	0	596	0	0
T4	30276	38	0	0
T5	32383	32	0	0
T6	1705	0	0	0
T7	2008	0	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T24	2151	0	0	0
T25	1187	0	0	0
T28	0	16	0	0
T29	0	40	0	0
T30	0	20	0	0
T31	0	8	0	0
T32	0	24	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	149484264	0	0
T1	172270	172077	0	0
T4	30276	3683	0	0
T5	32383	8836	0	0
T6	1705	1570	0	0
T7	2008	1849	0	0
T17	1594	1571	0	0
T18	1513	1475	0	0
T19	3520	3396	0	0
T24	2151	2070	0	0
T25	1187	1162	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152251160	200171	0	0
DstReqKnown_A	103265749	102666534	0	0
SrcAckBusyChk_A	152251160	24185	0	0
SrcBusyKnown_A	152251160	149484264	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	200171	0	0
T1	172270	617	0	0
T2	0	4068	0	0
T3	0	8208	0	0
T4	30276	190	0	0
T5	32383	162	0	0
T6	1705	0	0	0
T7	2008	0	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T24	2151	0	0	0
T25	1187	0	0	0
T28	0	219	0	0
T29	0	333	0	0
T30	0	281	0	0
T31	0	40	0	0
T32	0	342	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103265749	102666534	0	0
T1	209268	209123	0	0
T4	18150	3846	0	0
T5	18935	8821	0	0
T6	785	754	0	0
T7	517	510	0	0
T17	3580	3570	0	0
T18	1582	1568	0	0
T19	849	832	0	0
T24	1069	1035	0	0
T25	1279	1269	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	24185	0	0
T1	172270	150	0	0
T2	0	497	0	0
T3	0	596	0	0
T4	30276	38	0	0
T5	32383	32	0	0
T6	1705	0	0	0
T7	2008	0	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T24	2151	0	0	0
T25	1187	0	0	0
T28	0	16	0	0
T29	0	40	0	0
T30	0	20	0	0
T31	0	8	0	0
T32	0	24	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	149484264	0	0
T1	172270	172077	0	0
T4	30276	3683	0	0
T5	32383	8836	0	0
T6	1705	1570	0	0
T7	2008	1849	0	0
T17	1594	1571	0	0
T18	1513	1475	0	0
T19	3520	3396	0	0
T24	2151	2070	0	0
T25	1187	1162	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152251160	84956	0	0
DstReqKnown_A	439370856	434384579	0	0
SrcAckBusyChk_A	152251160	24185	0	0
SrcBusyKnown_A	152251160	149484264	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	84956	0	0
T1	172270	377	0	0
T2	0	1748	0	0
T3	0	2899	0	0
T4	30276	96	0	0
T5	32383	81	0	0
T6	1705	0	0	0
T7	2008	0	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T24	2151	0	0	0
T25	1187	0	0	0
T28	0	75	0	0
T29	0	142	0	0
T30	0	98	0	0
T31	0	20	0	0
T32	0	142	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439370856	434384579	0	0
T1	983365	982225	0	0
T4	131636	16010	0	0
T5	134935	36752	0	0
T6	3411	3142	0	0
T7	2136	1967	0	0
T17	12263	12080	0	0
T18	6577	6409	0	0
T19	3591	3465	0	0
T24	4479	4310	0	0
T25	5398	5286	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	24185	0	0
T1	172270	150	0	0
T2	0	497	0	0
T3	0	596	0	0
T4	30276	38	0	0
T5	32383	32	0	0
T6	1705	0	0	0
T7	2008	0	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T24	2151	0	0	0
T25	1187	0	0	0
T28	0	16	0	0
T29	0	40	0	0
T30	0	20	0	0
T31	0	8	0	0
T32	0	24	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	149484264	0	0
T1	172270	172077	0	0
T4	30276	3683	0	0
T5	32383	8836	0	0
T6	1705	1570	0	0
T7	2008	1849	0	0
T17	1594	1571	0	0
T18	1513	1475	0	0
T19	3520	3396	0	0
T24	2151	2070	0	0
T25	1187	1162	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152251160	122159	0	0
DstReqKnown_A	210863317	208486524	0	0
SrcAckBusyChk_A	152251160	23642	0	0
SrcBusyKnown_A	152251160	149484264	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	122159	0	0
T1	172270	468	0	0
T2	0	2556	0	0
T3	0	4716	0	0
T4	30276	82	0	0
T5	32383	106	0	0
T6	1705	0	0	0
T7	2008	0	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T24	2151	0	0	0
T25	1187	0	0	0
T28	0	119	0	0
T29	0	208	0	0
T30	0	160	0	0
T31	0	28	0	0
T32	0	198	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210863317	208486524	0	0
T1	463382	462835	0	0
T4	63186	7685	0	0
T5	64770	17642	0	0
T6	1637	1508	0	0
T7	1025	944	0	0
T17	5886	5799	0	0
T18	3157	3077	0	0
T19	1724	1664	0	0
T24	2151	2070	0	0
T25	2590	2537	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	23642	0	0
T1	172270	150	0	0
T2	0	497	0	0
T3	0	596	0	0
T4	30276	19	0	0
T5	32383	25	0	0
T6	1705	0	0	0
T7	2008	0	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T24	2151	0	0	0
T25	1187	0	0	0
T28	0	16	0	0
T29	0	40	0	0
T30	0	20	0	0
T31	0	8	0	0
T32	0	24	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	149484264	0	0
T1	172270	172077	0	0
T4	30276	3683	0	0
T5	32383	8836	0	0
T6	1705	1570	0	0
T7	2008	1849	0	0
T17	1594	1571	0	0
T18	1513	1475	0	0
T19	3520	3396	0	0
T24	2151	2070	0	0
T25	1187	1162	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152251160	107230	0	0
DstReqKnown_A	412060805	407350824	0	0
SrcAckBusyChk_A	152251160	29671	0	0
SrcBusyKnown_A	152251160	149484264	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	107230	0	0
T1	172270	380	0	0
T2	0	1823	0	0
T3	0	3010	0	0
T4	30276	189	0	0
T5	32383	157	0	0
T6	1705	0	0	0
T7	2008	0	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T24	2151	0	0	0
T25	1187	0	0	0
T28	0	78	0	0
T29	0	143	0	0
T30	0	103	0	0
T31	0	20	0	0
T32	0	123	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412060805	407350824	0	0
T1	834565	833471	0	0
T4	126366	15370	0	0
T5	129534	35281	0	0
T6	3274	3016	0	0
T7	2050	1888	0	0
T17	11773	11597	0	0
T18	6315	6153	0	0
T19	3447	3326	0	0
T24	4300	4138	0	0
T25	5182	5075	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	29671	0	0
T1	172270	150	0	0
T2	0	510	0	0
T3	0	606	0	0
T4	30276	76	0	0
T5	32383	64	0	0
T6	1705	0	0	0
T7	2008	0	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T24	2151	0	0	0
T25	1187	0	0	0
T28	0	16	0	0
T29	0	40	0	0
T30	0	20	0	0
T31	0	8	0	0
T32	0	24	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	149484264	0	0
T1	172270	172077	0	0
T4	30276	3683	0	0
T5	32383	8836	0	0
T6	1705	1570	0	0
T7	2008	1849	0	0
T17	1594	1571	0	0
T18	1513	1475	0	0
T19	3520	3396	0	0
T24	2151	2070	0	0
T25	1187	1162	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152251160	153680	0	0
DstReqKnown_A	206532727	205334126	0	0
SrcAckBusyChk_A	152251160	29447	0	0
SrcBusyKnown_A	152251160	149484264	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	153680	0	0
T1	172270	472	0	0
T2	0	2616	0	0
T3	0	4826	0	0
T4	30276	265	0	0
T5	32383	221	0	0
T6	1705	0	0	0
T7	2008	0	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T24	2151	0	0	0
T25	1187	0	0	0
T28	0	127	0	0
T29	0	210	0	0
T30	0	162	0	0
T31	0	28	0	0
T32	0	196	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206532727	205334126	0	0
T1	418541	418253	0	0
T4	36295	7687	0	0
T5	37869	17640	0	0
T6	1570	1508	0	0
T7	1037	1023	0	0
T17	7160	7139	0	0
T18	3164	3136	0	0
T19	1698	1663	0	0
T24	2138	2069	0	0
T25	2558	2537	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	29447	0	0
T1	172270	150	0	0
T2	0	510	0	0
T3	0	606	0	0
T4	30276	76	0	0
T5	32383	64	0	0
T6	1705	0	0	0
T7	2008	0	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T24	2151	0	0	0
T25	1187	0	0	0
T28	0	16	0	0
T29	0	40	0	0
T30	0	20	0	0
T31	0	8	0	0
T32	0	24	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	149484264	0	0
T1	172270	172077	0	0
T4	30276	3683	0	0
T5	32383	8836	0	0
T6	1705	1570	0	0
T7	2008	1849	0	0
T17	1594	1571	0	0
T18	1513	1475	0	0
T19	3520	3396	0	0
T24	2151	2070	0	0
T25	1187	1162	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152251160	248160	0	0
DstReqKnown_A	103265749	102666534	0	0
SrcAckBusyChk_A	152251160	29551	0	0
SrcBusyKnown_A	152251160	149484264	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	248160	0	0
T1	172270	617	0	0
T2	0	4230	0	0
T3	0	8460	0	0
T4	30276	363	0	0
T5	32383	314	0	0
T6	1705	0	0	0
T7	2008	0	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T24	2151	0	0	0
T25	1187	0	0	0
T28	0	218	0	0
T29	0	339	0	0
T30	0	285	0	0
T31	0	40	0	0
T32	0	341	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103265749	102666534	0	0
T1	209268	209123	0	0
T4	18150	3846	0	0
T5	18935	8821	0	0
T6	785	754	0	0
T7	517	510	0	0
T17	3580	3570	0	0
T18	1582	1568	0	0
T19	849	832	0	0
T24	1069	1035	0	0
T25	1279	1269	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	29551	0	0
T1	172270	150	0	0
T2	0	510	0	0
T3	0	606	0	0
T4	30276	76	0	0
T5	32383	64	0	0
T6	1705	0	0	0
T7	2008	0	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T24	2151	0	0	0
T25	1187	0	0	0
T28	0	16	0	0
T29	0	40	0	0
T30	0	20	0	0
T31	0	8	0	0
T32	0	24	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	149484264	0	0
T1	172270	172077	0	0
T4	30276	3683	0	0
T5	32383	8836	0	0
T6	1705	1570	0	0
T7	2008	1849	0	0
T17	1594	1571	0	0
T18	1513	1475	0	0
T19	3520	3396	0	0
T24	2151	2070	0	0
T25	1187	1162	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152251160	105073	0	0
DstReqKnown_A	439370856	434384579	0	0
SrcAckBusyChk_A	152251160	29660	0	0
SrcBusyKnown_A	152251160	149484264	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	105073	0	0
T1	172270	380	0	0
T2	0	1787	0	0
T3	0	2952	0	0
T4	30276	189	0	0
T5	32383	157	0	0
T6	1705	0	0	0
T7	2008	0	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T24	2151	0	0	0
T25	1187	0	0	0
T28	0	76	0	0
T29	0	144	0	0
T30	0	100	0	0
T31	0	20	0	0
T32	0	142	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439370856	434384579	0	0
T1	983365	982225	0	0
T4	131636	16010	0	0
T5	134935	36752	0	0
T6	3411	3142	0	0
T7	2136	1967	0	0
T17	12263	12080	0	0
T18	6577	6409	0	0
T19	3591	3465	0	0
T24	4479	4310	0	0
T25	5398	5286	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	29660	0	0
T1	172270	150	0	0
T2	0	510	0	0
T3	0	606	0	0
T4	30276	76	0	0
T5	32383	64	0	0
T6	1705	0	0	0
T7	2008	0	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T24	2151	0	0	0
T25	1187	0	0	0
T28	0	16	0	0
T29	0	40	0	0
T30	0	20	0	0
T31	0	8	0	0
T32	0	24	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	149484264	0	0
T1	172270	172077	0	0
T4	30276	3683	0	0
T5	32383	8836	0	0
T6	1705	1570	0	0
T7	2008	1849	0	0
T17	1594	1571	0	0
T18	1513	1475	0	0
T19	3520	3396	0	0
T24	2151	2070	0	0
T25	1187	1162	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	152251160	152602	0	0
DstReqKnown_A	210863317	208486524	0	0
SrcAckBusyChk_A	152251160	29130	0	0
SrcBusyKnown_A	152251160	149484264	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	152602	0	0
T1	172270	468	0	0
T2	0	2614	0	0
T3	0	4820	0	0
T4	30276	250	0	0
T5	32383	220	0	0
T6	1705	0	0	0
T7	2008	0	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T24	2151	0	0	0
T25	1187	0	0	0
T28	0	126	0	0
T29	0	212	0	0
T30	0	160	0	0
T31	0	28	0	0
T32	0	192	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210863317	208486524	0	0
T1	463382	462835	0	0
T4	63186	7685	0	0
T5	64770	17642	0	0
T6	1637	1508	0	0
T7	1025	944	0	0
T17	5886	5799	0	0
T18	3157	3077	0	0
T19	1724	1664	0	0
T24	2151	2070	0	0
T25	2590	2537	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	29130	0	0
T1	172270	150	0	0
T2	0	510	0	0
T3	0	606	0	0
T4	30276	61	0	0
T5	32383	63	0	0
T6	1705	0	0	0
T7	2008	0	0	0
T17	1594	0	0	0
T18	1513	0	0	0
T19	3520	0	0	0
T24	2151	0	0	0
T25	1187	0	0	0
T28	0	16	0	0
T29	0	40	0	0
T30	0	20	0	0
T31	0	8	0	0
T32	0	24	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152251160	149484264	0	0
T1	172270	172077	0	0
T4	30276	3683	0	0
T5	32383	8836	0	0
T6	1705	1570	0	0
T7	2008	1849	0	0
T17	1594	1571	0	0
T18	1513	1475	0	0
T19	3520	3396	0	0
T24	2151	2070	0	0
T25	1187	1162	0	0