Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T2,T17
0	1	Covered	T2,T102,T3
1	0	Covered	T1,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T102
1	0	Covered	T5,T17,T38
1	1	Covered	T1,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1155539087	14474	0	0
GateOpen_A	1155539087	20966	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155539087	14474	0	0
T2	2244225	332	0	0
T3	0	277	0	0
T5	3210	21	0	0
T6	12903	0	0	0
T17	7883	16	0	0
T18	41065	0	0	0
T19	13038	0	0	0
T20	19241	0	0	0
T21	4568	0	0	0
T22	4104	0	0	0
T38	0	8	0	0
T61	5035	0	0	0
T67	0	6	0	0
T102	0	26	0	0
T166	0	10	0	0
T167	0	14	0	0
T168	0	8	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155539087	20966	0	0
T1	456897	4	0	0
T2	2244225	338	0	0
T4	0	44	0	0
T5	3210	25	0	0
T6	12903	0	0	0
T17	7883	20	0	0
T18	41065	4	0	0
T19	13038	4	0	0
T20	19241	0	0	0
T21	4568	4	0	0
T22	4104	4	0	0
T39	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T2,T17
0	1	Covered	T2,T102,T3
1	0	Covered	T1,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T102
1	0	Covered	T5,T17,T38
1	1	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	127679568	3437	0	0
GateOpen_A	127679568	5059	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127679568	3437	0	0
T2	248345	81	0	0
T3	0	63	0	0
T5	338	6	0	0
T6	1482	0	0	0
T17	877	4	0	0
T18	4543	0	0	0
T19	1470	0	0	0
T20	2874	0	0	0
T21	513	0	0	0
T22	452	0	0	0
T38	0	2	0	0
T61	572	0	0	0
T67	0	2	0	0
T102	0	5	0	0
T166	0	3	0	0
T167	0	4	0	0
T168	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127679568	5059	0	0
T1	50760	1	0	0
T2	248345	82	0	0
T4	0	11	0	0
T5	338	7	0	0
T6	1482	0	0	0
T17	877	5	0	0
T18	4543	1	0	0
T19	1470	1	0	0
T20	2874	0	0	0
T21	513	1	0	0
T22	452	1	0	0
T39	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T2,T17
0	1	Covered	T2,T102,T3
1	0	Covered	T1,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T102
1	0	Covered	T5,T17,T38
1	1	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	255360011	3679	0	0
GateOpen_A	255360011	5301	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255360011	3679	0	0
T2	496693	83	0	0
T3	0	74	0	0
T5	676	6	0	0
T6	2966	0	0	0
T17	1753	4	0	0
T18	9085	0	0	0
T19	2939	0	0	0
T20	5753	0	0	0
T21	1025	0	0	0
T22	904	0	0	0
T38	0	2	0	0
T61	1143	0	0	0
T67	0	1	0	0
T102	0	7	0	0
T166	0	3	0	0
T167	0	4	0	0
T168	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255360011	5301	0	0
T1	101519	1	0	0
T2	496693	84	0	0
T4	0	11	0	0
T5	676	7	0	0
T6	2966	0	0	0
T17	1753	5	0	0
T18	9085	1	0	0
T19	2939	1	0	0
T20	5753	0	0	0
T21	1025	1	0	0
T22	904	1	0	0
T39	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T2,T17
0	1	Covered	T2,T102,T3
1	0	Covered	T1,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T102
1	0	Covered	T5,T17,T38
1	1	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	511072887	3694	0	0
GateOpen_A	511072887	5318	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511072887	3694	0	0
T2	993946	84	0	0
T3	0	71	0	0
T5	1430	6	0	0
T6	5636	0	0	0
T17	3543	4	0	0
T18	18291	0	0	0
T19	5752	0	0	0
T20	7076	0	0	0
T21	2020	0	0	0
T22	1832	0	0	0
T38	0	2	0	0
T61	2213	0	0	0
T67	0	1	0	0
T102	0	7	0	0
T166	0	3	0	0
T167	0	4	0	0
T168	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511072887	5318	0	0
T1	203075	1	0	0
T2	993946	86	0	0
T4	0	11	0	0
T5	1430	7	0	0
T6	5636	0	0	0
T17	3543	5	0	0
T18	18291	1	0	0
T19	5752	1	0	0
T20	7076	0	0	0
T21	2020	1	0	0
T22	1832	1	0	0
T39	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T2,T17
0	1	Covered	T2,T102,T3
1	0	Covered	T1,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T102
1	0	Covered	T5,T17,T38
1	1	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	261426621	3664	0	0
GateOpen_A	261426621	5288	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261426621	3664	0	0
T2	505241	84	0	0
T3	0	69	0	0
T5	766	3	0	0
T6	2819	0	0	0
T17	1710	4	0	0
T18	9146	0	0	0
T19	2877	0	0	0
T20	3538	0	0	0
T21	1010	0	0	0
T22	916	0	0	0
T38	0	2	0	0
T61	1107	0	0	0
T67	0	2	0	0
T102	0	7	0	0
T166	0	1	0	0
T167	0	2	0	0
T168	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261426621	5288	0	0
T1	101543	1	0	0
T2	505241	86	0	0
T4	0	11	0	0
T5	766	4	0	0
T6	2819	0	0	0
T17	1710	5	0	0
T18	9146	1	0	0
T19	2877	1	0	0
T20	3538	0	0	0
T21	1010	1	0	0
T22	916	1	0	0
T39	0	1	0	0