Unified Coverage Report :: Module :: clkmgr

Module : clkmgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	100.00	93.15	90.16		100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	98.63	100.00	93.15	100.00		100.00	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.63	100.00	93.15	100.00		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.47	99.15	95.84	100.00	100.00	98.81	97.01

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
clkmgr_aes_trans_sva_if	100.00						100.00
clkmgr_aon_cg_aon_peri	100.00						100.00
clkmgr_aon_cg_aon_powerup	100.00						100.00
clkmgr_aon_cg_aon_secure	100.00						100.00
clkmgr_aon_cg_aon_timers	100.00						100.00
clkmgr_aon_cg_io_div2_powerup	100.00						100.00
clkmgr_aon_cg_io_div4_powerup	100.00						100.00
clkmgr_aon_cg_io_powerup	100.00						100.00
clkmgr_aon_cg_main_powerup	100.00						100.00
clkmgr_aon_cg_usb_powerup	100.00						100.00
clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00
clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
clkmgr_csr_assert	100.00						100.00
clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
clkmgr_div4_sva_if	100.00	100.00	100.00				100.00
clkmgr_extclk_sva_if	100.00	100.00	100.00				100.00
clkmgr_hmac_trans_sva_if	100.00						100.00
clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
clkmgr_kmac_trans_sva_if	100.00						100.00
clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
clkmgr_lost_calib_regwen_sva_if	100.00						100.00
clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
clkmgr_otbn_trans_sva_if	100.00						100.00
clkmgr_pwrmgr_sva_if	100.00						100.00
clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00
clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	99.30	100.00				100.00	97.90
u_calib_rdy_sync	100.00	100.00				100.00	100.00
u_clk_aon_buf	100.00	100.00
u_clk_aon_peri_buf	100.00	100.00
u_clk_aon_powerup_buf	100.00	100.00
u_clk_aon_secure_buf	100.00	100.00
u_clk_aon_timers_buf	100.00	100.00
u_clk_io_buf	100.00	100.00
u_clk_io_div2_peri_cg	100.00	100.00	100.00			100.00
u_clk_io_div2_peri_scanmode_sync	100.00	100.00					100.00
u_clk_io_div2_peri_sw_en_sync	100.00	100.00				100.00
u_clk_io_div2_powerup_buf	100.00	100.00
u_clk_io_div4_peri_cg	100.00	100.00	100.00			100.00
u_clk_io_div4_peri_scanmode_sync	100.00	100.00					100.00
u_clk_io_div4_peri_sw_en_sync	100.00	100.00				100.00
u_clk_io_div4_powerup_buf	100.00	100.00
u_clk_io_peri_cg	100.00	100.00	100.00			100.00
u_clk_io_peri_scanmode_sync	100.00	100.00					100.00
u_clk_io_peri_sw_en_sync	100.00	100.00				100.00
u_clk_io_powerup_buf	100.00	100.00
u_clk_main_aes_trans	100.00	100.00	100.00	100.00		100.00	100.00
u_clk_main_buf	100.00	100.00
u_clk_main_hmac_trans	100.00	100.00	100.00	100.00		100.00	100.00
u_clk_main_kmac_trans	100.00	100.00	100.00	100.00		100.00	100.00
u_clk_main_otbn_trans	100.00	100.00	100.00	100.00		100.00	100.00
u_clk_main_powerup_buf	100.00	100.00
u_clk_usb_buf	100.00	100.00
u_clk_usb_peri_cg	100.00	100.00	100.00			100.00
u_clk_usb_peri_scanmode_sync	100.00	100.00					100.00
u_clk_usb_peri_sw_en_sync	100.00	100.00				100.00
u_clk_usb_powerup_buf	100.00	100.00
u_clkmgr_byp	100.00	100.00	100.00			100.00	100.00
u_io_div2_div_scanmode_sync	100.00	100.00					100.00
u_io_div2_meas	95.78	100.00	95.56		100.00	100.00	83.33
u_io_div2_root_ctrl	100.00	100.00	100.00			100.00	100.00
u_io_div4_div_scanmode_sync	100.00	100.00					100.00
u_io_div4_meas	95.78	100.00	95.56		100.00	100.00	83.33
u_io_div4_root_ctrl	100.00	100.00	100.00			100.00	100.00
u_io_meas	95.78	100.00	95.56		100.00	100.00	83.33
u_io_root_ctrl	100.00	100.00	100.00			100.00	100.00
u_io_status	100.00	100.00				100.00
u_io_step_down_req_sync	100.00	100.00	100.00			100.00	100.00
u_main_meas	95.78	100.00	95.56		100.00	100.00	83.33
u_main_root_ctrl	100.00	100.00	100.00			100.00	100.00
u_main_status	100.00	100.00				100.00
u_no_scan_io_div2_div	100.00	100.00	100.00			100.00	100.00
u_no_scan_io_div4_div	100.00	100.00	100.00			100.00	100.00
u_prim_mubi4_sender_clk_io_div2_infra	100.00	100.00				100.00	100.00
u_prim_mubi4_sender_clk_io_div2_peri	100.00	100.00				100.00	100.00
u_prim_mubi4_sender_clk_io_div4_infra	100.00	100.00				100.00	100.00
u_prim_mubi4_sender_clk_io_div4_peri	100.00	100.00				100.00	100.00
u_prim_mubi4_sender_clk_io_div4_secure	100.00	100.00				100.00	100.00
u_prim_mubi4_sender_clk_io_div4_timers	100.00	100.00				100.00	100.00
u_prim_mubi4_sender_clk_io_infra	100.00	100.00				100.00	100.00
u_prim_mubi4_sender_clk_io_peri	100.00	100.00				100.00	100.00
u_prim_mubi4_sender_clk_main_infra	100.00	100.00				100.00	100.00
u_prim_mubi4_sender_clk_main_secure	100.00	100.00				100.00	100.00
u_prim_mubi4_sender_clk_usb_infra	100.00	100.00				100.00	100.00
u_prim_mubi4_sender_clk_usb_peri	100.00	100.00				100.00	100.00
u_reg	97.64	98.39	95.42	100.00		97.91	96.48
u_usb_meas	95.78	100.00	95.56		100.00	100.00	83.33
u_usb_root_ctrl	100.00	100.00	100.00			100.00	100.00
u_usb_status	100.00	100.00				100.00

Line Coverage for Module : clkmgr

	Line No.	Total	Covered	Percent
TOTAL		34	34	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	310	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	437	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
ALWAYS	552	5	5	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	743	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	765	1	1	100.00
CONT_ASSIGN	776	1	1	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	861	1	1	100.00
CONT_ASSIGN	903	1	1	100.00
CONT_ASSIGN	945	1	1	100.00
CONT_ASSIGN	1062	1	1	100.00
CONT_ASSIGN	1071	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
260	1	1
266	1	1
279	1	1
309	1	1
310	1	1
408	1	1
413	1	1
414	1	1
415	1	1
418	1	1
437	1	1
462	1	1
474	1	1
486	1	1
511	1	1
552	1	1
553	1	1
555	1	1
556	1	1
557	1	1
			MISSING_ELSE
699	1	1
710	1	1
721	1	1
732	1	1
743	1	1
754	1	1
765	1	1
776	1	1
819	1	1
861	1	1
903	1	1
945	1	1
1062	1	1
1071	1	1

---

Cond Coverage for Module : clkmgr

	Total	Covered	Percent
Conditions	146	136	93.15
Logical	146	136	93.15
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       37
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       46
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       55
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       65
 EXPRESSION (idle_i[0] == MuBi4True)
            ------------1-----------

-1-	Status	Tests
0	Covered	T5,T6,T2
1	Covered	T1,T5,T6

 LINE       65
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       75
 EXPRESSION (idle_i[1] == MuBi4True)
            ------------1-----------

-1-	Status	Tests
0	Covered	T5,T6,T2
1	Covered	T1,T5,T6

 LINE       75
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       85
 EXPRESSION (idle_i[2] == MuBi4True)
            ------------1-----------

-1-	Status	Tests
0	Covered	T5,T6,T2
1	Covered	T1,T5,T6

 LINE       85
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       95
 EXPRESSION (idle_i[3] == MuBi4True)
            ------------1-----------

-1-	Status	Tests
0	Covered	T5,T6,T2
1	Covered	T1,T5,T6

 LINE       95
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       119
 EXPRESSION (div_step_down_req_i == MuBi4True)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       119
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       130
 EXPRESSION (div_step_down_req_i == MuBi4True)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       130
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       139
 EXPRESSION (cg_en_o.aon_peri == MuBi4True)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Not Covered

 LINE       143
 EXPRESSION (cg_en_o.aon_powerup == MuBi4True)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Not Covered

 LINE       147
 EXPRESSION (cg_en_o.aon_secure == MuBi4True)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Not Covered

 LINE       151
 EXPRESSION (cg_en_o.aon_timers == MuBi4True)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Not Covered

 LINE       155
 EXPRESSION (cg_en_o.io_powerup == MuBi4True)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Not Covered

 LINE       159
 EXPRESSION (cg_en_o.io_div2_powerup == MuBi4True)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Not Covered

 LINE       165
 EXPRESSION (cg_en_o.io_div4_powerup == MuBi4True)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Not Covered

 LINE       171
 EXPRESSION (cg_en_o.main_powerup == MuBi4True)
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Not Covered

 LINE       175
 EXPRESSION (cg_en_o.usb_powerup == MuBi4True)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Not Covered

 LINE       180
 EXPRESSION (cg_en_o.io_div2_infra == MuBi4True)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       189
 EXPRESSION (cg_en_o.io_div4_infra == MuBi4True)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       198
 EXPRESSION (cg_en_o.io_infra == MuBi4True)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       207
 EXPRESSION (cg_en_o.main_infra == MuBi4True)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       216
 EXPRESSION (cg_en_o.io_div4_secure == MuBi4True)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       225
 EXPRESSION (cg_en_o.main_secure == MuBi4True)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       234
 EXPRESSION (cg_en_o.io_div4_timers == MuBi4True)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       243
 EXPRESSION (cg_en_o.io_div2_peri == MuBi4True)
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       252
 EXPRESSION (cg_en_o.io_div4_peri == MuBi4True)
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       260
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault.q & reg2hw.alert_test.fatal_fault.qe)
                 ---------------1---------------   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T31,T32
1	0	Covered	T1,T5,T6
1	1	Covered	T18,T31,T32

 LINE       260
 SUB-EXPRESSION (reg2hw.alert_test.recov_fault.q & reg2hw.alert_test.recov_fault.qe)
                 ---------------1---------------   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T31,T32
1	0	Covered	T1,T5,T6
1	1	Covered	T18,T31,T32

 LINE       261
 EXPRESSION (cg_en_o.io_peri == MuBi4True)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       266
 EXPRESSION 
 Number  Term
      1  hw2reg.recov_err_code.io_measure_err.de | 
      2  hw2reg.recov_err_code.io_timeout_err.de | 
      3  hw2reg.recov_err_code.io_div2_measure_err.de | 
      4  hw2reg.recov_err_code.io_div2_timeout_err.de | 
      5  hw2reg.recov_err_code.io_div4_measure_err.de | 
      6  hw2reg.recov_err_code.io_div4_timeout_err.de | 
      7  hw2reg.recov_err_code.main_measure_err.de | 
      8  hw2reg.recov_err_code.main_timeout_err.de | 
      9  hw2reg.recov_err_code.usb_measure_err.de | 
     10  hw2reg.recov_err_code.usb_timeout_err.de | 
     11  hw2reg.recov_err_code.shadow_update_err.de)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T5,T6
0	0	0	0	0	0	0	0	0	0	1	Not Covered
0	0	0	0	0	0	0	0	0	1	0	Covered	T2,T3,T28
0	0	0	0	0	0	0	0	1	0	0	Covered	T1,T2,T23
0	0	0	0	0	0	0	1	0	0	0	Covered	T2,T3,T28
0	0	0	0	0	0	1	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	0	0	0	0	0	Covered	T2,T3,T10
0	0	0	0	1	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	1	0	0	0	0	0	0	0	Covered	T33,T34,T35
0	0	1	0	0	0	0	0	0	0	0	Covered	T1,T2,T3
0	1	0	0	0	0	0	0	0	0	0	Covered	T33,T34,T35
1	0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T23

 LINE       270
 EXPRESSION (cg_en_o.usb_peri == MuBi4True)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       279
 EXPRESSION (clkmgr.u_clk_main_aes_trans.sw_hint_synced || ((!clkmgr.u_clk_main_aes_trans.idle_valid)))
             ---------------------1--------------------    ---------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T36,T37
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       279
 EXPRESSION (cg_en_o.main_aes == MuBi4True)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       288
 EXPRESSION (clkmgr.u_clk_main_hmac_trans.sw_hint_synced || ((!clkmgr.u_clk_main_hmac_trans.idle_valid)))
             ---------------------1---------------------    ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T37,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       288
 EXPRESSION (cg_en_o.main_hmac == MuBi4True)
            ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       297
 EXPRESSION (clkmgr.u_clk_main_kmac_trans.sw_hint_synced || ((!clkmgr.u_clk_main_kmac_trans.idle_valid)))
             ---------------------1---------------------    ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T36,T37
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       297
 EXPRESSION (cg_en_o.main_kmac == MuBi4True)
            ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       306
 EXPRESSION (clkmgr.u_clk_main_otbn_trans.sw_hint_synced || ((!clkmgr.u_clk_main_otbn_trans.idle_valid)))
             ---------------------1---------------------    ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T36,T37
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       306
 EXPRESSION (cg_en_o.main_otbn == MuBi4True)
            ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       704
 EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
             -------1------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       715
 EXPRESSION (clk_main_en ? MuBi4False : MuBi4True)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       726
 EXPRESSION (clk_usb_en ? MuBi4False : MuBi4True)
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       737
 EXPRESSION (clk_io_en ? MuBi4False : MuBi4True)
             ----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       748
 EXPRESSION (clk_io_div2_en ? MuBi4False : MuBi4True)
             -------1------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       759
 EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
             -------1------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       770
 EXPRESSION (clk_main_en ? MuBi4False : MuBi4True)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       781
 EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
             -------1------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       819
 EXPRESSION (clk_io_div4_peri_sw_en & clk_io_div4_en)
             -----------1----------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T5,T17,T38
1	1	Covered	T1,T5,T6

 LINE       832
 EXPRESSION (clk_io_div4_peri_combined_en ? MuBi4False : MuBi4True)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       861
 EXPRESSION (clk_io_div2_peri_sw_en & clk_io_div2_en)
             -----------1----------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T5,T17,T38
1	1	Covered	T1,T5,T6

 LINE       874
 EXPRESSION (clk_io_div2_peri_combined_en ? MuBi4False : MuBi4True)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       903
 EXPRESSION (clk_io_peri_sw_en & clk_io_en)
             --------1--------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T5,T17,T38
1	1	Covered	T1,T5,T6

 LINE       916
 EXPRESSION (clk_io_peri_combined_en ? MuBi4False : MuBi4True)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       945
 EXPRESSION (clk_usb_peri_sw_en & clk_usb_en)
             ---------1--------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T5,T17,T38
1	1	Covered	T1,T5,T6

 LINE       958
 EXPRESSION (clk_usb_peri_combined_en ? MuBi4False : MuBi4True)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

---

Toggle Coverage for Module : clkmgr

	Total	Covered	Percent
Totals	115	106	92.17
Total Bits	732	660	90.16
Total Bits 0->1	366	330	90.16
Total Bits 1->0	366	330	90.16

Ports	115	106	92.17
Port Bits	732	660	90.16
Port Bits 0->1	366	330	90.16
Port Bits 1->0	366	330	90.16

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
rst_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
rst_shadowed_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
clk_main_i	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
rst_main_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
clk_io_i	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
rst_io_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
clk_usb_i	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
clk_aon_i	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
rst_aon_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
rst_io_div2_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
rst_io_div4_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
rst_root_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
rst_root_main_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
rst_root_io_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
rst_root_io_div2_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
rst_root_io_div4_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
rst_root_usb_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T6,T2,T18	Yes	T1,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T22,T39	Yes	T2,T22,T39	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T19	Yes	T1,T2,T19	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	INPUT
tl_i.a_valid	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	INPUT
tl_o.a_ready	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	OUTPUT
tl_o.d_error	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T6,T2	Yes	T1,T6,T2	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T19	Yes	T1,T6,T2	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T6,*T2	Yes	T1,T6,T2	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T18	Yes	T1,T2,T18	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T18,T40,T31	Yes	T18,T40,T31	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T18	Yes	T1,T2,T18	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T18,T40,T31	Yes	T18,T40,T31	OUTPUT
pwr_i.usb_ip_clk_en	Yes	Yes	T5,T17,T38	Yes	T5,T17,T38	INPUT
pwr_i.io_ip_clk_en	Yes	Yes	T5,T17,T38	Yes	T5,T17,T38	INPUT
pwr_i.main_ip_clk_en	Yes	Yes	T5,T17,T38	Yes	T5,T17,T38	INPUT
pwr_o.usb_status	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
pwr_o.io_status	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
pwr_o.main_status	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
scanmode_i[3:0]	Yes	Yes	T6,T2,T19	Yes	T1,T6,T2	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T6,T2,T19	Yes	T6,T2,T19	INPUT
lc_clk_byp_req_i[3:0]	Yes	Yes	T6,T2,T19	Yes	T6,T2,T19	INPUT
lc_clk_byp_ack_o[3:0]	Yes	Yes	T2,T19,T20	Yes	T2,T19,T20	OUTPUT
io_clk_byp_req_o[3:0]	Yes	Yes	T2,T19,T20	Yes	T2,T19,T20	OUTPUT
io_clk_byp_ack_i[3:0]	Yes	Yes	T2,T19,T20	Yes	T2,T19,T20	INPUT
all_clk_byp_req_o[3:0]	Yes	Yes	T6,T2,T19	Yes	T6,T2,T19	OUTPUT
all_clk_byp_ack_i[3:0]	Yes	Yes	T6,T2,T19	Yes	T6,T2,T19	INPUT
hi_speed_sel_o[3:0]	Yes	Yes	T6,T2,T19	Yes	T1,T5,T6	OUTPUT
calib_rdy_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T23	INPUT
jitter_en_o[3:0]	Yes	Yes	T2,T3,T41	Yes	T2,T3,T41	OUTPUT
div_step_down_req_i[3:0]	Yes	Yes	T6,T2,T19	Yes	T6,T2,T19	INPUT
cg_en_o.usb_peri[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.io_peri[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.io_div2_peri[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.io_div4_peri[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.io_div4_timers[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.main_secure[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.io_div4_secure[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.io_div2_infra[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.io_infra[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.usb_infra[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.main_infra[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.io_div4_infra[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.main_otbn[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.main_kmac[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.main_hmac[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.main_aes[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.aon_timers[3:0]	No	No		No		OUTPUT
cg_en_o.aon_peri[3:0]	No	No		No		OUTPUT
cg_en_o.aon_secure[3:0]	No	No		No		OUTPUT
cg_en_o.io_div2_powerup[3:0]	No	No		No		OUTPUT
cg_en_o.usb_powerup[3:0]	No	No		No		OUTPUT
cg_en_o.io_powerup[3:0]	No	No		No		OUTPUT
cg_en_o.main_powerup[3:0]	No	No		No		OUTPUT
cg_en_o.aon_powerup[3:0]	No	No		No		OUTPUT
cg_en_o.io_div4_powerup[3:0]	No	No		No		OUTPUT
clocks_o.clk_usb_peri	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_io_peri	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_io_div2_peri	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_io_div4_peri	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_io_div4_timers	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_main_secure	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_io_div4_secure	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_io_div2_infra	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_io_infra	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_usb_infra	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_main_infra	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_io_div4_infra	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_main_otbn	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_main_kmac	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_main_hmac	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_main_aes	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_aon_timers	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_aon_peri	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_aon_secure	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_io_div2_powerup	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_usb_powerup	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_io_powerup	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_main_powerup	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_aon_powerup	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_io_div4_powerup	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : clkmgr

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
TERNARY	704	2	2	100.00
TERNARY	715	2	2	100.00
TERNARY	726	2	2	100.00
TERNARY	737	2	2	100.00
TERNARY	748	2	2	100.00
TERNARY	759	2	2	100.00
TERNARY	770	2	2	100.00
TERNARY	781	2	2	100.00
TERNARY	832	2	2	100.00
TERNARY	874	2	2	100.00
TERNARY	916	2	2	100.00
TERNARY	958	2	2	100.00
IF	555	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	704	(clk_io_div4_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	715	(clk_main_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	726	(clk_usb_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	737	(clk_io_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	748	(clk_io_div2_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	759	(clk_io_div4_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	770	(clk_main_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	781	(clk_io_div4_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	832	(clk_io_div4_peri_combined_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	874	(clk_io_div2_peri_combined_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	916	(clk_io_peri_combined_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	958	(clk_usb_peri_combined_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	555	if (prim_mubi_pkg::mubi4_test_false_strict(calib_rdy[BaseIdx]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T5,T6

---

Assert Coverage for Module : clkmgr

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnownO_A	166028274	163848903	0	0
AllClkBypReqKnownO_A	166028274	163848903	0	0
CgEnKnownO_A	166028274	163848903	0	0
ClocksKownO_A	166028274	163848903	0	0
FpvSecCmClkMainAesCountCheck_A	166028274	44	0	0
FpvSecCmClkMainHmacCountCheck_A	166028274	49	0	0
FpvSecCmClkMainKmacCountCheck_A	166028274	48	0	0
FpvSecCmClkMainOtbnCountCheck_A	166028274	46	0	0
FpvSecCmRegWeOnehotCheck_A	166028274	80	0	0
IoClkBypReqKnownO_A	166028274	163848903	0	0
JitterEnableKnownO_A	166028274	163848903	0	0
LcCtrlClkBypAckKnownO_A	166028274	163848903	0	0
PwrMgrKnownO_A	166028274	163848903	0	0
TlAReadyKnownO_A	166028274	163848903	0	0
TlDValidKnownO_A	166028274	163848903	0	0

AlertsKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	163848903	0	0
T1	207315	207219	0	0
T2	490256	489261	0	0
T5	1627	1488	0	0
T6	1408	1351	0	0
T17	988	951	0	0
T18	952	939	0	0
T19	1437	1404	0	0
T20	1768	1724	0	0
T21	1051	938	0	0
T22	1907	1667	0	0

AllClkBypReqKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	163848903	0	0
T1	207315	207219	0	0
T2	490256	489261	0	0
T5	1627	1488	0	0
T6	1408	1351	0	0
T17	988	951	0	0
T18	952	939	0	0
T19	1437	1404	0	0
T20	1768	1724	0	0
T21	1051	938	0	0
T22	1907	1667	0	0

CgEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	163848903	0	0
T1	207315	207219	0	0
T2	490256	489261	0	0
T5	1627	1488	0	0
T6	1408	1351	0	0
T17	988	951	0	0
T18	952	939	0	0
T19	1437	1404	0	0
T20	1768	1724	0	0
T21	1051	938	0	0
T22	1907	1667	0	0

ClocksKownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	163848903	0	0
T1	207315	207219	0	0
T2	490256	489261	0	0
T5	1627	1488	0	0
T6	1408	1351	0	0
T17	988	951	0	0
T18	952	939	0	0
T19	1437	1404	0	0
T20	1768	1724	0	0
T21	1051	938	0	0
T22	1907	1667	0	0

FpvSecCmClkMainAesCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	44	0	0
T11	183798	0	0	0
T12	21670	0	0	0
T29	231798	0	0	0
T40	28631	20	0	0
T42	0	20	0	0
T43	0	4	0	0
T44	2071	0	0	0
T45	2964	0	0	0
T46	1020	0	0	0
T47	3187	0	0	0
T48	2136	0	0	0
T49	1305	0	0	0

FpvSecCmClkMainHmacCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	49	0	0
T11	183798	0	0	0
T12	21670	0	0	0
T29	231798	0	0	0
T40	28631	20	0	0
T42	0	20	0	0
T43	0	5	0	0
T44	2071	0	0	0
T45	2964	0	0	0
T46	1020	0	0	0
T47	3187	0	0	0
T48	2136	0	0	0
T49	1305	0	0	0
T50	0	4	0	0

FpvSecCmClkMainKmacCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	48	0	0
T11	183798	0	0	0
T12	21670	0	0	0
T29	231798	0	0	0
T40	28631	20	0	0
T42	0	19	0	0
T43	0	4	0	0
T44	2071	0	0	0
T45	2964	0	0	0
T46	1020	0	0	0
T47	3187	0	0	0
T48	2136	0	0	0
T49	1305	0	0	0
T50	0	5	0	0

FpvSecCmClkMainOtbnCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	46	0	0
T11	183798	0	0	0
T12	21670	0	0	0
T29	231798	0	0	0
T40	28631	19	0	0
T42	0	20	0	0
T43	0	4	0	0
T44	2071	0	0	0
T45	2964	0	0	0
T46	1020	0	0	0
T47	3187	0	0	0
T48	2136	0	0	0
T49	1305	0	0	0
T50	0	3	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	80	0	0
T11	183798	0	0	0
T12	21670	0	0	0
T29	231798	0	0	0
T40	28631	20	0	0
T42	0	20	0	0
T43	0	10	0	0
T44	2071	0	0	0
T45	2964	0	0	0
T46	1020	0	0	0
T47	3187	0	0	0
T48	2136	0	0	0
T49	1305	0	0	0
T50	0	10	0	0
T51	0	20	0	0

IoClkBypReqKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	163848903	0	0
T1	207315	207219	0	0
T2	490256	489261	0	0
T5	1627	1488	0	0
T6	1408	1351	0	0
T17	988	951	0	0
T18	952	939	0	0
T19	1437	1404	0	0
T20	1768	1724	0	0
T21	1051	938	0	0
T22	1907	1667	0	0

JitterEnableKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	163848903	0	0
T1	207315	207219	0	0
T2	490256	489261	0	0
T5	1627	1488	0	0
T6	1408	1351	0	0
T17	988	951	0	0
T18	952	939	0	0
T19	1437	1404	0	0
T20	1768	1724	0	0
T21	1051	938	0	0
T22	1907	1667	0	0

LcCtrlClkBypAckKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	163848903	0	0
T1	207315	207219	0	0
T2	490256	489261	0	0
T5	1627	1488	0	0
T6	1408	1351	0	0
T17	988	951	0	0
T18	952	939	0	0
T19	1437	1404	0	0
T20	1768	1724	0	0
T21	1051	938	0	0
T22	1907	1667	0	0

PwrMgrKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	163848903	0	0
T1	207315	207219	0	0
T2	490256	489261	0	0
T5	1627	1488	0	0
T6	1408	1351	0	0
T17	988	951	0	0
T18	952	939	0	0
T19	1437	1404	0	0
T20	1768	1724	0	0
T21	1051	938	0	0
T22	1907	1667	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	163848903	0	0
T1	207315	207219	0	0
T2	490256	489261	0	0
T5	1627	1488	0	0
T6	1408	1351	0	0
T17	988	951	0	0
T18	952	939	0	0
T19	1437	1404	0	0
T20	1768	1724	0	0
T21	1051	938	0	0
T22	1907	1667	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	163848903	0	0
T1	207315	207219	0	0
T2	490256	489261	0	0
T5	1627	1488	0	0
T6	1408	1351	0	0
T17	988	951	0	0
T18	952	939	0	0
T19	1437	1404	0	0
T20	1768	1724	0	0
T21	1051	938	0	0
T22	1907	1667	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		34	34	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	310	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	437	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
ALWAYS	552	5	5	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	743	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	765	1	1	100.00
CONT_ASSIGN	776	1	1	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	861	1	1	100.00
CONT_ASSIGN	903	1	1	100.00
CONT_ASSIGN	945	1	1	100.00
CONT_ASSIGN	1062	1	1	100.00
CONT_ASSIGN	1071	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
260	1	1
266	1	1
279	1	1
309	1	1
310	1	1
408	1	1
413	1	1
414	1	1
415	1	1
418	1	1
437	1	1
462	1	1
474	1	1
486	1	1
511	1	1
552	1	1
553	1	1
555	1	1
556	1	1
557	1	1
			MISSING_ELSE
699	1	1
710	1	1
721	1	1
732	1	1
743	1	1
754	1	1
765	1	1
776	1	1
819	1	1
861	1	1
903	1	1
945	1	1
1062	1	1
1071	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	146	136	93.15
Logical	146	136	93.15
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       37
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       46
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       55
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       65
 EXPRESSION (idle_i[0] == MuBi4True)
            ------------1-----------

-1-	Status	Tests
0	Covered	T5,T6,T2
1	Covered	T1,T5,T6

 LINE       65
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       75
 EXPRESSION (idle_i[1] == MuBi4True)
            ------------1-----------

-1-	Status	Tests
0	Covered	T5,T6,T2
1	Covered	T1,T5,T6

 LINE       75
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       85
 EXPRESSION (idle_i[2] == MuBi4True)
            ------------1-----------

-1-	Status	Tests
0	Covered	T5,T6,T2
1	Covered	T1,T5,T6

 LINE       85
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       95
 EXPRESSION (idle_i[3] == MuBi4True)
            ------------1-----------

-1-	Status	Tests
0	Covered	T5,T6,T2
1	Covered	T1,T5,T6

 LINE       95
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       119
 EXPRESSION (div_step_down_req_i == MuBi4True)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       119
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       130
 EXPRESSION (div_step_down_req_i == MuBi4True)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       130
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T6,T2,T19

 LINE       139
 EXPRESSION (cg_en_o.aon_peri == MuBi4True)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Not Covered

 LINE       143
 EXPRESSION (cg_en_o.aon_powerup == MuBi4True)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Not Covered

 LINE       147
 EXPRESSION (cg_en_o.aon_secure == MuBi4True)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Not Covered

 LINE       151
 EXPRESSION (cg_en_o.aon_timers == MuBi4True)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Not Covered

 LINE       155
 EXPRESSION (cg_en_o.io_powerup == MuBi4True)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Not Covered

 LINE       159
 EXPRESSION (cg_en_o.io_div2_powerup == MuBi4True)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Not Covered

 LINE       165
 EXPRESSION (cg_en_o.io_div4_powerup == MuBi4True)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Not Covered

 LINE       171
 EXPRESSION (cg_en_o.main_powerup == MuBi4True)
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Not Covered

 LINE       175
 EXPRESSION (cg_en_o.usb_powerup == MuBi4True)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Not Covered

 LINE       180
 EXPRESSION (cg_en_o.io_div2_infra == MuBi4True)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       189
 EXPRESSION (cg_en_o.io_div4_infra == MuBi4True)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       198
 EXPRESSION (cg_en_o.io_infra == MuBi4True)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       207
 EXPRESSION (cg_en_o.main_infra == MuBi4True)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       216
 EXPRESSION (cg_en_o.io_div4_secure == MuBi4True)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       225
 EXPRESSION (cg_en_o.main_secure == MuBi4True)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       234
 EXPRESSION (cg_en_o.io_div4_timers == MuBi4True)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       243
 EXPRESSION (cg_en_o.io_div2_peri == MuBi4True)
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       252
 EXPRESSION (cg_en_o.io_div4_peri == MuBi4True)
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       260
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault.q & reg2hw.alert_test.fatal_fault.qe)
                 ---------------1---------------   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T31,T32
1	0	Covered	T1,T5,T6
1	1	Covered	T18,T31,T32

 LINE       260
 SUB-EXPRESSION (reg2hw.alert_test.recov_fault.q & reg2hw.alert_test.recov_fault.qe)
                 ---------------1---------------   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T31,T32
1	0	Covered	T1,T5,T6
1	1	Covered	T18,T31,T32

 LINE       261
 EXPRESSION (cg_en_o.io_peri == MuBi4True)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       266
 EXPRESSION 
 Number  Term
      1  hw2reg.recov_err_code.io_measure_err.de | 
      2  hw2reg.recov_err_code.io_timeout_err.de | 
      3  hw2reg.recov_err_code.io_div2_measure_err.de | 
      4  hw2reg.recov_err_code.io_div2_timeout_err.de | 
      5  hw2reg.recov_err_code.io_div4_measure_err.de | 
      6  hw2reg.recov_err_code.io_div4_timeout_err.de | 
      7  hw2reg.recov_err_code.main_measure_err.de | 
      8  hw2reg.recov_err_code.main_timeout_err.de | 
      9  hw2reg.recov_err_code.usb_measure_err.de | 
     10  hw2reg.recov_err_code.usb_timeout_err.de | 
     11  hw2reg.recov_err_code.shadow_update_err.de)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T5,T6
0	0	0	0	0	0	0	0	0	0	1	Not Covered
0	0	0	0	0	0	0	0	0	1	0	Covered	T2,T3,T28
0	0	0	0	0	0	0	0	1	0	0	Covered	T1,T2,T23
0	0	0	0	0	0	0	1	0	0	0	Covered	T2,T3,T28
0	0	0	0	0	0	1	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	0	0	0	0	0	Covered	T2,T3,T10
0	0	0	0	1	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	1	0	0	0	0	0	0	0	Covered	T33,T34,T35
0	0	1	0	0	0	0	0	0	0	0	Covered	T1,T2,T3
0	1	0	0	0	0	0	0	0	0	0	Covered	T33,T34,T35
1	0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T23

 LINE       270
 EXPRESSION (cg_en_o.usb_peri == MuBi4True)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       279
 EXPRESSION (clkmgr.u_clk_main_aes_trans.sw_hint_synced || ((!clkmgr.u_clk_main_aes_trans.idle_valid)))
             ---------------------1--------------------    ---------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T36,T37
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       279
 EXPRESSION (cg_en_o.main_aes == MuBi4True)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       288
 EXPRESSION (clkmgr.u_clk_main_hmac_trans.sw_hint_synced || ((!clkmgr.u_clk_main_hmac_trans.idle_valid)))
             ---------------------1---------------------    ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T37,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       288
 EXPRESSION (cg_en_o.main_hmac == MuBi4True)
            ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       297
 EXPRESSION (clkmgr.u_clk_main_kmac_trans.sw_hint_synced || ((!clkmgr.u_clk_main_kmac_trans.idle_valid)))
             ---------------------1---------------------    ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T36,T37
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       297
 EXPRESSION (cg_en_o.main_kmac == MuBi4True)
            ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       306
 EXPRESSION (clkmgr.u_clk_main_otbn_trans.sw_hint_synced || ((!clkmgr.u_clk_main_otbn_trans.idle_valid)))
             ---------------------1---------------------    ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T36,T37
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       306
 EXPRESSION (cg_en_o.main_otbn == MuBi4True)
            ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       704
 EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
             -------1------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       715
 EXPRESSION (clk_main_en ? MuBi4False : MuBi4True)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       726
 EXPRESSION (clk_usb_en ? MuBi4False : MuBi4True)
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       737
 EXPRESSION (clk_io_en ? MuBi4False : MuBi4True)
             ----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       748
 EXPRESSION (clk_io_div2_en ? MuBi4False : MuBi4True)
             -------1------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       759
 EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
             -------1------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       770
 EXPRESSION (clk_main_en ? MuBi4False : MuBi4True)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       781
 EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
             -------1------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       819
 EXPRESSION (clk_io_div4_peri_sw_en & clk_io_div4_en)
             -----------1----------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T5,T17,T38
1	1	Covered	T1,T5,T6

 LINE       832
 EXPRESSION (clk_io_div4_peri_combined_en ? MuBi4False : MuBi4True)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       861
 EXPRESSION (clk_io_div2_peri_sw_en & clk_io_div2_en)
             -----------1----------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T5,T17,T38
1	1	Covered	T1,T5,T6

 LINE       874
 EXPRESSION (clk_io_div2_peri_combined_en ? MuBi4False : MuBi4True)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       903
 EXPRESSION (clk_io_peri_sw_en & clk_io_en)
             --------1--------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T5,T17,T38
1	1	Covered	T1,T5,T6

 LINE       916
 EXPRESSION (clk_io_peri_combined_en ? MuBi4False : MuBi4True)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       945
 EXPRESSION (clk_usb_peri_sw_en & clk_usb_en)
             ---------1--------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T5,T17,T38
1	1	Covered	T1,T5,T6

 LINE       958
 EXPRESSION (clk_usb_peri_combined_en ? MuBi4False : MuBi4True)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	106	106	100.00
Total Bits	660	660	100.00
Total Bits 0->1	330	330	100.00
Total Bits 1->0	330	330	100.00

Ports	106	106	100.00
Port Bits	660	660	100.00
Port Bits 0->1	330	330	100.00
Port Bits 1->0	330	330	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
rst_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
rst_shadowed_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
clk_main_i	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
rst_main_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
clk_io_i	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
rst_io_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
clk_usb_i	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
clk_aon_i	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
rst_aon_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
rst_io_div2_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
rst_io_div4_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
rst_root_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
rst_root_main_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
rst_root_io_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
rst_root_io_div2_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
rst_root_io_div4_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
rst_root_usb_ni	Yes	Yes	T2,T4,T27	Yes	T1,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T6,T2,T18	Yes	T1,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T22,T39	Yes	T2,T22,T39	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T19	Yes	T1,T2,T19	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	INPUT
tl_i.a_valid	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	INPUT
tl_o.a_ready	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	OUTPUT
tl_o.d_error	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T6,T2	Yes	T1,T6,T2	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T19	Yes	T1,T6,T2	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T6,*T2	Yes	T1,T6,T2	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T6,T2	Yes	T1,T6,T2	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T18	Yes	T1,T2,T18	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T18,T40,T31	Yes	T18,T40,T31	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T18	Yes	T1,T2,T18	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T18,T40,T31	Yes	T18,T40,T31	OUTPUT
pwr_i.usb_ip_clk_en	Yes	Yes	T5,T17,T38	Yes	T5,T17,T38	INPUT
pwr_i.io_ip_clk_en	Yes	Yes	T5,T17,T38	Yes	T5,T17,T38	INPUT
pwr_i.main_ip_clk_en	Yes	Yes	T5,T17,T38	Yes	T5,T17,T38	INPUT
pwr_o.usb_status	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
pwr_o.io_status	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
pwr_o.main_status	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
scanmode_i[3:0]	Yes	Yes	T6,T2,T19	Yes	T1,T6,T2	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T6,T2,T19	Yes	T6,T2,T19	INPUT
lc_clk_byp_req_i[3:0]	Yes	Yes	T6,T2,T19	Yes	T6,T2,T19	INPUT
lc_clk_byp_ack_o[3:0]	Yes	Yes	T2,T19,T20	Yes	T2,T19,T20	OUTPUT
io_clk_byp_req_o[3:0]	Yes	Yes	T2,T19,T20	Yes	T2,T19,T20	OUTPUT
io_clk_byp_ack_i[3:0]	Yes	Yes	T2,T19,T20	Yes	T2,T19,T20	INPUT
all_clk_byp_req_o[3:0]	Yes	Yes	T6,T2,T19	Yes	T6,T2,T19	OUTPUT
all_clk_byp_ack_i[3:0]	Yes	Yes	T6,T2,T19	Yes	T6,T2,T19	INPUT
hi_speed_sel_o[3:0]	Yes	Yes	T6,T2,T19	Yes	T1,T5,T6	OUTPUT
calib_rdy_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T23	INPUT
jitter_en_o[3:0]	Yes	Yes	T2,T3,T41	Yes	T2,T3,T41	OUTPUT
div_step_down_req_i[3:0]	Yes	Yes	T6,T2,T19	Yes	T6,T2,T19	INPUT
cg_en_o.usb_peri[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.io_peri[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.io_div2_peri[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.io_div4_peri[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.io_div4_timers[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.main_secure[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.io_div4_secure[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.io_div2_infra[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.io_infra[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.usb_infra[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.main_infra[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.io_div4_infra[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.main_otbn[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.main_kmac[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.main_hmac[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.main_aes[3:0]	Yes	Yes	T5,T2,T17	Yes	T1,T5,T6	OUTPUT
cg_en_o.aon_timers[3:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] This is driven by a constant, and unr doesn't detect it.
cg_en_o.aon_peri[3:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] This is driven by a constant, and unr doesn't detect it.
cg_en_o.aon_secure[3:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] This is driven by a constant, and unr doesn't detect it.
cg_en_o.io_div2_powerup[3:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] This is driven by a constant, and unr doesn't detect it.
cg_en_o.usb_powerup[3:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] This is driven by a constant, and unr doesn't detect it.
cg_en_o.io_powerup[3:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] This is driven by a constant, and unr doesn't detect it.
cg_en_o.main_powerup[3:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] This is driven by a constant, and unr doesn't detect it.
cg_en_o.aon_powerup[3:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] This is driven by a constant, and unr doesn't detect it.
cg_en_o.io_div4_powerup[3:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] This is driven by a constant, and unr doesn't detect it.
clocks_o.clk_usb_peri	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_io_peri	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_io_div2_peri	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_io_div4_peri	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_io_div4_timers	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_main_secure	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_io_div4_secure	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_io_div2_infra	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_io_infra	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_usb_infra	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_main_infra	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_io_div4_infra	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_main_otbn	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_main_kmac	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_main_hmac	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_main_aes	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_aon_timers	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_aon_peri	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_aon_secure	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_io_div2_powerup	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_usb_powerup	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_io_powerup	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_main_powerup	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_aon_powerup	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
clocks_o.clk_io_div4_powerup	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
TERNARY	704	2	2	100.00
TERNARY	715	2	2	100.00
TERNARY	726	2	2	100.00
TERNARY	737	2	2	100.00
TERNARY	748	2	2	100.00
TERNARY	759	2	2	100.00
TERNARY	770	2	2	100.00
TERNARY	781	2	2	100.00
TERNARY	832	2	2	100.00
TERNARY	874	2	2	100.00
TERNARY	916	2	2	100.00
TERNARY	958	2	2	100.00
IF	555	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	704	(clk_io_div4_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	715	(clk_main_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	726	(clk_usb_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	737	(clk_io_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	748	(clk_io_div2_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	759	(clk_io_div4_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	770	(clk_main_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	781	(clk_io_div4_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	832	(clk_io_div4_peri_combined_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	874	(clk_io_div2_peri_combined_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	916	(clk_io_peri_combined_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	958	(clk_usb_peri_combined_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	555	if (prim_mubi_pkg::mubi4_test_false_strict(calib_rdy[BaseIdx]))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnownO_A	166028274	163848903	0	0
AllClkBypReqKnownO_A	166028274	163848903	0	0
CgEnKnownO_A	166028274	163848903	0	0
ClocksKownO_A	166028274	163848903	0	0
FpvSecCmClkMainAesCountCheck_A	166028274	44	0	0
FpvSecCmClkMainHmacCountCheck_A	166028274	49	0	0
FpvSecCmClkMainKmacCountCheck_A	166028274	48	0	0
FpvSecCmClkMainOtbnCountCheck_A	166028274	46	0	0
FpvSecCmRegWeOnehotCheck_A	166028274	80	0	0
IoClkBypReqKnownO_A	166028274	163848903	0	0
JitterEnableKnownO_A	166028274	163848903	0	0
LcCtrlClkBypAckKnownO_A	166028274	163848903	0	0
PwrMgrKnownO_A	166028274	163848903	0	0
TlAReadyKnownO_A	166028274	163848903	0	0
TlDValidKnownO_A	166028274	163848903	0	0

AlertsKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	163848903	0	0
T1	207315	207219	0	0
T2	490256	489261	0	0
T5	1627	1488	0	0
T6	1408	1351	0	0
T17	988	951	0	0
T18	952	939	0	0
T19	1437	1404	0	0
T20	1768	1724	0	0
T21	1051	938	0	0
T22	1907	1667	0	0

AllClkBypReqKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	163848903	0	0
T1	207315	207219	0	0
T2	490256	489261	0	0
T5	1627	1488	0	0
T6	1408	1351	0	0
T17	988	951	0	0
T18	952	939	0	0
T19	1437	1404	0	0
T20	1768	1724	0	0
T21	1051	938	0	0
T22	1907	1667	0	0

CgEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	163848903	0	0
T1	207315	207219	0	0
T2	490256	489261	0	0
T5	1627	1488	0	0
T6	1408	1351	0	0
T17	988	951	0	0
T18	952	939	0	0
T19	1437	1404	0	0
T20	1768	1724	0	0
T21	1051	938	0	0
T22	1907	1667	0	0

ClocksKownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	163848903	0	0
T1	207315	207219	0	0
T2	490256	489261	0	0
T5	1627	1488	0	0
T6	1408	1351	0	0
T17	988	951	0	0
T18	952	939	0	0
T19	1437	1404	0	0
T20	1768	1724	0	0
T21	1051	938	0	0
T22	1907	1667	0	0

FpvSecCmClkMainAesCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	44	0	0
T11	183798	0	0	0
T12	21670	0	0	0
T29	231798	0	0	0
T40	28631	20	0	0
T42	0	20	0	0
T43	0	4	0	0
T44	2071	0	0	0
T45	2964	0	0	0
T46	1020	0	0	0
T47	3187	0	0	0
T48	2136	0	0	0
T49	1305	0	0	0

FpvSecCmClkMainHmacCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	49	0	0
T11	183798	0	0	0
T12	21670	0	0	0
T29	231798	0	0	0
T40	28631	20	0	0
T42	0	20	0	0
T43	0	5	0	0
T44	2071	0	0	0
T45	2964	0	0	0
T46	1020	0	0	0
T47	3187	0	0	0
T48	2136	0	0	0
T49	1305	0	0	0
T50	0	4	0	0

FpvSecCmClkMainKmacCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	48	0	0
T11	183798	0	0	0
T12	21670	0	0	0
T29	231798	0	0	0
T40	28631	20	0	0
T42	0	19	0	0
T43	0	4	0	0
T44	2071	0	0	0
T45	2964	0	0	0
T46	1020	0	0	0
T47	3187	0	0	0
T48	2136	0	0	0
T49	1305	0	0	0
T50	0	5	0	0

FpvSecCmClkMainOtbnCountCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	46	0	0
T11	183798	0	0	0
T12	21670	0	0	0
T29	231798	0	0	0
T40	28631	19	0	0
T42	0	20	0	0
T43	0	4	0	0
T44	2071	0	0	0
T45	2964	0	0	0
T46	1020	0	0	0
T47	3187	0	0	0
T48	2136	0	0	0
T49	1305	0	0	0
T50	0	3	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	80	0	0
T11	183798	0	0	0
T12	21670	0	0	0
T29	231798	0	0	0
T40	28631	20	0	0
T42	0	20	0	0
T43	0	10	0	0
T44	2071	0	0	0
T45	2964	0	0	0
T46	1020	0	0	0
T47	3187	0	0	0
T48	2136	0	0	0
T49	1305	0	0	0
T50	0	10	0	0
T51	0	20	0	0

IoClkBypReqKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	163848903	0	0
T1	207315	207219	0	0
T2	490256	489261	0	0
T5	1627	1488	0	0
T6	1408	1351	0	0
T17	988	951	0	0
T18	952	939	0	0
T19	1437	1404	0	0
T20	1768	1724	0	0
T21	1051	938	0	0
T22	1907	1667	0	0

JitterEnableKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	163848903	0	0
T1	207315	207219	0	0
T2	490256	489261	0	0
T5	1627	1488	0	0
T6	1408	1351	0	0
T17	988	951	0	0
T18	952	939	0	0
T19	1437	1404	0	0
T20	1768	1724	0	0
T21	1051	938	0	0
T22	1907	1667	0	0

LcCtrlClkBypAckKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	163848903	0	0
T1	207315	207219	0	0
T2	490256	489261	0	0
T5	1627	1488	0	0
T6	1408	1351	0	0
T17	988	951	0	0
T18	952	939	0	0
T19	1437	1404	0	0
T20	1768	1724	0	0
T21	1051	938	0	0
T22	1907	1667	0	0

PwrMgrKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	163848903	0	0
T1	207315	207219	0	0
T2	490256	489261	0	0
T5	1627	1488	0	0
T6	1408	1351	0	0
T17	988	951	0	0
T18	952	939	0	0
T19	1437	1404	0	0
T20	1768	1724	0	0
T21	1051	938	0	0
T22	1907	1667	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	163848903	0	0
T1	207315	207219	0	0
T2	490256	489261	0	0
T5	1627	1488	0	0
T6	1408	1351	0	0
T17	988	951	0	0
T18	952	939	0	0
T19	1437	1404	0	0
T20	1768	1724	0	0
T21	1051	938	0	0
T22	1907	1667	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	163848903	0	0
T1	207315	207219	0	0
T2	490256	489261	0	0
T5	1627	1488	0	0
T6	1408	1351	0	0
T17	988	951	0	0
T18	952	939	0	0
T19	1437	1404	0	0
T20	1768	1724	0	0
T21	1051	938	0	0
T22	1907	1667	0	0