Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	830141370	79147	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	830141370	79147	0	0
T1	1036575	109	0	0
T2	2451280	1758	0	0
T3	0	1811	0	0
T5	8135	0	0	0
T6	7040	0	0	0
T10	0	1350	0	0
T11	0	478	0	0
T12	0	227	0	0
T13	0	112	0	0
T14	0	210	0	0
T15	0	205	0	0
T16	0	2001	0	0
T17	4940	0	0	0
T18	4760	0	0	0
T19	7185	0	0	0
T20	8840	0	0	0
T21	5255	0	0	0
T22	9535	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	166028274	11710	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	11710	0	0
T1	207315	14	0	0
T2	490256	260	0	0
T3	0	240	0	0
T5	1627	0	0	0
T6	1408	0	0	0
T10	0	219	0	0
T11	0	64	0	0
T12	0	37	0	0
T13	0	14	0	0
T14	0	28	0	0
T15	0	30	0	0
T16	0	297	0	0
T17	988	0	0	0
T18	952	0	0	0
T19	1437	0	0	0
T20	1768	0	0	0
T21	1051	0	0	0
T22	1907	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	166028274	15892	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	15892	0	0
T1	207315	22	0	0
T2	490256	353	0	0
T3	0	365	0	0
T5	1627	0	0	0
T6	1408	0	0	0
T10	0	273	0	0
T11	0	97	0	0
T12	0	47	0	0
T13	0	23	0	0
T14	0	41	0	0
T15	0	41	0	0
T16	0	411	0	0
T17	988	0	0	0
T18	952	0	0	0
T19	1437	0	0	0
T20	1768	0	0	0
T21	1051	0	0	0
T22	1907	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	166028274	24186	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	24186	0	0
T1	207315	37	0	0
T2	490256	535	0	0
T3	0	606	0	0
T5	1627	0	0	0
T6	1408	0	0	0
T10	0	366	0	0
T11	0	160	0	0
T12	0	61	0	0
T13	0	38	0	0
T14	0	74	0	0
T15	0	64	0	0
T16	0	648	0	0
T17	988	0	0	0
T18	952	0	0	0
T19	1437	0	0	0
T20	1768	0	0	0
T21	1051	0	0	0
T22	1907	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	166028274	11522	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	11522	0	0
T1	207315	14	0	0
T2	490256	253	0	0
T3	0	232	0	0
T5	1627	0	0	0
T6	1408	0	0	0
T10	0	217	0	0
T11	0	62	0	0
T12	0	36	0	0
T13	0	14	0	0
T14	0	26	0	0
T15	0	29	0	0
T16	0	254	0	0
T17	988	0	0	0
T18	952	0	0	0
T19	1437	0	0	0
T20	1768	0	0	0
T21	1051	0	0	0
T22	1907	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	166028274	15837	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	15837	0	0
T1	207315	22	0	0
T2	490256	357	0	0
T3	0	368	0	0
T5	1627	0	0	0
T6	1408	0	0	0
T10	0	275	0	0
T11	0	95	0	0
T12	0	46	0	0
T13	0	23	0	0
T14	0	41	0	0
T15	0	41	0	0
T16	0	391	0	0
T17	988	0	0	0
T18	952	0	0	0
T19	1437	0	0	0
T20	1768	0	0	0
T21	1051	0	0	0
T22	1907	0	0	0