Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T4,T27

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	166028274	163711632	0	0
AllClkBypReqTrue_A	166028274	134974	0	0
IoClkBypReqFalse_A	166028274	163628533	0	2415
IoClkBypReqTrue_A	166028274	213479	0	0
LcClkBypAckFalse_A	166028274	163722322	0	0
LcClkBypAckTrue_A	166028274	124284	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	163711632	0	0
T1	207315	207218	0	0
T2	490256	489112	0	0
T5	1627	1487	0	0
T6	1408	1250	0	0
T17	988	950	0	0
T18	952	938	0	0
T19	1437	1403	0	0
T20	1768	1558	0	0
T21	1051	937	0	0
T22	1907	1549	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	134974	0	0
T2	490256	1478	0	0
T3	0	1563	0	0
T6	1408	100	0	0
T17	988	0	0	0
T18	952	0	0	0
T19	1437	0	0	0
T20	1768	165	0	0
T21	1051	0	0	0
T22	1907	117	0	0
T39	2305	205	0	0
T61	2282	191	0	0
T66	0	127	0	0
T84	0	9	0	0
T107	0	32	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	163628533	0	2415
T1	207315	207216	0	3
T2	490256	489002	0	3
T5	1627	1485	0	3
T6	1408	1348	0	3
T17	988	948	0	3
T18	952	936	0	3
T19	1437	1169	0	3
T20	1768	1418	0	3
T21	1051	842	0	3
T22	1907	1623	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	213479	0	0
T2	490256	2566	0	0
T4	16503	0	0	0
T17	988	0	0	0
T18	952	0	0	0
T19	1437	232	0	0
T20	1768	303	0	0
T21	1051	93	0	0
T22	1907	41	0	0
T39	2305	509	0	0
T61	2282	252	0	0
T66	0	379	0	0
T84	0	225	0	0
T107	0	61	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	163722322	0	0
T1	207315	207218	0	0
T2	490256	489094	0	0
T5	1627	1487	0	0
T6	1408	1350	0	0
T17	988	950	0	0
T18	952	938	0	0
T19	1437	1360	0	0
T20	1768	1636	0	0
T21	1051	855	0	0
T22	1907	1628	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	124284	0	0
T2	490256	1662	0	0
T4	16503	0	0	0
T17	988	0	0	0
T18	952	0	0	0
T19	1437	43	0	0
T20	1768	87	0	0
T21	1051	82	0	0
T22	1907	38	0	0
T39	2305	223	0	0
T61	2282	129	0	0
T66	0	178	0	0
T84	0	100	0	0
T107	0	46	0	0