Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	15987	0	0
TransStop_A	2147483647	8156	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15987	0	0
T2	423904	230	0	0
T3	0	252	0	0
T4	275060	0	0	0
T10	0	124	0	0
T17	13692	0	0	0
T18	76212	0	0	0
T19	23968	0	0	0
T20	29480	0	0	0
T21	8416	0	0	0
T22	7632	0	0	0
T36	0	5	0	0
T37	0	16	0	0
T39	38428	0	0	0
T41	0	4	0	0
T45	0	45	0	0
T46	0	7	0	0
T47	0	20	0	0
T61	9220	0	0	0
T69	0	36	0	0
T70	0	10	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8156	0	0
T2	423904	141	0	0
T3	0	115	0	0
T4	275060	0	0	0
T10	0	57	0	0
T17	13692	0	0	0
T18	76212	0	0	0
T19	23968	0	0	0
T20	29480	0	0	0
T21	8416	0	0	0
T22	7632	0	0	0
T36	0	5	0	0
T37	0	5	0	0
T39	38428	0	0	0
T41	0	4	0	0
T45	0	20	0	0
T47	0	22	0	0
T49	0	1	0	0
T61	9220	0	0	0
T69	0	17	0	0
T70	0	6	0	0
T108	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	544415049	4056	0	0
TransStop_A	544415049	2104	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544415049	4056	0	0
T2	105976	58	0	0
T3	0	61	0	0
T4	68765	0	0	0
T10	0	30	0	0
T17	3423	0	0	0
T18	19053	0	0	0
T19	5992	0	0	0
T20	7370	0	0	0
T21	2104	0	0	0
T22	1908	0	0	0
T36	0	2	0	0
T37	0	3	0	0
T39	9607	0	0	0
T41	0	1	0	0
T45	0	13	0	0
T46	0	2	0	0
T61	2305	0	0	0
T69	0	11	0	0
T70	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544415049	2104	0	0
T2	105976	40	0	0
T3	0	28	0	0
T4	68765	0	0	0
T10	0	12	0	0
T17	3423	0	0	0
T18	19053	0	0	0
T19	5992	0	0	0
T20	7370	0	0	0
T21	2104	0	0	0
T22	1908	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T39	9607	0	0	0
T41	0	1	0	0
T45	0	7	0	0
T47	0	5	0	0
T61	2305	0	0	0
T69	0	7	0	0
T70	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	544415049	3980	0	0
TransStop_A	544415049	1993	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544415049	3980	0	0
T2	105976	59	0	0
T3	0	62	0	0
T4	68765	0	0	0
T10	0	28	0	0
T17	3423	0	0	0
T18	19053	0	0	0
T19	5992	0	0	0
T20	7370	0	0	0
T21	2104	0	0	0
T22	1908	0	0	0
T37	0	3	0	0
T39	9607	0	0	0
T41	0	1	0	0
T45	0	11	0	0
T46	0	3	0	0
T47	0	8	0	0
T61	2305	0	0	0
T69	0	7	0	0
T70	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544415049	1993	0	0
T2	105976	37	0	0
T3	0	28	0	0
T4	68765	0	0	0
T10	0	13	0	0
T17	3423	0	0	0
T18	19053	0	0	0
T19	5992	0	0	0
T20	7370	0	0	0
T21	2104	0	0	0
T22	1908	0	0	0
T39	9607	0	0	0
T41	0	1	0	0
T45	0	6	0	0
T47	0	4	0	0
T49	0	1	0	0
T61	2305	0	0	0
T69	0	2	0	0
T70	0	1	0	0
T108	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	544415049	3978	0	0
TransStop_A	544415049	2026	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544415049	3978	0	0
T2	105976	59	0	0
T3	0	62	0	0
T4	68765	0	0	0
T10	0	35	0	0
T17	3423	0	0	0
T18	19053	0	0	0
T19	5992	0	0	0
T20	7370	0	0	0
T21	2104	0	0	0
T22	1908	0	0	0
T36	0	2	0	0
T37	0	5	0	0
T39	9607	0	0	0
T41	0	1	0	0
T45	0	12	0	0
T46	0	2	0	0
T61	2305	0	0	0
T69	0	8	0	0
T70	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544415049	2026	0	0
T2	105976	32	0	0
T3	0	26	0	0
T4	68765	0	0	0
T10	0	17	0	0
T17	3423	0	0	0
T18	19053	0	0	0
T19	5992	0	0	0
T20	7370	0	0	0
T21	2104	0	0	0
T22	1908	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T39	9607	0	0	0
T41	0	1	0	0
T45	0	5	0	0
T47	0	6	0	0
T61	2305	0	0	0
T69	0	3	0	0
T70	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	544415049	3973	0	0
TransStop_A	544415049	2033	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544415049	3973	0	0
T2	105976	54	0	0
T3	0	67	0	0
T4	68765	0	0	0
T10	0	31	0	0
T17	3423	0	0	0
T18	19053	0	0	0
T19	5992	0	0	0
T20	7370	0	0	0
T21	2104	0	0	0
T22	1908	0	0	0
T36	0	1	0	0
T37	0	5	0	0
T39	9607	0	0	0
T41	0	1	0	0
T45	0	9	0	0
T47	0	12	0	0
T61	2305	0	0	0
T69	0	10	0	0
T70	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544415049	2033	0	0
T2	105976	32	0	0
T3	0	33	0	0
T4	68765	0	0	0
T10	0	15	0	0
T17	3423	0	0	0
T18	19053	0	0	0
T19	5992	0	0	0
T20	7370	0	0	0
T21	2104	0	0	0
T22	1908	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	9607	0	0	0
T41	0	1	0	0
T45	0	2	0	0
T47	0	7	0	0
T61	2305	0	0	0
T69	0	5	0	0
T70	0	3	0	0