Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	166028274	21669039	0	63

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166028274	21669039	0	63
T1	207315	12887	0	1
T2	490256	900729	0	0
T3	0	624746	0	0
T5	1627	0	0	0
T6	1408	0	0	0
T10	0	193372	0	0
T11	0	59952	0	1
T12	0	14606	0	1
T13	0	13549	0	1
T15	0	0	0	1
T17	988	0	0	0
T18	952	0	0	0
T19	1437	0	0	0
T20	1768	0	0	0
T21	1051	0	0	0
T22	1907	0	0	0
T23	0	1281	0	1
T24	0	687	0	1
T25	0	671	0	1
T109	0	0	0	1
T110	0	0	0	1