Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	167000745	5364375	0	0
clk_enables_rd_A	167000745	42442	0	0
clk_hints_rd_A	167000745	37363	0	0
extclk_ctrl_rd_A	167000745	47079	0	0
extclk_ctrl_regwen_rd_A	167000745	36821	0	0
jitter_enable_rd_A	167000745	54998	0	0
jitter_regwen_rd_A	167000745	40114	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167000745	5364375	0	0
T2	490256	243198	0	0
T3	0	165697	0	0
T4	16503	0	0	0
T10	0	136741	0	0
T16	0	177607	0	0
T17	988	0	0	0
T18	952	0	0	0
T19	1437	0	0	0
T20	1768	0	0	0
T21	1051	0	0	0
T22	1907	0	0	0
T26	0	55216	0	0
T30	0	59560	0	0
T39	2305	0	0	0
T61	2282	0	0	0
T62	0	95041	0	0
T63	0	53166	0	0
T64	0	71961	0	0
T65	0	60955	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167000745	42442	0	0
T13	501744	4	0	0
T26	0	2219	0	0
T34	0	4659	0	0
T63	0	1120	0	0
T64	0	3007	0	0
T74	37773	0	0	0
T85	1425	0	0	0
T128	0	3	0	0
T129	0	7	0	0
T130	0	6	0	0
T131	0	1	0	0
T132	0	7	0	0
T133	2333	0	0	0
T134	1040	0	0	0
T135	1802	0	0	0
T136	998	0	0	0
T137	856	0	0	0
T138	1719	0	0	0
T139	1127	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167000745	37363	0	0
T13	501744	1	0	0
T26	0	1764	0	0
T34	0	3848	0	0
T63	0	1078	0	0
T64	0	2592	0	0
T74	37773	0	0	0
T85	1425	0	0	0
T128	0	3	0	0
T129	0	4	0	0
T130	0	2	0	0
T132	0	5	0	0
T133	2333	0	0	0
T134	1040	0	0	0
T135	1802	0	0	0
T136	998	0	0	0
T137	856	0	0	0
T138	1719	0	0	0
T139	1127	0	0	0
T140	0	893	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167000745	47079	0	0
T4	16503	0	0	0
T20	1768	37	0	0
T21	1051	0	0	0
T22	1907	13	0	0
T23	31688	0	0	0
T36	1356	0	0	0
T39	2305	0	0	0
T48	0	41	0	0
T61	2282	0	0	0
T66	2293	45	0	0
T84	2060	0	0	0
T97	0	26	0	0
T141	0	26	0	0
T142	0	12	0	0
T143	0	44	0	0
T144	0	16	0	0
T145	0	35	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167000745	36821	0	0
T26	0	1840	0	0
T31	1172	0	0	0
T32	1324	0	0	0
T34	0	4276	0	0
T63	0	954	0	0
T64	0	2757	0	0
T97	5583	6	0	0
T111	91590	0	0	0
T140	0	945	0	0
T146	0	64	0	0
T147	0	19	0	0
T148	0	2772	0	0
T149	0	27	0	0
T150	1938	0	0	0
T151	1025	0	0	0
T152	888	0	0	0
T153	1066	0	0	0
T154	1820	0	0	0
T155	1065	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167000745	54998	0	0
T13	501744	218	0	0
T26	0	2538	0	0
T34	0	5389	0	0
T63	0	1606	0	0
T64	0	3010	0	0
T74	37773	0	0	0
T85	1425	0	0	0
T128	0	84	0	0
T129	0	124	0	0
T130	0	152	0	0
T131	0	38	0	0
T132	0	106	0	0
T133	2333	0	0	0
T134	1040	0	0	0
T135	1802	0	0	0
T136	998	0	0	0
T137	856	0	0	0
T138	1719	0	0	0
T139	1127	0	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167000745	40114	0	0
T7	70221	0	0	0
T26	185781	2288	0	0
T34	0	4603	0	0
T63	0	1029	0	0
T64	0	2953	0	0
T76	47593	0	0	0
T86	2105	0	0	0
T140	0	1244	0	0
T148	0	3197	0	0
T156	0	1147	0	0
T157	0	1780	0	0
T158	0	3467	0	0
T159	0	5426	0	0
T160	2650	0	0	0
T161	1531	0	0	0
T162	2001	0	0	0
T163	1595	0	0	0
T164	1365	0	0	0
T165	1419	0	0	0