Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T19
1	0	Covered	T2,T19,T20
1	1	Covered	T6,T2,T19

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	511072887	4479	0	0
g_div2.Div2Whole_A	511072887	5280	0	0
g_div4.Div4Stepped_A	255360011	4396	0	0
g_div4.Div4Whole_A	255360011	5009	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511072887	4479	0	0
T2	993946	69	0	0
T6	5636	8	0	0
T17	3543	0	0	0
T18	18291	0	0	0
T19	5752	2	0	0
T20	7076	5	0	0
T21	2020	3	0	0
T22	1832	1	0	0
T39	9222	9	0	0
T61	2213	3	0	0
T66	0	7	0	0
T84	0	4	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511072887	5280	0	0
T2	993946	87	0	0
T6	5636	8	0	0
T17	3543	0	0	0
T18	18291	0	0	0
T19	5752	5	0	0
T20	7076	4	0	0
T21	2020	3	0	0
T22	1832	3	0	0
T39	9222	10	0	0
T61	2213	8	0	0
T66	0	7	0	0
T84	0	6	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255360011	4396	0	0
T2	496693	69	0	0
T6	2966	8	0	0
T17	1753	0	0	0
T18	9085	0	0	0
T19	2939	2	0	0
T20	5753	5	0	0
T21	1025	3	0	0
T22	904	1	0	0
T39	5282	9	0	0
T61	1143	3	0	0
T66	0	7	0	0
T84	0	3	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255360011	5009	0	0
T2	496693	87	0	0
T6	2966	8	0	0
T17	1753	0	0	0
T18	9085	0	0	0
T19	2939	5	0	0
T20	5753	4	0	0
T21	1025	3	0	0
T22	904	3	0	0
T39	5282	10	0	0
T61	1143	8	0	0
T66	0	7	0	0
T84	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T19
1	0	Covered	T2,T19,T20
1	1	Covered	T6,T2,T19

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	511072887	4479	0	0
g_div2.Div2Whole_A	511072887	5280	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511072887	4479	0	0
T2	993946	69	0	0
T6	5636	8	0	0
T17	3543	0	0	0
T18	18291	0	0	0
T19	5752	2	0	0
T20	7076	5	0	0
T21	2020	3	0	0
T22	1832	1	0	0
T39	9222	9	0	0
T61	2213	3	0	0
T66	0	7	0	0
T84	0	4	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511072887	5280	0	0
T2	993946	87	0	0
T6	5636	8	0	0
T17	3543	0	0	0
T18	18291	0	0	0
T19	5752	5	0	0
T20	7076	4	0	0
T21	2020	3	0	0
T22	1832	3	0	0
T39	9222	10	0	0
T61	2213	8	0	0
T66	0	7	0	0
T84	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T19
1	0	Covered	T2,T19,T20
1	1	Covered	T6,T2,T19

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	255360011	4396	0	0
g_div4.Div4Whole_A	255360011	5009	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255360011	4396	0	0
T2	496693	69	0	0
T6	2966	8	0	0
T17	1753	0	0	0
T18	9085	0	0	0
T19	2939	2	0	0
T20	5753	5	0	0
T21	1025	3	0	0
T22	904	1	0	0
T39	5282	9	0	0
T61	1143	3	0	0
T66	0	7	0	0
T84	0	3	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255360011	5009	0	0
T2	496693	87	0	0
T6	2966	8	0	0
T17	1753	0	0	0
T18	9085	0	0	0
T19	2939	5	0	0
T20	5753	4	0	0
T21	1025	3	0	0
T22	904	3	0	0
T39	5282	10	0	0
T61	1143	8	0	0
T66	0	7	0	0
T84	0	6	0	0